ELX304-Topic5-Lesson 4 - pr2 PDF

ElectronicSystemsDesign(ELX304) Lesson4CMOSAnaloguedesign
UniversityofSunderland Page1
LESSON4
CMOSANALOGUEDESIGN
INTRODUCTION
Thislessondiscussesthoseanalogueapplicationssuitablefor
implementationusingVLSIandthemethodologiesusedfortheir
construction.
YOURAIMS
Attheendofthislesson,youshouldbeableto
appraisecritically theperformance/operationofconversion
devicesbetweentheanalogueanddigitaldomains
analysealternativestructuresusedinanalogueVLSICircuits.
STUDYADVICE
Thisparticularlessonisdesignedtobeselfcontained.However,
thefollowingreferenceswillprovideadditionalsupportmaterial.
SUPPORTMATERIAL
Allen,P.E., Holberg,D.R. (2002)CMOSAnalogCircuitDesign.
OxfordUniversityPress.
Geiger,R.L.,Allen,P.E.&Strader,N.R. (1990) VLSI,Design
techniquesforAnaloganddigitalcircuits.McGrawHill.(Chapter
8)
Ismail,M.,Fiez,T. (1994) AnalogueVLSI:Signaland
InformationProcessing.McGrawHill.(Chapter9)
4.1 ANALOGUEVLSIDESIGN
TodatewehavemainlyconsideredtheconstructionofMOS
transistorsfortheimplementationofdigitallogic.Inthislesson
wewillbeinvestigatingtheuseofthesetechnologiesfor
Analogueapplications.However,inpreviousmodulesanalogue
circuitdesignhasinvolvedtheuseof
i) PassiveTechnology:CircuitsconstructedfromResistors,
Capacitorsand Inductorsalone,forexamplefilters.
ii) ActiveTechnology:Circuitsbuiltusingelectronic
amplifiers,forexampleoperationalamplifiers.
InVLSItermspassivetechnologyisnotconsideredascircuits
builtentirelyfromresistorsandcapacitorsarewastefulof
availablesiliconarea,comparedwithtransistors,andinductor
constructionisproblematic.
However,amplifierconstructioncanbeachievedusingBipolar
JunctionTechnologyorCMOStechnologyandsothebasic
buildingblocksformorecomplexapplicationsareavailabletothe
designerforconstructionwithinVLSI.Theoperationalamplifier
isaparticularlyusefuldeviceasitisahighgaindifferential
amplifierwhichideallyhasthecharacteristicsofhighinput
impedance,lowoutputimpedance,highbandwidthandlowoffset.
Theaboveschematicshowsthatinpractice,thisisachievedusing
abasicdifferentialamplifierinconjunctionwithfurthercircuitry
specificallydesignedtoimproveitsoverallcharacteristics.
Althoughthislessonwillnotaddressoperationalamplifierdesign
thefollowingtable,inconjunctionwiththerecommended
reading,identifiescircuitdesignsforanyonewishingto
investigatefurther.
Differential
Amplifier
Stage
HighGain
Amplification
Stage
Output
Buffer
Differential
Input
Compensation
Circuitry
Bias
Circuitry
Output
CurrentSink
CurrentMirrorLoad DifferentialAmplifier
SourceCoupledPair
Inverter HighGainStage
CurrentSinkLoad
CurrentSource BiasCircuit
CurrentMirror
SourceFollower
Operational
Amplifier
OutputBuffer
CurrentSinkLoad
4.1.1 APPLICATIONTECHNOLOGIES
TheVLSIdesigntechnologydescribedinpreviouslessonshas
allowedthedesignofdigitalApplicationSpecificIntegrated
Circuits(ASIC's)inhouseusingsuitableCADsoftware.
Unfortunatelyseveralproblemsexistusingtheabovetechnology
asitisspecificallydevelopedfordigitalcomputationandstorage.
Themainproblembeinglowintegrationlevels(largesilicon
usage)requiredforanalogueICimplementationsinceituses
hybridtechnologyinitsconstruction.
Morerecently,withtheadventofdoublepolysiliconCMOS
(BiMOS)technology,someoftheseproblemshavebeen
overcome.Inparticular,theconstructionofhighvaluecapacitors
inamuchsmallerareathanispossiblewithmetalsilicon
capacitorsispossiblebyusingtwopolysiliconlayersas
conductingplates.InadditionBipolarTransistor's,thebasic
buildingblockoflinearanalogueIC's,mayalsobeconstructedon
thesamechipprovidingincreasedspeed,improvednoise
performanceandmoreprecisecharacteristicsthanisavailable
usingCMOStechnologyalone.
Asanaloguesignalsexistincontinuoustimewithcontinuous
amplitudesthenthepreviouscircuitswillbeexpectedtoworkin
theactive,linear,regionwherepowerconsumptionisrelatively
high.However,analternativesolutionistouselogicswitching
athighfrequencies,withsomeformofaveraging,sothatthe
digitalsystemappearscontinuous.Thefollowingtableillustrates
suitabletechnologiesforsignalprocessingapplications:
MOSDigitalLogic
MOSAnalogue
BipolarDigitalLogic
BipolarAnalogue
BiCMOS
Optical
GalliumArsenide
Frequency(Hz)
1 10 100 1K 10K 100K 1M 10M 100M 1G 10G
Seismic Audio Telecommunications Microwave
100G
4.2 SIGNALPROCESSING
Insignalprocessingthereisamajorneedtobeableto
communicatebetweentheAnalogueandDigitaldomainsinorder
tofullyutilisethebenefitsaffordedbybothtechnologies.In
particular:
i) DataAcquisitionSystems
Thecollectionofcontinuoussignals(audioandvideo
signals,measurementsviatransducers,etc...) andtheir
subsequentanalysis/storagewithindigitaldevices
(computers,controllers,disks,memories,etc...).For
example:
Multiplexer
Analogue
Signals
Sample
Hold
&
Analogue
to
Digital
Converter
nbit
Signal
Digital
ii) DigitalControlSystems
Inordertocompletethefeedbackcontrolloopwerequire
theabilitytomanipulateaprocessinput,viaactuators,
usingasignalgeneratedbyacomputercontrolalgorithm.
Thatis:
Analogue
Analogue
to
Digital
Converter
nbit
Signal
Digital
Filter
Signal
Amplifier
OptionalDevices
Thefollowingsectionswillinvestigatecommonlyusedcircuits
forconstructingtheelementsidentifiedabove.
4.2.1 DIGITALTOANALOGUE
CONVERTERS(DAC'S)
Thedigitaltoanalogueconverter,DAC,isrequired toprovidean
analogueoutputwhichisproportionaltoan nbitdigitalcode
input.Thatistoproduceauniquevoltagelevelforeachofthe
possible2
n
digitalcodesthatcanoccurwhenusingan nbit
converter.Althoughtherearenumerousmethodsofachievingthis
theyallsharethefollowingbasicstructure:
nbit Signal Digital
Scaling
Network
D.V
ref
Output
Amplifier
V
out
Binary
Latches
b
1
b
2
b
3
b
n
V
ref Voltage
Reference
whereb
1
istheMostSignificantBit(MSB)andb
n
theLeast
SignificantBit(LSB)which,whenswitched,leadtochangesin
analoguevoltageequivalentto:
MSB:
V
b
range
2
1
@
and where V
range
=Vout
max
Vout
min
LSB:
V
b
n
range
n
2
@
andthereforetheDACoutputwillapproachthatofanideal
analogueoutputasn .
Notethattherangeisactuallycoveredby 2
n
1bitchangesin
levelthenthemaximumoutputvoltageobtainablefromaDACis
generally
( )

- = -
n range
n
n
range
V 2
V
2
1
1 1
2
andthereforefallsshortbyoneLSB.Thisiscompensatedforin
practicebysomegain/offsettrimmingoutsideofthechip.
4.2.1.1 SWITCHEDRESISTORNETWORKS
(CURRENTSCALINGNETWORKS)
(a) BinaryWeighted
V
ref
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
R
2R
4R
8R
16R
2R
7
6
2R
5
2R
_
+
R
f
V
o
I
I 1
I2
I3
I4
I5
I6
I7
I8
Heredigitalbitswhicharelogichighswitchthereferencevoltage
V
ref
ontothesummingamplifier,viaanappropriatelyweighted
resistance,toprovidetherequiredamountofcurrent.Bitswhich
arelogiclowgroundtheappropriateinputandproducenocurrent.
Thusthei'thbitproducesanassociatedoutputvoltageof
i i
f
ref
b
R
R
V .
2
.
1

-
-
Thus,bysettingtherequiredR
f
/R ratioandV
ref
toprovidethe
requiredoutputrangethen (herewith R
f
=R/2):

+ + + + + - =
n
n
ref o
b b b b b
V V
2
....
16 8 4 2
4 3 2 1
ThemajorproblemwiththeVLSIconstructionoftheabove
networkisthespreadintherequiredvaluesoftheresistance's
especiallyasthenumberofbitsnincreases.Thiscausesa
doublingofthemaximumresistorsizeforeachbitincreaseinthe
digitalwordandtherefore,adoublingoftherequiredsiliconarea.
Inaddition,thereareproblemsregardingtheexactvalueofthe
resistors(especiallytheMSBresistor R) iftheDACistoremain
'linear'andexpensivetrimmingmayneedtobedonetoensure
accuracy.
Onepracticalsolutiontoalleviatethisproblemistousecascaded
structures,thatisaparallel/serialhybridarrangement,where
overallconversionspeedissacrificedforaccuracy/linearity:
AnotheralternativeistousematchedFETtransistorstoprovide
theappropriatecurrentpulldown.WhereasingleFETisusedto
establishtheLSBcurrentand2
n1
FETsinparalleltoprovidethe
MSBcurrent.
(b) R2RLadder
OneresistivesolutiontoalleviatetheseproblemsistheR2R
LadderDAC:
i/2
i/4
i/8
i/16
i/32
i/64
i/128
i/256
2R
V
ref
R
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
_
+
R
f
V
o
I
I 1
I2
I3
I4
I 5
I6
I7
I8
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
i
Here,acurrentdividernetworkisusedtogeneratethedesiredop
ampinputcurrentsoftherequiredmagnitudeforeachbit.
However,onlytwovaluesofresistorarerequiredandtherefore
theirmanufactureiseasier,eventhoughtherearealmosttwiceas
manyresistorsrequired.Sincetherighthandendofthe2R
resistorswillbeconnectedtogroundirrespectiveofthebitswitch
position,eitherdirectly(b
i
=0)orviatheopampsvirtualearth
(b
i
=1),then:
R
V
= i
ref
and,asabove

+ + + + + - =
n
n
f
ref o
b b b b b
R
R
V V
2
....
16 8 4 2
. .
4 3 2 1
1:16Resistor
Divider
Network
Bits14
Generates'bit'
switchedcurrentsof
I/2,I/4,I/8andI/16
I
From
Inverting
OpAmp
Bits58
(StructureasBits14)
OneoftheproblemswiththeR2Rladdernetworkisthatthere
areupto2
n1
floatingnodesinthearrangement.Thatisnodesthat
havearelativelylargeresistancetogroundwhicharethen
susceptibletoparasiticcapacitance.Theneedtocharge/discharge
these'capacitors'reducestheoperatingspeedoftheconverter.
InordertodevelopBipolarversionsoftheladderconverterthen
BJT'swithappropriateEmitterarea's(sinceEmitterareais
proportionaltoemittercurrent)mustbeusedtosinkthebit
controlledcurrents.Thatis:
V
ref
_
+
R
f
V
o
I
'Base'
V
ee
BitControlledSwitchingNetwork
BJTSwitcheswithBinaryWeighted
EmitterArea's
'Emitter'R2RLadderNetwork
ToovercometheneedforBJT'swithvarying'size'ofemitterthen
theR2Rnetworkmustbeplacedbetweentheopampandthebit
switchingnetwork.AlltheBJTemitterscanthenbeconnectedto
V
ee
withresistorsofthesamevalue,andtherebypassthesame
current.
4.2.1.2 SWITCHEDVOLTAGENETWORKS
Here,everypossibleoutputvoltagelevelisgeneratedviaa
referencevoltageandaseriesresistancenetwork.Theappropriate
levelbeingswitchedthroughtotheamplifierviaabitcontrolled
switchingnetwork.Theresultingconverterhasaregularstructure
andisthereforeidealforMOStechnology.However,therequired
areaoftheconverterincreasesrapidlyasthenumberofbits
increase.Inaddition,speedisreducedasparasiticcapacitance's
ariseatthefloating nodes.
Bothofwhichcanbeimprovedbyreplacingtheswitching
networkto2
n
bitlevelswitchesfedviaannto2
n
decoderforlarge
bitconverters.
4.2.1.3 SWITCHEDCAPACITORNETWORKS
(CHARGESCALINGNETWORKS)
Commencingwithinitiallyunchargedcapacitor'satwophase
clockisusedtosharethetotalchargewhichisappliedtoa
capacitorarray.Forexampleconsiderthefollowingarrangement:
During f1oftheclockalltheDAC'scapacitorsaredischarged.
Whilstduring f2thecapacitorsassociatedwiththerelevantbits
are:
i) bi=0 leftuncharged(connectedtoground)
ii)bi=1 charged(connectedtoVref)
Theoutputvoltage,V
0
,reflectsthesumofcapacitorsthatare
charged,Cc,withrespecttothetotalcapacitanceinthenetwork,
2C.Thatis,foranydigitalcodethenthefollowingnetworkexists:
Vref Vo
Cc
2CCc
andtherefore
Vo
Vref
Cc
Cc C Cc
Cc
C
= =
+ - ( ) 2 2
Theaccuracyoftheabovedeviceislimitedbytheaccuracyofthe
ratiobetweenthecapacitorsandthearearequiredisafunctionof
thenumberofbits.MOSaccuracyisaround0.1%,sothat10bit
resolutionispossible.Howeverthearearequiredwouldrequirea
ratioof1024:1betweentheMSBandtheLSB,whichisclearly
undesirable.Toovercomethisthenotherscalingapproachesare
requiredsuchasthecascadedapproachesshownpreviously (for
currentscaling).
f2
1 f
b2 .
b2 .
f2
C/2
f2
1 f
b1 .
b1 .
f2
C
Vref
+
_
V
0
f2
1 f
bn .
bn .
f2
C/2
n1
C/2
n1
1 f
4.2.1.4 CHARGEREDISTRIBUTIONDAC
Here,theoperationoftheconverterissequential.Thatis
informationispasseddownanetworkusingswitchestoisolate,
forannbitconverterthennclockpulsesarerequiredbefore
conversioncantakeplaceadisthereforeslowerinoperationthan
thepreviousparallelstructures.
clk
Vref Vo Vc1 Vc2
C1 C2
bit.clk
bit.clk Reset
BeforeconversioncommencesVc2,andthereforeVo(Vo=Vc2),issettozeroviatheReset
signal.ThencapacitorC1ischargedtoVrefifbit=1ordischargedifbit=0.Ontheclockpulse
goinghigh,clk,thenthechargeissharedbetweenC1andC2suchthatVc1=Vc2.Theprocess
repeatingfortherequirednumberofclockpulses.
Note:
TheconvertercommenceswiththeLSBdecision,whichisthen
repeatedlyhalvedateachclock,untilfinallytheMSBdecision
isapplied.
WORKEDEXAMPLE1
Showtheconversionofthesignal 0101(MSBtoLSB)usinga
chargedistributionDACwithC1=C2.
SOLUTION
CLK
0.0
0.25
0.5
0.75
1.0
time
0.0
0.25
0.5
0.75
1.0
time
Vc1/Vref
Vc2/Vref
b4(1) b3(0) b2(1) b1(0)
Althoughtheconverterstructureisverysimplethecontrol
circuitryrequiredtooperatethedeviceisnot.Inadditionits
accuracyissomewhatlimitedbyparasiticcapacitanceandclock
feedthrougherrors.
4.2.1.5 ALGORITHMICDAC'S
Algorithmicdevicesconsistofunitdelaysandweightedsummers
whichrelyupontheLSBdecision toripplethroughtotheoutputa
stageatatime.Foranalysispurposestheunitoftimedelay
(clock) isrepresentedintheztransformationform,where:
OneclockDelay
n clockDelays

-
-
-
z
z
n
1
Inadditionthesedevicesarebipolarinnatureandhencealogic
highandlowarerepresentedbya1and 1respectively.Consider
thestructureofa4bitconverter:
S
Z
1
S
Z
1
S
Z
1
S
Z
1
Vref
+Vref
b4 b3 b2 b1
0
Vo
C B A
1/2 1/2 1/2
LSB MSB
whichcanberepresentedbytheequation
1 1 here w .
2
..... .
2
4
.
2
3
.
2
2
. 1 ) (
1
4
3
3
2
2 1
+ -

+ + + + + =
-
-
- - - -
i
n
n
b Vref z
bn
z
b
z
b
z
b
z b z Vo
Note:
Theoutputoftheconverterwillrangebetween
-
-
2 1
2
1
n
n
Vref . for
allpossibledigitalinputs.
Themainadvantageofthealgorithmicconverteristhatitdoesnot
relyuponcapacitor/resistorratio'sforitsaccuracy.However,the
amplifiersrequiredtoprovidethegainofahalfdoandtherefore
sodoestheoverallnetwork.Theconverterisalsoslowin
operationduetoitssequentialoperation.
Note:
Notethatforannbitconversionnclocksarerequired.
Howeverclockcontrolisnotnecessaryastheconverterwill
ripplethroughtothecorrectconversionvalueprovided
sufficienttimeislefttoallowforthepropagationdelayofthe
LSBthroughthecircuit.
WORKEDEXAMPLE2
Showtheconversionofthedigitalword1101(MSBtoLSB)
usingabipolaralgorithmicDAC.
SOLUTION
Followingthesignalsripplingdownthenetworkattheapplied
clocksthen
A
B
C
Position
in
Network
Vo
1234
ClockNo.
Vref
Vref
Vref
Vref
Vref Vref Vref
Vref/2 Vref/2 Vref/2
Vref/2 3Vref/4 3Vref/4
3Vref/2 5Vref/4 11Vref/8
Checkvia
Vref Vref z Vo
8
11
2
1
2
1
2
1
1 ) (
3 2
=

+
-
+ + =
4.2.2 ANALOGUETODIGITAL
CONVERTERS(ADC'S)
Ananaloguetodigitalconverter,ADC,isusedtoconvertan
analogueinputsignalintoanequivalentnbitdigitalword.In
generaltheallzero'sdigitalwordisusedtorepresentthe
minimumanaloguevalueintherangeandtheallone'scasethe
maximum.However,duetoconstructionalproblemsoffset,gain
andnonlinearityerrorsmayexistinpractice.
AswasthecaseforDACs,bothserialandparallelformsofADC
existalthoughthemajorityemployfeedbackandhavethe
followingbasicstructure:
+
_
Control
Logic
DAC
nbit
word
Digital
Analogue
Input
equivalent
Error
DAC
Vin
Vd
Analogue
Itissimplytheformofthecontrollogicusedduringthe
conversionthatdistinguishesoneconverterfromanother.
4.2.2.1 COUNTERADC
Themostsimpleformofwherethecontrollogicissimplyaclock
operatedcounterwhich,afterastartconversionsignalwhich
resetsthecounter,continuesadigitalcountuntiltheanalogue
equivalentofthedigitalword,Vd,bcomesgreaterthanthe
analogueinput,Vin.Whereuponthecountceasesandthedigital
wordisheldforoutput.
100%
75%
50%
25%
0%
Vd
Time(clockPulses)
Vin
1LSB
1clock
Notethattheconversiontimeisproportional tothesizeofVin
andthattherateofchangeofthecountforannbitADCcovering
therangeV
span
(operatingataclockfrequency fc)is:
Vspan
fc Volts
n
2
. / sec
AsimpleextensiontotheCounterADCistheTrackerADC
whereanUp/DowncounterisuseddependinguponwhetherVin
isbiggerthanVdornotrespectively.Thustheanalogueinputis
continuouslytrackedatamaximumratewhichisdependantupon
theminimumloopoperatingtime(hencethemaximumclock
frequency),theanaloguerangeandthenumberofbitsasabove.
4.2.2.2 SUCCESSIVEAPPROXIMATIONADC(SAC)
InordertospeedconversiontimesupthentheSACdecidesupon
thecorrectvaluefortheMSBtotheLSBinsequence.
100%
75%
50%
25%
0%
Vd
Time(clockPulses)
Vin
Inordertoachievethis,thecontrol logicrequiredbecomesmore
complexthanforpreviousapproaches.Generally,ashiftregister
isusedtoidentifyeachbit(fromMSBtoLSB)inturnandthe
decisionisthenbaseduponthesignoftheerrorbetweenVdand
Vin.Theconversionmaybeterminatedbysendingtheshift
registertotheallzero'scasewhereuponnofurtherchangesin
outputcanoccur.
+
_
Vin
error
DAC
1 1 1
K J clr K J clr K J clr
clk
start
'0'
MSB
LSB
& & &
start
clk
nbitshiftregister
Thus,althoughthemaximumclockfrequencymaybeslowerdue
tothelongerlooptimesrequiredtoperformthecontrollogic
correctly,thenapproximatelynclockpulsesarerequiredforann
bitconverterirrespectiveoftherangeandthevalueoftheinput,
thusSACconversiontimeisn/f
c
.
WORKEDEXAMPLE3
Showthe4bitSACconversion(usingtheabovestructure)ofan
analogueinputof70%ofitsrange.
SOLUTION
OUTPUT
OperationShiftRegister FlipFlop DAC Error
Output Outputs inputs Status
Start 1000 0000 1000 1(Vd=50%)
clk1 0100 1000 1100 0(Vd=75%)
clk2 0010 1000 1010 1(Vd=62.5%)
clk3 0001 1010 1011 1(Vd=68.75%)
clk4+ 0000 1011 1011 etc...
4.2.2.3 SERIALADC'S(SLOPECONVERTERS)
Thebasisofthemajorityofserialconvertersistheintegratorand
themostcommonlyemployeddeviceareSlopeConverters.
(a) SingleSlopeADCs
Singleslopedevicesoperatebycountingthetime(ona
clockedcounter) takenforanintegratedreferencevoltageto
becomeequaltotheanalogueinput.Thatis,thehigherthe
valueoftheinputvoltage,thelongertheintegrationofthe
referencevoltagetakestoreachthisvalue,thehigherthe
digitalcountreached.HencetoramptomaximumVin,thus
theintegrationrateis:

-
= =

c
n
span
in
ref
f
V
t
V
V
RC
1 2
1
max
d
d
However,thismeansthattheiraccuracyiscriticallydependant
uponmatchingtheRCvaluesoftheintegratortothecorrect
ratiototheclockfrequency.Thenatureofthedevices
operationmeansthatconversiontimecantakeanywhereupto
2
n
clocks(notincludingreset).
(b) DualSlopeADCs
Acommonstructurefortheimplementationofadualslope
deviceisshownbelow:
Vref
Interface
=1
'0'
&
&
clk
Counter
up
Q Q
MSB
+
_
Vin
'0'
'1'
R
0v
+
_
C
Register
clk
Themajorbenefitofthedualslopeapproachisthatboththe
charginganddischargingtimesaredependantuponthe
integratorgainRCandthereforeitsaccuracyisnolonger
critical.Considerthefollowingwaveforms:
Thusconsideringtheintegratoroutputsignalduringthe
conversionthen,atitsmaximumvalue(Vin
*
)then

=

-

c
out
ref
c
n
in
f
ADC
V
RC f
V
RC
1 1 2 1
whichsimplifiesto
( ) 1 2 -

=
n
ref
in
out
V
V
ADC
Henceitsoutputisnotdependantupontheintegratorsslopeor
theclockfrequencyandisthereforeveryaccurate.However,it
doestakeapproximately2(2
n
)clockstoconvert.
Integrator
Comparator
Nand2
Counter
Q
0
Vin/RC +Vref/RC
+15
15
1
0
Interface&
ExOr
Nand1
1
0
1
0
clk clk
counter
disabled
+veedgefor
storagein
register
111..11
000..00
1
0
clockedon
counterreset
Conversiontime
count
stored
Vin
*
4.2.2.4 ALGORITHMICADC
ThisparticularstructureshowsaBipolardevicewhichcan
convertintherangeVrefto+Vref.TheactualsignofVrefwhich
isappliedtothesummerbeingdependantuponthesignofthe
previouscomparatorsoutput:
Previousbitdecisionhigh,sum Vref
Previousbitdecisionlow,sum+Vref
Itsaccuracyisdependantupontheaccuracyofthemultipliers(x2)
andthecharacteristicsofthesummers/comparators.
WORKEDEXAMPLE4
Considerthea4bitconverterwithaVrefof10Vconvertingan
analogueinputof+4V.
SOLUTION
MSB: 4V>0VthereforeMSB=+1Voltagefedtonextstageis2* 4V Vref= 2V
Bit2:2V<0V " Bit2= 1 Voltagefedtonextstageis2*2V+ Vref= 6V
Bit3: 6V>0V " Bit3=+1 Voltagefedtonextstageis2* 6V Vref= 2V
LSB: 2V>0V" Bit4=+1 Endof Conversion,Result1011.
Tochecktheresult,usetheformulae:
( ) ( ) Volts b b b b Vref Vd 375 . 4 = 4375 . 0 10 =
16
1
8
1
4
1
2
1
10 2 . 2 . 2 . 2 . =
4
4
3
3
2
2
1
1

+ + - = + + +
- - - -
Theaboveformofconverterisaserialpipelinedevicewhichhas
thedisadvantagethatitwilltaken clockstoperformasingle
conversion(althoughaconversionisproducedateachclock).
MSB
Vin
+
_
2
Z
1
+
_
2
Z
1
+
_
LSB
+Vref
Vref
+1 1 +1 1
S S
Theconvertercanbeoperatediteratively,tosavesiliconarea,
usingtheform:
+
_
Digital
Output
Vref
Vb
x2
Sample
and
hold
Vref
Gnd(0V)
1 +
Vin
Va
Note:
TheaboveconverterisunipolarinoperationofspanVref.To
directlyconstructthepreviousbipolardevicethenyoumust
comparewithrespectto0Vandswitch+/Vref.
WORKEDEXAMPLE5
ShowhowtheiterativeformofaunipolaralgorithmicADC
providesan8bitconversionof7V(Vref=10V).
SOLUTION
For8bitconversionthen8clockpulsesarerequired,wherethe
initialswitchpositiononlyisatVin,and
ClockNo. 1 2 3 4 5 6 7 8
Va/Vref 0.7 0.4 0.8 0.6 0.2 0.4 0.8 0.6
Vb/Vref 1.4 0.8 1.6 1.2 0.4 0.8 1.6 1.2
Output 1 0 1 1 0 0 1 1
Check:
Vd Volts = = 0.69922 10
1
2
0
4
1
8
1
16
0
32
0
64
1
128
1
256
+ + + + + + +

4.2.2.5 PARALLELADC
Vin Vref
R
R
R
R
R
R
R
R
+
_
+
_
+
_
+
_
+
_
+
_
+
_
Digital
Encoding
Network
Digital
Output
7/8Vref
6/8Vref
5/8Vref
4/8Vref
3/8Vref
2/8Vref
1/8Vref
Shift
Register
ParalleloperationensuresthatthisparticularADCisthequickest
intermsofconversion.Theconversiontimebeinglimitedonlyto
thatofthetransmissiontimesoftheslowestcomparator,
Encodingnetworkandshiftregister.However,accuracyproblems
doexistduetothelargenumberofidenticalresistors(ofvalueR)
andcomparator'srequiredinadditiontothelargesiliconarea
whichisrequired.Sinceadoublinginareaisrequiredforeach
singlebitincreaseintheconverteralternativeparallel/series
combinationsareusedtotradeoffthesiliconareaagainstspeedof
conversation,e.g
Vin +
_ 2
n
Vin*
Parallel
ADC
Converter
n/2bit
DAC
Parallel
ADC
Converter
n/2bit
Shift
Register
nbitDigital
Output
4.2.3 SAMPLEHOLDNETWORKS
Thepurposeofthesampleholdistomaintainthesampled(pulse)
signalforafinitetime(Tsamplingtime)toallowanyfurther
operations,suchasADconversion,totakeplacecorrectly.Inits
simplestformitconsistsofaswitchedcapacitor:
Vin Vout
C
Vin
C
+
_
+
_
Control
Gate
Vout
Themajorproblemwithcapacitorstoragedevicesbeingthe
conflictofrequirementsintermsofitscharging/discharging
times.ThatisasmallvalueofCisrequiredforquickacquisition
(chargingfromthelastinputvaluetothepresent)ofdata,buta
largevalueofCisrequiredforlongtermstorageofthisvalue.In
thearrangementabovethecapacitorwillcharge,whentheFETis
on,ataratedeterminedbytheoutputresistanceoftheamplifier,
R
o
,andthe'on'resistanceoftheFET,R
DS
.Ifthesearesmallthen
therate ofchargeofthecapacitorwillbelimitedbythemaximum
current,I,whichtheamplifiercandeliver:
dVc
dt
I
C
=
Toimprovetheacquisitiontimethensomeformofcurrent
amplifierisusedtoincreaseI.Thefollowingdeviceutilisesan
externalcomplementaryemitterfollower.
Vin
+
_
Control
Gate
C
+
_
Vout
V
+V
Itshouldbenotedthattheinclusionofthisextra'integrator'inthe
controlloopcancausesomestabilityproblems.Capacitorswith
polycarbonate,polyethyleneorpolystyrenedielectricsare
recommendedastheirdecayrateisslowerandtheyhaveless
absorption(causingthecapacitortorememberitslastvoltage
levelafterasuddenchange).
4.3 SWITCHEDCAPACITORFILTERS
Signalprocessingalsorequirestheuseofactivecircuitsinorder
toamplify,integrateandfiltersignals.Previousmodules
illustratedtherequirementtouseoperationalamplifierswith
suitableresistor/capacitorarrangementsconnectedaboutthemto
achievethis.However,previouslessonshavealsoshownthat
accuracyandphysicalsizelimitationsexistwheneverthese
passivecomponentsareconstructedinsilicon.Onecommonly
employedsolutiontotheseproblemsistoreplacetheresistor's
withaswitchedcapacitor(SC)structure.Thesubsequent
arrangementofFETswitchesandcapacitor(s)maybeusedto
restrictcurrentflowwiththeadditionalbenefitofdecreased
powerconsumption.
Considerthetwoarrangementsbelow:
Inordertodeterminetheeffectiveresistance,R
eff
,oftheSC
network,notethatfornetworka):
R
V V
= I
out in
-
1
Innetworkb)chargeisswitchedacrossthenetworkduringeach
clockphaseprovidingthattheclockfrequency,fc,ismuch
sufficientlylargethatthechangesinvoltageacrossthenetwork
aresmall.Thisisalimitingfactoralthoughahighclockfrequency
isrequiredifoperationistoappearcontinuousanyway.
Theanalysisofsuchcircuitsrequiresthecalculationofthe
averagecurrentI
1
thatflowsintotheSCnetworkforeachclock
phase.Thus
( )
( ) ( )
T
T T
T
t dq
dt
dt
t dq
T
dt t i
T
I
0
1
0
1
0
1 1
1 1

= = =

I
1
R
Vin
C Vin
T1
T2
Vout Vout
f1 f2
a)StandardResistor b)SwitchedCapacitor'Resistor'
I
1
Therefore,fortheabovecircuit,then(assumingthatthevoltages
areapproximatelyconstantovertheclockperiod, T:
f
1
(0toT/2): ( ) [ ] ( ) Vout Vin C = t dq
T/2
0
-
1
f
2
(T/2toT): ( ) [ ] 0
1
= t dq
T
T/2
Thus
( )
( ) Vout Vin C f
T
Vout Vin C
= I
C 1
- =
-
.
andtherefore
fc . C
=
C
T
R
eff
1
=
LetusconsidertheuseoftheaboveSCnetworktoconstructa
passiveRCfilter:
Frompreviouslessons,andtheaboveanalysis,then:
RCFilter TimeConstant
(t )
Accuracy CMOS
Implementation
Passive
R.C
C
C
R
R d d
+
% 20 5
SC
R C
C f
C
.
C
C
R
R
f
f
C
C
C
C d d d
- -
% 1 . 0 @
AndhencetherelativeaccuracyofthecapacitorsmakestheSC
variantmoreaccurate,particularlyastheclockfrequency
variation, df
c
,isgenerallyverysmall.
R
Vin
Vin Vout Vout
a)PassiveRCFilter b)SwitchedCapacitorRCFilter
C
R
C
T1
f1
T2
f2
C
WORKEDEXAMPLE6
UsingtheaboveRCnetworkwhatwouldbethecapacitorratio
requiredtoconstructapassiveRCfilterofBandwidth1KHzand
clockfrequency200KHz
SOLUTION
Notingthatafirstorderfilters3dBbandwidthis1/t then
005 . 0
200
1
10 200
10 1 /
3
3
3
= =

= =
C
dB R
f
W B
C
C
4.3.1 ALTERNATIVESCNETWORKS
TheSCnetworkoutlinedaboveisaparallelrealisation.Other
formsofnetworkcommonlyusedare
4.3.1.1 SERIESSCNETWORK
f2 f1
C
Vi
Vo
4.3.1.2 SERIESPARALLELSCNETWORK
C1
C2
Vi
Vo
f1 f2
Req=
1
C.fc
Req=
1
(C1+C2).fc
4.3.1.3 BILINEARSCNETWORK
Vi Vo
f1 f2
C
f1 f2
4.3.1.4 STRAYINSENSITIVESCNETWORK
Vi
f2 f1
Vo
C1
f2 f1
C
A
C
B
Oneofthemostcommonlyusednetworkspractically.Here
capacitorC1ischarged(fromVi)during f1oftheclock.andthe
chargeisthenpassedontotheoperationalamplifiersinverting
inputduring f2 oftheclockforintegration.Whenthecapacitoris
notbeingcharged/dischargeditisdisconnected.
Howeverduring f1oftheclock,C
A
chargesitsstraycapacitance
toViwhileC
B
isdischarged.Theother f2 operatedFETbeing
effectivelygroundedviathe f1 operatedFETandthevirtualearth
oftheopampandthereforeremainsuncharged.During f2 the
chargedC
A
isdischargedandtheunchargedC
B
isparalledwith
thevirtualearthoftheopampandthereforeremainsuncharged.
ThereforethestraycapacitancesC
A
andC
B
donotcontribute
chargetoC1orC2andhencedonotaffecttheaccuracyofthe
circuitsoperation.
Req=
1
4C.fc
Req=
1
C.fc
4.3.2 SWITCHCAPACITORACTIVEFILTER
CIRCUITS
SCnetworks,combinedwithanoperationalamplifier,canbeused
toimplementactivefiltercircuits.Forexampleconsiderthe
integratorshownbelow:
Vi
C2
Vo
_
+
C1
f2 f1
Analysisoftheaboveintegrator, replacingtheSCnetworkby
Reff,showsthat
Vo s
Vi s sR C s
fc C
C
eff
( )
( )
.
= = - -
1
2
1 1
2
4.3.2.1 RESISTIVEFEEDBACKCIRCUITS
Theaboveprocedurecanbeusedtoestablishvariousfilter
circuitssimplybyapplyingtherequiredfeedbackaroundthe
operationalamplifier.Forexampleconsidertheconstructionofa
noninvertingFirstOrderLowPassFilter(LPF):
Vo
f2 f1
Vi
_
+
f2 f1
f2 f1
C2
Cr C
C1
However,thearrangementshownaboveisimpracticalasthe
feedbackpathisalwaysdisconnected,since f1 and f2 arenever
onsimultaneously.Thereforeapracticalrealisationoftheabove
is:
Vo
f2 f1
Vi
_
+
f2 f1
C2
Cr C
f1
C1
WhichisaFirstorderNoninvertingamplifierofsteadystate
gain,Avo,where
Avo
ff ff
ff
C C
C
= =
Re Re
Re
1 2
1
1 2
2
+ +
Thesteadystategainisindependentoftheclockfrequency
becauseboththeSCnetworksinthefeedbackpathoperateatthe
samefrequency.
Andwhosetimeconstant, t,is
t = = = C q
C
Cr fc
T C
Cr
r
. Re
.
.
UsingtheaboveSCnetworks,anytypeoffiltermaybe
constructedusingthedesign techniquesproposedbyButterworth,
Chebyshev,etc.
4.3.2.2 FREQUENCYRESPONSE
Theabilityoftheswitchedcapacitornetworkstoapproximate
theircontinuoustimecounterpartsisbestshownbyanalyzing
theirrespectivefrequencyresponses.Letusonceagainconsider
thepassivefirstorderlowpassfilter(LPF)anditsparallel
switchedcapacitorequivalent:
UsingLaplacetransforms,thetransferfunctionofthecontinuous
circuitcanbeshowntobe
( )
1 /
1
1
1
1
1
0
+
=
+
=
+
=
w t s s sRC
s H
which,byreplacingsby jwprovidesthefrequencyresponse
whosemagnitudeandphasearedescribedvia
( )
( ) 1 /
1
2
0
+
=
w w
w j H and
( )

- =
-
0
1
tan
w
w
w j H
However,analysisoftheswitchedcapacitorequivalentrequires
theuseofdiscretetimetheoryusingdifferenceequationsandz
transforms.Considertheswitchedcapacitorcircuitattheendof
the(n1)thclockperiod,then
Priorto f
1
:
During f
1
:
R
Vin
Vin Vout Vout
C
R
C
f1
f2
C
V
i
(n1)
C
R
V
o
(n1) C V
o
(n1)
V
i
(n1)
C
R
V
o
(n1) C V
i
(n1)
Startof f
2
:
Thereforethenextoutputvoltage,V
o
(n),oftheabovecircuitcan
befoundafterthechargeintheabovecircuithasbeenshared,that
is
( ) ( ) ) 1 ( ) ( ) ( ) 1 ( - - = - - = n V n V C n V n V C I
o o o i R
) 1 ( ) 1 ( ) ( -

+
+ -

+
= n V
C C
C
n V
C C
C
n V
o
R
i
R
R
o
TofindtheztransferfunctionwesimplyreplaceV(nm)by
V(z).z
m
andequateterms,hence
) ( 1 ) (
1 1
z V z
C C
C
z
C C
C
z V
i
R
R
R
o
- -

+
=

+
-
therefore(a =C/C
R
)
( )
( ) ( )

+ -

+
=

+ -

+
=

+
-

+
= =
+ -
-
-
-
a a a a a a 1 /
1
1
1
1 / 1 1
1
1
) (
) (
1 1
1
1
1
z z
z
z
C C
C
z
C C
C
z V
z V
z H
R
R
R
i
o
whosefrequencyresponsecanbefoundbyreplacingz
+1
by e
jwt
wherefromeulerstheory
e
jwt
@cos(wt)+jsin(wt)hence
( )
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t j t t j t
e H
t j
w a a w a a a w w a
w
sin 1 cos 1
1
1 / sin cos
1
1
1
+ + - +
=

+ - +

+
=
whosemagnitudeandphasearedescribedvia
( )
( ) ( ) ( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) t
t t t
e H
t j
w a a
w a a w a a w a
w
cos 1 1 2 1
1
sin 1 cos 1 2 cos 1
1
2 2 2 2 2
- + +
=
+ + - + - +
=
and
( )
( ) ( )
( ) ( )
( )
( ) ( )

+ -
- =

- +
+
- =
- -
a a w
w
a w a
w a
w
1 / cos
sin
tan
cos 1
sin 1
tan
1 1
t
t
t
t
e H
t j
V
i
(n1)
C
R
V
o
(n1) C V
i
(n1)
V
o
(n)
C
R
C
V
i
(n1)
+
_ V
o
(n1)
+
_
Thefollowingdiagramshowsthecomparisonbetweenthedesired
frequencyresponseofthenormalized(w
o
=1)continuoustime
LPFanditsswitchcapacitoralternativeforvarious w
c
/w
o
ratios,
notingthedesignequations:
o
c
w
w
b = therefore
o c
T
bw
p
w
p 2 2
= =
and
R
eff
C
T
R = therefore
T T
CR
C
C
o
eff
R
w
a
1
= = =
hence
demonstratingclearlytheeffectofclockfrequency, w
c
,onthe
overallresponseofthefilter.Thefastertheclockthesmallerthe
chargetransferred,theclosertheswitchedcapacitorbecomesto
itscontinuouscounterpart.
10
1
10
0
10
1
10
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
w/w
c
Magnitude
Normalised(w
1
=1)
1
st
orderLPF
w
c
/w
o
=10
w
c
/w
o
=100
WORKEDEXAMPLE7
Showthatthediscretetimetransferfunctionisthesamewhena
firstorderLPFisconstructedusingseriesandparallelSC
networks.
SOLUTION
Considertheseries1
st
orderLPFNetwork:
f2 f1
C
R
Vi Vo C
Then,fromtheendofthe(n1)thclockperiod:
During f
1
:
Startof f
2
:
Thereforethenextoutputvoltage,V
o
(n),oftheabovecircuitcan
befoundafterthechargeintheabovecircuithasbeenshared,that
is
WhichisthesameasintheparallelSC
caseabove,hence
) 1 ( ) 1 ( ) ( -

+
+ -

+
= n V
C C
C
n V
C C
C
n V
o
R
i
R
R
o
Becausethedifferenceequationsandeffectiveresistanceforboth
SCnetworksarethesame,T/C
R
,thensomusttheirtransfer
functionsandfrequencyresponsecharacteristics.
V
i
(n1)
V
i
(n1)
C
R
V
o
(n1) C
discharged
C
R
V
o
(n1) C
0
V
o
(n)
C
R
C
V
i
(n1)
V
o
(n1)
+
_
SUMMARY
ThislessonhasintroducedtheuseofVLSIdesignforanalogue
circuitapplications.Themajorityofanalogueapplicationsfall
intothegeneralareaofsignalprocessingandthereforethe
materialcoveredhasdemonstratedtheuseofdigitaltechnologyto
constructcircuitscapableofconditioninganaloguesignalsand/or
convertingbetweentheanalogue/digitaldomains.
Intermsofcircuitconstruction,thebasicbuildingblockof
analoguecircuitsistheoperationalamplifierwhichitselfcanbe
manufacturedfrombipolarorCMOStechnology.Inthislesson,
onlyabasicintroductiontothedesignofhighgainamplifier
circuitsandthecompensationsubcircuitsrequiredtoachieve
idealcharacteristics.Interestedpartiesareencouragedtoread
Allen&Holberg(seethelessonsreferences)whichcoverthe
topicinmuchgreaterdetail.
Finally,theuseofswitchedcapacitornetworkstominimize
siliconareaandimproveaccuracyhasbeeninvestigated.
Basically,switchedstoragestructureshavebeenusedtocontrol
currentflow,viachargetransfer,inordertoachievethedesired
behaviour,providedthattheswitchingfrequencyisconsiderably
higher(>10)thanthebandwidthrequiredofthecircuitin
question.
SELFASSESSMENTQUESTIONS
QUESTION1
ShowthattheoutputvoltageofaswitchedcapacitorNetworkDACofsection 4.2.1.3isgivenby
Vref
C
Cc
Vo

2
=
andsketchthecharacteristicsofa3bitconverter.
QUESTION2
WhatmodificationsarerequiredtoconvertthebipolaralgorithmicDACofsection 4.2.1.5in
ordertoachieveunipolaroperationof 0V
ref
volts?
QUESTION3
ThefollowingcircuitshowsasingleslopeADCconverter(ignoringresetandbasedaroundthe
dualslopedeviceofsection 4.2.2.3).Sketchitsconversionoperationandevaluateanexpression
foritsoutput.
QUESTION4
Howwouldyouconstructaunipolarversion(spanVref)ofthealgorithmicADCofsection
4.2.2.4?Demonstrateyoursolutionbyshowing8bitconversionof6Vassumingthereference
voltageis10V.
QUESTION5
EvaluatetheeffectiveresistanceoftheBilinearSCnetworkof section 4.3.1.3.
&
clk
Counter
up
ADC
out
+
_
V
in
R
0v
+
_
C
V
ref
ANSWERSTOSELFASSESSMENTQUESTIONS
ANSWER1
Fromsection 4.2.1.3thenetworkeffectivelylookslikeacapacitivepotentialdividerwithC
1
=
C
C
andC
2
=2CC
C
.Thusastheimpedanceofacapacitoris1/jwCthen

+

+

+

+

+
2 1
1
2 1
2 1
2
2 1
2
2 1
2
2 1
2 0
1
1 1
1
1 1
1
C C
C
=
C C
C C
C
=
C C
C
=
j j
j
=
Z Z
Z
=
V
V
ref
Therefore

- + C
C
=
C C C
C
=
V
V
C
C C
C
ref
2 2
0
Foranbitconverterthen:
00...00: C
C
=0, and V
0
=0
0001: C
C
=C/2
n1
, and V
0
=V
ref
/2
n1
.
.
1111: C
C
=2CC/2
n1
,and V
0
=(1 1/2
n
)V
ref
Hencefora3bitconverterthefollowingcharacteristicswillarise:
000001010011100101110111
8BitDigitalCode
V
ref
7V
ref
/8
3V
ref
/4
5V
ref
/8
V
ref
/2
3V
ref
/8
V
ref
/4
V
ref
/8
0
V
0
Ideal
ANSWER2
TheonlywaytochangetheoutputrangeofanalgorithmicDACistoswitchfromdifferent
referencelevels.Foraunipolaroutputof 0toV
ref
voltsthen,astheoutputisapproximatelytwice
thecommoninput(atthelimitsofconverteroperation):
i) For0V outwhenallbitsarelowtheymustconnectto0V
ii) ForV
ref
outwhenallbitsarehightheymustconnecttoV
ref
/2volts,hence:
Whichcanberepresentedbytheequation
1 0 here w
2
.
2
..... .
2
4
.
2
3
.
2
2
. 1 ) (
1
4
3
3
2
2
1
1
+

+ + + + + =
-
-
- - - -
i
ref
n
n
b
V
z
bn
z
b
z
b
z
b
z b z Vo
Notethattheoutputoftheconverterwillactuallyrangebetween
0and ref
n
V

-
2
1
1
ThatisitwillfalloneLSBshortof V
ref
.ThiswouldbeacceptableforlargebitDACsbutif
precisionisrequiredthen V
ref
/2mustbetrimmedto
2 1 2
2
ref
n
n
V

-
1/2
S
Z
1
S
Z
1
S
Z
1
S
Z
1
0
Vref/2
b4 b3 b2 b1
0
V
0
1/2
LSB MSB
1/2
ANSWER3
Fromthecircuitprovidedthenthefollowingsignalswillariseduringconversion:
Inspectionoftheintegratoroutputshows

=

=
c
out
in
ref
f
ADC
V
V
RC t
V 1
d
d
whichsimplifiesto
( )
c
ref
in
out
f RC
V
V
ADC

=
Henceitsoutputisdependantupontheintegratorsslopeandtheclockfrequency.
Integrator
Comparator
And
Counter
0
+Vref/RC
1
0
1
0
clk
counter
disabled
111..11
000..00
Conversiontime
count
stored
Vin
ANSWER4
Notethefirstcomparison,andallthereafter,requiresaMSBvaluetobesetiftheinputisgreater
thanhalf theunipolarrange,thatisVref/2.Thiscompareswiththeunipolarstructureofthe
iterativeform,showninsection 4.2.2.4, asherethecomparatorisbeforethe2multiplier.
Hence
MSB:6V>5VthereforeMSB=1 Voltagefedtonextstageis2*6V 10 =2V
Bit2:2V<5V" Bit2=0 Voltagefedtonextstageis2*2V+ 0 =4V
Bit4:8V>5V" Bit4=1 Voltagefedtonextstageis2*8V 10=6V
Bit5:6V>5V" Bit5=1 Voltagefedtonextstageis2*6V 10=2V
LSB:8V>5V " LSB=1 EndofConversion,Result10011001.
Tochecktheresult,usetheformulae:
( )
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2 . 2 . 2 . 2 . 2 . 2 . 2 . 2 . =
- - - - - - - -
+ + + + + + + b b b b b b b b Vref Vd
therefore
( ) Volts Vd 977 . 5 = 5977 . 0 10 =
256
1
128
0
64
0
32
1
16
1
8
0
4
0
2
1
10 =

+ + + + + + +
MSB
Vin
+
_
2
Z
1
+
_
2
Z
1
+
_
LSB
0
Vref
+1 1 +1 1
S S
Vref/2
Vref/2 Vref/2
ANSWER5
Therefore,fortheabovecircuit,then(assumingthatthevoltagesareapproximatelyconstantover
theclockperiod,T:
Endof f
1
(T/2): ( ) [ ] ( )
out in
T/2
0
V V C = t dq -
1
Endof f
2
(T): ( ) [ ] ( )
in out
T
T/2
V V C = t dq -
1
Thusthechargechangefromphasetophaseis
( ) [ ] ( ) ( ) ( ) ( )
out in in out out in
V V C V V C V V C = t dq
2
1
- = - - - 2
1
f
f
Sinceaperiodcoverstwosuchchangesthen
( )
( )
out in C
out in
1
V V C f
T
V V C
= I - =
-
. 4
4
andtherefore
fc . C
=
C
T
R
eff
4
1
4
=

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ELX304-Topic5-Lesson 4 - pr2 PDF

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ElectronicSystemsDesign(ELX304) Lesson4CMOSAnaloguedesign

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