On-chip current sensing techniques for

hysteresis current controlled DCDC

converters
J.-J. Chen, Y.-T. Lin, H.-Y. Lin, J.-H. Su, W.-Y. Chung,
Y.-S. Hwang and C.-L. Tseng
An on-chip current sensing technique for a hysteresis current
controlled step-down DCDC converter is presented. This current
sensing technique has been designed with standard 0.35 mm CMOS
2P4M processes. Experimental results show that the current sensing
circuit measures full-time the inductor current whether the high-side or
low-side switch is turned on.
Introduction: Sensing techniques for the output current are necessary
in both voltage-mode and current-mode switch-mode power conver-
ters (SMPC), because they can detect open-load, short-circuit and
over-current situations for both energy saving and protection
purposes. Especially, for current-mode control schemes, their control-
lers require the sensing of the inductor current throughout the whole
switching period. There are different current sensing techniques,
which have been published or implemented [19]. To sense the
output current of current-mode converters, a sensing resistor is
usually used in series with the inductor or power transistor. The
main concern of this approach is its high power dissipation, as all of
the inductor current or drain current of the power transistor must pass
through the sensing resistor. Another common method is using an
integrator to determine the inductor current. This control scheme is
called sensorless current mode control [1], which would increase the
complexity of designing different kinds of converters as different
topologies have different integrators. In some sensing techniques, the
current transformer is used for sensing the current signal, but this is
not suitable for portable electronic device applications because of the
large transformer size and weight. The sensing technique in [2] uses
the conduction resistance of the power MOSFET instead of the
sensing resistor. The main concern of this sensing scheme is the
value of R
on
required for good control of the converters. One of the
on-chip current-sensing techniques designed with the BiCMOS
process is proposed in [4] and [5], but it cannot sense full-time the
inductor current. Another improved on-chip current sensing scheme is
proposed in [7] and [8], but this scheme can still not measure the
current of the low-side switch.
In current-mode controllers, hysteresis current controlled techniques
can be used to achieve fast transient response [6]. The on-chip current
sensing schemes described above are not suitable for this controller,
because they cannot fully sense the inductor current. In this Letter, an
on-chip current sensing circuit suitable for hysteresis current controlled
DC-DC converters is proposed.
Circuit descriptions: To sense the current of the inductor full-time, a
current sensing circuit is proposed and shown in Fig. 1, which is
process independent and supply voltage independent as compared
with previous work [9]. The number of components shown in Fig. 1 is
less than that proposed in [9]. The output current I
pp
, which ows
through the power transistor MP1, is mirrored to the sense transistor
MS1. The voltage change of node A will mirror a similar change to
node B owing to the virtual short-circuit provided by the operational
amplier. Therefore, the drain-to-source voltage V
DS
of transistors
MP1 and MS1 are almost the same, as well as their current density. If
the aspect ratio of the power switch is larger than that of the sense
transistor, e.g. N:1, the sensing current I
ps
is proportional to the output
current I
pp
and can be described as
I
ps
I
pp

W=L
MS1
W=L
MP1

1
N
1
Conversely, the output current I
np
, which ows through the power
transistor MP2, is mirrored to the sense transistor MS2. The voltage at
node P is virtually grounded owing to the virtual short-circuit provided
by the operational amplier. The drain-to-source voltage V
DS
of
transistors MP2 and MS2 are then almost the same, as well as their
current density. If the aspect ratio of power switch is larger than that of
the sense transistor, e.g. N1:1, the sensing current I
ns
is proportional
to the output current I
np
and can be obtained as
I
ns
I
np

W=L
MS2
W=L
MP2
W=L
MS2

1
N
2
The current I
ind
of the sensing circuit can then be obtained and
described as the summation of sense currents I
ps
and I
ns
. Since the
inductor current I
L
is the summation of power switch currents I
pp
and
I
np
, the output current of sensing circuit I
ind
can be written as:
I
ind
I
L

I
ps
I
ns
I
pp
I
np

1
N
3
Using the current sensing circuit, the step-down hysteresis-controlled
DCDC converter, as shown in Fig. 2a, is designed to work in parallel.
The parallel hysteresis current controlled step-down DCDC converter
shown in Fig. 2b is operated at continuous mode with current sharing
techniques.
V
DH
Ipp
MP1
VA
N:1
V
DD
MS1
Ips
VB
M5 M7
M4
A1
A2
V
p
current sensing circuit
MS2
( 1):1 N-
MP2
V
DL
I
np
C
out
L
out
I
L
V
out
ZL
I
ns
V
DD
M2
M11 M9
- +
I
ind
+ -
Fig. 1 Proposed current sensing circuit
VDD
IAV
CM1
CM2
CM3
VP
VFB
GND
VDD
IAV
CM1
CM2
CM3
VP
VFB
GND
VDD
IAV
CM1
CM2
CM3
VP
VFB
GND
V
DD I
L1 L1
I
L2
L2
I
L3 L3
Rf11
Rf12
C
out1
I
R1
I
R2
C
out2
I
R3
C
out3
ZL
V
out
I
out
b
current
sharing
circuit
frequency
compensated
circuit
hysteresis
current
comparator
current
sensing
circuit
driving
circuit
V
DH
MP1
V
DL
MP2
Rf1
Rf2
VP
L
out
V
DD
power stage
Cp1
Cp2
IAV
CM1
CM2
CM3
hysteresis-current-controlled circuit
VFB
V
ref
C
out ZL
V
out
a
I
ind

Fig. 2 Proposed step-down DCDC converter and parallel DCDC

converter
a Proposed step-down DCDC converter
b Parallel DCDC converter
power
NMOS
driving
circuit
power
PMOS
current
sensing
hysteresis-current-
controlled circuit
bias
circuit
Fig. 3 Photograph of proposed chip, as shown in Fig. 2a
Experimental results: The hysteresis current controlled step-down
DCDC converter using the proposed current sensing circuit has
been implemented with 0.35 mm 2P4M CMOS processes. The
ELECTRONICS LETTERS 20th January 2005 Vol. 41 No. 2
photograph of the proposed converter, as shown in Fig. 2a, is shown
in Fig. 3. The experimental results of this converter are shown in
Figs. 4a and b with 2.5 V supply voltage. As shown in Fig. 4a, from
top to bottom, the waveforms are output voltage V
out
, control voltage
V
DH
and inductor current with 1.5 Voutput voltage, respectively. The
parallel DCDC converter, as shown in Fig. 2a, is also measured. Fig.
4b shows the experimental results of the parallel converter, as shown
in Fig. 2b, with 1.5 V output voltage. From top to bottom, the
waveforms are inductor currents I
L1
and I
L2
, respectively. The induc-
tance of each converter is 59 and 89 mH, respectively. Then the
proposed inductor current sensing circuits work and agree well with
theoretical analysis in the parallel DCDC converter.
4
a
3
T
1
4
b
m1
Fig. 4 Experimental results of proposed converter (from top to bottom,
the waveforms are output voltage V
out
(1 V=div.), control voltage V
DH
(2 V=div.), inductor current (100 mA=div.), respectively); and experimen-
tal results of proposed parallel hysteresis current controlled DCDC
converter (from top to bottom, the waveforms are inductor currents I
L1
and I
L2
(200 mA=div.), respectively)
Inductance of each converter 59 and 89 mH, respectively
a Of proposed converter
b Of proposed parallel hysteresis current controlled DCDC converter
Conclusions: A new on-chip current sensing technique for a hyster-
esis current controlled step-down DCDC converter is presented. The
main advantages of this scheme are threefold: (i) the current sensing
circuit can full-time measure the inductor current through sensing the
current of power switches whether the high-side or low-side switch
is turned on; (ii) the proposed converter can work in parallel hyster-
esis current controlled step-down DCDC converters such that the
load current can be easily managed through control theories; (iii)
the current sensing circuit works well even if the inductors are
mismatched. This current sensing circuit will be useful in portable
parallel DCDC converters, multimedia power supporting and power
electronic and telecommunication applications.
Acknowledgments: The authors wish to thank the National Science
Council for project support and the Chip Implementation Center for
chip fabrication. This work was sponsored by NSC-92-2213-E262-012.
# IEE 2005 31 August 2004
Electronics Letters online no: 20056807
doi: 10.1049/el:20056807
J.-J. Chen and Y.-S. Hwang (Department of Electronic Engineering,
National Taipei University of Technology, Taipei 106, Taiwan)
Y.-T. Lin and W.-Y. Chung (Department of Electronic Engineering,
Chung Yuan Christian University, Chung-Li 320, Taiwan)
H.-Y. Lin and J.-H. Su (Department of Electronic Engineering,
Lunghwa University of Science and Technology, Taoyuan 333,
Taiwan)
C.-L. Tseng (Department of Electrical Engineering, National Taipei
University of Technology, Taipei 106, Taiwan)
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