Vignans Lara Institute of Technology and Science, Vadlamudi

(Affiliated to JAWAHARLAL !HR" T!#H$L$%I#AL "IV!RSIT&' (A(IA)A * (A(IA)A+

)e,artment of !lectrical - !lectronics !ngineering
L!#T"R! .LA
(+ Linear - )igital I# A,,lications
Academic Year: /012*/013 Regulation : R10
Year / Course : III / 45Tech Semester : I
Branch : !lectrical - !lectronics !ngineering Hours per week : 03
Name ' Mr. J. Veerayya Tutorials : 0
Credits : 2
$67ecti8e' Linear !igital "C Applications course introduces di##erent Linear and !igital "ntegrated
Circuits their characteristics$ speci#ications$ and applications% At the end o# this course students can a&le to
use these "C's #or their inno(ati(e ideas%
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Integrated #ircuits
)3 "ntegrated circuits/T7pes$ Classi#ication$ 8ackage
T7pes$ temperature ranges$ 8ower supplies$
*3 !i##erential Ampli#ier/ !C and AC anal7sis o# !ual
input &alanced output Con#iguration
+3 8roperties o# other di##erential ampli#ier con#iguration
,3 3!C Coupling and Cascade !i##erential Ampli#ier
Stages
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$,erational Am,lifier
)3 Characteristics o# 98/Amps
*3 9p/amp Block !iagram$ ideal and practical 9p/amp
speci#ications
+3 !C and AC characteristics
,3 5,) op/amp its #eatures
-3 :;T input$ 9p/Amp parameters measurement
43 "nput 9ut put 9## set (oltages currents
53 slew rates$ C<RR$ 8SRR
63 dri#t$ :re=uenc7 Compensation techni=ue
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A,,lications of o,*Am,s
)3 "n(erting and Non/in(erting ampli#ier
*3 "ntegrator and di##erentiator
+3 !i##erence ampli#ier
,3 "nstrumentation ampli#ier
-3 AC ampli#ier
43 > to "$ " to > con(erters
53 Bu##ers% Comparators
63 <ulti(i&rators
23 Triangular and S=uare wa(e generators
)13 Log and Anti log ampli#iers
))3 8recision recti#iers
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Timers - .hase Loc9ed Loo,s '
)3 "ntroduction to --- timer$ #unctional diagram
*3 <onosta&le and Asta&le operations and applications
+3 Schmitt Trigger
,3 8LL / introduction$ &lock schematic$ principles and
description o# indi(idual &locks
-3 -4- 8LL
43 Applications o# 8LL ? #re=uenc7 multiplication$
#re=uenc7 translation
53A<$ :< :S@ demodulators
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Acti8e :ilters
)3 "ntroduction$ )st order$ *nd order L8:$ H8: #ilters
*3 Band pass$ Band reAect and all pass #ilters
+3 "ntroduction$ &asic !AC techni=ues
,3 weighted resistor !AC$ R/*R ladder !AC
-3 in(erted R/*R !AC
43 !i##erent t7pes o# A!Cs / parallel comparator t7pe
A!C
53 counter t7pe A!C$ successi(e approBimation A!C
and dual slope A!C
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#om6inational Logic )esign
)3 "ntroduction$ !esign and Anal7sis procedures
*3 !ecoders$ encoders
+3 multipleBers and demultipleBers$ Code Con(erters
,3 comparators$ adders su&tractors
-3 $ Ripple Adder$ Binar7 8arallel Adder
43 Binar7 Adder/Su&tractor
53 Com&inational multipliers
63 AL. !esign
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41
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Se;uential Logic )esign
)3 "ntroduction$ Latches$ and #lip/#lops$ :lip/:lop
Con(ersions
*3 Counters$ !esign o# Counters using !igital "Cs$
+3 Counter applications
,3 S7nchronous design methodolog7
-3 Shi#t Registers$ <odes o# 9peration o# Shi#t Registers$
43 Ring Counter$ Cohnson Counter
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.rogramma6le Logic )e8ices (.L)S+
)3 8rogramma&le Read 9nl7 <emor7$ 8rogramma&le
Logic Arra7$ and 8rogramma&le Arra7 Logic !e(ices
*3 R9<: "nternal structure$ Commercial R9< t7pes$
timing and applications
+3Static RA<: "nternal structure$ SRA< timing$ standard
SRA<S
,3 s7nchronous SRA<S
-3!7namic RA<: "nternal structure$ timing$ s7nchronous
!RA<s%
Signature o# the :acult7 Signature o# the H9!