CHAPTERTWO

ASICDesignFlow
Application-specic integrated circuit (ASIC) design is based on a design
owthatuseshardwaredescriptionlanguage(HDL). Mostelectronicdesign
automation(EDA)toolsusedforASICowarecompatiblewithbothVerilog
andveryhighspeedintegratedcircuithardwaredescriptionlanguage(VHDL).
In this ow, the design and implementation of a logic circuit are coded in
eitherVerilog orVHDL. Simulation is performed to check its functionality.
Thisisfollowedbysynthesis. SynthesisisaprocessofconvertingHDLtologic
gates. After synthesis, the next step is APR (auto-place-route). APR is ex-
plainedinmoredetailinSection2.6.
Figure2.1showsadiagramofanASICdesignow, beginningwithspeci-
cationofanASICdesigntoregistertransferlevel(RTL)codingand, nally,
totapeout.
2.1 SPECIFICATION
Figure 2.2 indicates the beginning of the ASIC ow: the specication of a
design. This is Step 1 of an ASIC design ow. The design of an ASIC chip
beginshere.
SpecicationisthemostimportantportionofanASICdesignow. Inthis
step, the features and functionalities of an ASIC chip are dened. Chip
planningisalsoperformedinthisstep.
During this process, architecture and microarchitecture are derived from
the required features and functionalities. This derivation is especially impor-
3
VerilogCodingforLogicSynthesis, editedbyWengFookLee
ISBN0-471-429767 Copyright2003byJohnWileyandSons, Inc.
4 ASICDESIGNFLOW
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
Logic
verication
pass?
Yes
No
No
FIGURE2.1. DiagramshowinganASICdesignow. Sections2.1to2.9explaineach
sectionoftheASICowindetail.
STEP1
Specication RTLCoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
Verication
Pass?
Yes
No
FIGURE2.2. DiagramindicatingStep1ofanASICdesignow: specication.
tant, asthearchitectureofadesignplaysanimportantroleindeterminingthe
performancecapabilitiesandsiliconareautilization.
Figure 2.3 shows the process involved in dening the architecture and
microarchitectureofadesign. Specicationcontainsalistofallfeaturesand
functionalities required in the design. These include power consumption,
voltagereferences, timingrestrictions, andperformancecriteria. Fromthislist,
thechiparchitecturecanbedrafted. Thisdenedarchitecturemusttakeinto
consideration all required timing, voltage, and speed/performance of the
design. Architecturalsimulationsneedtobeperformedonthedraftedarchi-
tecturetoensurethatitmeetstherequiredspecication.
Duringarchitecturesimulations, thearchitecturaldenitionwillhavetobe
changedifthesimulationresultshowsitcannotmeetanyrequirementsinthe
specication. When all the requirements are met, this architecture is said to
meettherequiredspecications. Fromhere, amicroarchitectureisdraftedand
denedtoallowexecutionofthearchitecturefromadesignstandpoint.
The microarchitecture is the key point that enables the design phase.
A microarchitecture interfaces the designs architecture and circuit. It also
allows transformation of an architectural concept into possible design
implementation.
2.2 RTLCODING
Figure2.4showsStep2oftheASICdesignow. Thisisthebeginningofthe
designphase. Themicroarchitectureistransformedintoadesignbyconvert-
ingitintoRTLcode.
AsshowninSection2.1(Step1oftheASICdesignow), architectureand
microarchitecture are derived from specication. In Step 2, the micro-
architecture, which is the implementation of the design, is coded in synthe-
sizableRTL.
RTLCODING 5
Specication
Architecture
denition
Microarchitecture
denition
Architectural
simulation
Simulation
pass
Yes
No
FIGURE2.3. Diagramshowingthedenitionofarchitectureandmicroarchitecture.
ThereareseveralwaystoobtaintheRTLcode. Somedesignersusegraphi-
cal entry tools like Summit DesignsVisual HDL or Mentor Graphics HDL
Designer. Thesegraphicalentrytoolsallowdesignerstousebubblediagrams,
ow charts, or truth table to implement the microarchitecture, which subse-
quently generate the RTL code either inVerilog orVHDL. However, some
designerspreferwritingtheRTLcoderatherthanusingagraphicalentrytool.
Both approaches end in the same result: synthesizable RTL code that
describeslogicfunctionalityofthespecication.
2.2.1 TypesofVerilogCode:RTL,Behavioral,andStructural
Section 2.2 discusses RTL coding. In Verilog language, there are three
typesofVerilogcode. Formostcasesofsynthesis, synthesizableRTLcodeis
used. Table2.1liststhedifferencesandusageofeachofthetypesofVerilog
code.
2.3 TESTBENCHANDSIMULATION
Figure 2.5 shows Step 3 in theASIC design ow, which involves creation of
testbenches. TheseareusedtosimulatetheRTLcode.
Atestbenchisbasicallyawraparoundenvironmentsurroundingadesign,
whichenablesthedesigntobesimulated. Itinjectsaspeciedsetofstimulus
6 ASICDESIGNFLOW
STEP2
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE2.4. DiagramindicatingStep2ofanASICdesignow: RTLcoding.
TESTBENCHANDSIMULATION 7
TABLE2.1. ThethreetypesofVerilogcode
RTL Behavioral Structural
RTLcoding, orregister Behavioralcodingis StructuralVerilogcoding
transferlevel, ismost usedtodescribeablack hasadatatypestructure
commonlyusedtodescribe box designwherebythe thatdenesthe
thefunctionalityofa outputofthedesignis differentcomponentsand
designforsynthesis. It speciedforacertain theirinterconnects
isalsodescriptivein inputpattern. Behavioral presentinadesign. It
nature, similarto codemimicsthe representsanetlistofa
behavioralVerilog. functionalityand design. Structural
However, itonlyusesa behavioroftheblack Verilogisnormallyused
subsetofVerilogsyntax, box design. Itis whenpassingnetlist
asnotallVerilogsyntax normallyusedforsystem- informationofadesign
issynthesizable. RTL leveltesting. betweendesigntools. For
codingcanbeviewedas example, uponcompletion
moredescriptivethan ofsynthesis, thenetlist
structuralVerilogbut ofadesignispassedto
lessdescriptivecompared APR(refertoSection2.6
withbehavioralVerilog. forexplanationofAPR)
usingstructuralVerilog.
moduleRTL(inputA, inputB,
inputC, inputD, outputA);
inputinputA, inputB, inputC,
inputD;
outputoutputA;
regoutputA;
always@(inputAorinputB
orinputCorinputD)
begin
if(inputA&inputB
&~inputD)
outputA=inputC;
elseif(inputA&
inputD&~inputC)
outputA=inputB;
else
outputA=0;
end
endmodule
modulebehavior(inputA,
inputB, inputC, inputD,
outputA);
inputinputA, inputB,
inputC, inputD;
outputoutputA;
regoutputA;
always@(inputAorinputB
orinputCorinputD)
begin
if(inputA&inputB&
~inputD)
outputA=#5
inputC;
elseif(inputA&
inputD&~inputC)
outputA=#3
inputB;
elseif((inputA==
1'bx)|(inputB==
1'bx)|(inputC==
1'bx)|(inputD==
1'bz))
outputA=#71'bx;
elseif((inputA==
1'bz)|(inputB==
1'bZ))
outputA=#71'bZ;
else
outputA=#30;
end
endmodule
modulestructural(inputA,
inputB, inputC, inputD,
outputA);
inputinputA, inputB,
inputC, inputD;
outputoutputA;
wiren30;
AN3U8(.A(inputA),
.B(n30), .C(inputB),
.Z(outputA));
EOU9(.A(inputD),
.B(inputC), .Z(n30));
endmodule
into the inputs of the design, check/view the output of the design to ensure
thedesignsoutputpatterns/waveformsmatchdesignersexpectations.
RTL code and the test bench are simulated using HDL simulators. If the
RTLcodeiswritteninVerilog, aVerilogsimulatorisrequired. IftheRTLcode
is written in VHDL, a VHDL simulator is required. Cadences Verilog XL,
8 ASICDESIGNFLOW
ReferringtotheVerilogcodeshown, whensimulatedorsynthesized, boththeRTL
andstructuralVerilogwillyieldthesamefunctionality. BehavioralVerilog, however,
isnotsynthesizable.
SynthesizedlogicforRTLVerilogandstructuralVerilog
inputA
inputD
inputC
inputB
EO AN3
STEP3
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE 2.5. Diagram indicating Step 3 of an ASIC design ow: test bench and
simulation.
TABLE2.1. (Continued)
RTL Behavioral Structural
Synopsyss VCS, and Mentor Graphics Modelsim are among some of the
Verilog simulators used. Cadences NCSim and Mentor Graphics Modelsim
arecapableofsimulatingbothVerilogandVHDL. SynopsyssSciroccoisan
exampleofaVHDLsimulator. Apartfromthesesimulators, therearemany
other VHDL and Verilog simulators. Whichever simulator is used, the end
resultisthevericationoftheRTLcodeofthedesignbasedonthetestbench
thatiswritten.
If the designer nds the output patterns/waveforms during simulation do
not match what he or she expects, the design needs to be debugged. A non-
matching design output can be caused by a faulty test bench or a bug in the
RTL code. The designer needs to identify and x the error by xing the test
bench(ifthetestbenchisfaulty)ormakingchangestotheRTLcode(ifthe
erroriscausedbyabugintheRTLcode).
Upon completion of the change, the designer will rerun the simulation.
This is iterated in a loop until the designer is satised with the simulation
results. ThismeansthattheRTLcodecorrectlydescribestherequiredlogical
behaviorofthedesign.
2.4 SYNTHESIS
Figure 2.6 shows Step 4 of theASIC design ow, which is synthesis. In this
step, theRTLcodeissynthesized. ThisisaprocesswherebytheRTLcodeis
convertedintologicgates. Thelogicgatessynthesizedwillhavethesamelogic
functionalityasdescribedintheRTLcode.
SYNTHESIS 9
STEP4
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE2.6. DiagramindicatingStep4ofanASICdesignow: synthesis.
InStep4, asynthesistoolisrequiredtoconverttheRTLcodetologicgates.
More common tools used in the ASIC industry include Synopsyss Design
CompilerandCadencesAmbit.
Thesynthesisprocessrequirestwootherinputlestomaketheconversion
fromRTLtologicgates. Therstinputlethatthesynthesistoolmusthave
beforemakingtheconversionisthetechnologylibrary le. Itisalibraryle
that contains standard cells. During the synthesis process, the logic function-
alityoftheRTLcodeisconvertedtologicgatesusingtheavailablestandard
cellsinthetechnologylibrary. Thesecondinputle, constraintsle, helpsto
determine the optimization of the logic being synthesized. This le normally
consistsofinformationliketimingandloadingrequirementsandoptimization
algorithms that the synthesis tool needs to optimize the logic, and even pos-
siblydesignrulerequirementsthatneedtobeconsideredduringsynthesis.
Step4isaveryimportantstepintheASICdesignow. Thisstepensures
that synthesis tweaks are performed to obtain the most optimal results
possible, shouldthedesignnotmeetthespeciedperformanceorarea.
If, uponnaloptimization, therequiredperformanceorareautilizationis
still not within acceptable boundaries, the designer must reconsider the
microarchitecture as well as architectural denitions of the design. The
designer must re-evaluate to ensure the specied architecture and microar-
chitecture can meet the required performance and area. If the requirements
cannotbemetwiththecurrentarchitectureormicroarchitecture, thedesigner
will have to consider changing the denition of the architecture or microar-
chitecture. Thisisundesirable, aschangingthearchitectureormicroarchitec-
turecanpotentiallybringthedesignphasebacktotheearlystagesofStep1
of theASIC design ow (specication). If by changing the architecture and
microarchitecture denition the design is still unable to provide the kind of
performance or area utilization required, the designer must resort to the
possibilityofchangingthespecicationitself.
2.5 PRE-LAYOUTTIMINGANALYSIS
When synthesis is completed in Step 4, the synthesized database along with
thetiminginformationfromStep4isusedtoperformastatictiminganalysis
(Step 5). In Step 5, timing analysis is pre-layout, because the database is
withoutanylayoutinformation(Fig. 2.7).
Atimingmodelisbuiltanditstiminganalysisisperformedonthedesign.
Normally, the timing analysis is performed across all corners with different
voltages and temperatures. This is to catch any possible timing violations in
thedesignwhenusedacrossspeciedtemperatureandvoltagerange.
Any timing violation caught, for example, setup and hold time violations,
will have to be xed by the designer. The most common way of xing these
timingviolationsistocreatesynthesistweakstoxthosepathsthatarefailing
timing.
10 ASICDESIGNFLOW
Acommonxforholdviolationistoadddelaycellsintothepaththatis
failing hold time check. A common x for setup violation is to reduce the
overalldelayofthepaththatfailedthesetuptimingcheck.
These synthesis tweaks are used to resynthesize the design. Another
pre-layouttiminganalysisisperformed.
Step5intheASICowsometimesvariesdependingonthedesignproject.
Some design projects will proceed to Step 6, although having timing failures
in pre-layout timing analysis. The reason for this is because it is pre-layout
timing analysis. The interconnect parasitics that are used for timing analysis
areestimationsandmaynotbeaccurate.
A more common method used in Step 5 is to x timing failures that are
above certain values. The designer can set a value of x nanoseconds allowed
timingviolation. Thepaththatfailsmorethanx nanosecondsisxed. Thepath
thatfailslessthanx nanosecondsisnotxed. Again, thiscanbeattributedto
thefactthattheparasiticsusedinthetiminganalysisarenotaccurate, because
no back annotated information is used during this step (pre-layout timing
analysis).
2.6 APR
Oncepre-layouttiminganalysisofthesynthesizeddatabaseiscompleted, the
synthesized database together with the timing information from synthesis is
APR 11
STEP5
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE 2.7. Diagram indicating Step 5 of an ASIC design ow: pre-layout timing
analysis.
used forAPR (Fig. 2.8). In this step, synthesized logic gates are placed and
routed. The process of this placement and routing has some degree of exi-
bility whereby the designer can place the logic gates of each submodule
accordingtoapredenedoorplan.
Most designs have critical paths that are tight in terms of timing. These
paths can be specied by the designer as high-priority paths. TheAPR tool
will route these high-priority paths rst before routing other paths to allow
forthemostoptimalrouting.
APRisalsothestepinvolvedinclocktreesynthesis. MostAPRtoolscan
handle routing of clock tree with built-in special algorithms. This is an espe-
cially important portion of theAPR ow because it is critical that the clock
tree be routed correctly with an acceptable clock skew. Most APR tools
allowadesignertospecifyarequiredclockskewandbuffersupeachbranch
ontheclocktreetothedesiredclockskew.
2.7 BACKANNOTATION
BackannotationisthestepintheASICdesignowwheretheRCparasitics
in layout is extracted (Fig. 2.9). The path delay is calculated from these RC
parasitics. Fordeepsubmicrondesign, theseparasiticscancauseasignicant
increaseinpathdelay. Longroutinglinescansignicantlyincreasetheinter-
connectdelayforapath. Thiscouldpotentiallycausepathsthatarepreviously
12 ASICDESIGNFLOW
STEP6
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE2.8. DiagramindicatingStep6ofanASICdesignow: APR.
(in pre-layout) not critical in timing to be timing critical. It could also cause
pathsthataremeetingthetimingrequirementstonowbecomecriticalpaths
thatnolongermeetthetimingrequirements.
Backannotationisanimportantstepthatbridgesthedifferencesbetween
synthesis and physical layout. During synthesis, design constraints are used
by the synthesis tool to generate the logic that is required. However, these
design constraints are only an estimation of constraints that apply to each
module. The real physical constraints caused by the RC parasitics may or
may not reect the estimated constraints accurately. More likely than not,
the estimations are not accurate. As a result, these will cause differences
betweensynthesisandphysicallayout. Backannotationisthestepthatbridges
them.
2.8 POST-LAYOUTTIMINGANALYSIS
Post-layout timing analysis is an important step in ASIC design ow that
allowsrealtimingviolationssuchasholdandsetup, tobecaught(Fig. 2.10).
Thisstepissimilartopre-layouttiminganalysis, butitincludesphysicallayout
information.
In this step, the net interconnect delay information from back annotation
is fed into a timing analysis tool to perform post-layout timing analysis. Any
setup violations need to be xed by optimizing the paths that fail the setup
POST-LAYOUTTIMINGANALYSIS 13
STEP7
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No
Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE2.9. DiagramindicatingStep7ofanASICdesignow: backannotation.
violations to reduce the path delay. Any hold violation is xed by adding
bufferstothepathtoincreasethepathdelay.
Post-layout synthesis tweaks are used to make these timing xes during
resynthesis. Thisallowslogicoptimizationofthosefailingpaths.
Whenpost-layoutsynthesisiscompleted, APR, backannotation, andtiming
analysis are performed again. This will occur in a loop until all the timing
violationsarexed. Whentherearenolongertimingviolationsinthelayout
database, thedesignisreadyforlogicverication.
Note: Post-layout timing analysis is the same as pre-layout timing analysis,
exceptthatinpost-layouttiminganalysis, accuratenetdelayinformationfrom
physical layout (net delay information for the design is obtained from the
extractedlayoutparasitics)isused. Inpre-layouttiminganalysis, netdelayinfor-
mationisestimated.
2.9 LOGICVERIFICATION
Whenpost-layouttiminganalysisiscompleted, thenextstepislogicverica-
tion(Fig. 2.11). Thisstepactsasanalsanitychecktoensurethedesignhas
thecorrectfunctionality. Inthisstep, thedesignisresimulatedusingtheexist-
ingtestbenchesusedinStep3butwithadditionaltiminginformationobtained
fromlayout.
14 ASICDESIGNFLOW
STEP8
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Standardcell
technology
library
Yes
Timing
constraints
Pre-layout
timinganalysis
pass?
APR
No Yes
Tapeout
Pre-layout
synthesis
tweaks
Back
annotation
Post-layout
timinganalysis
pass?
Yes
Post-layout
synthesis
tweaks
andsynthesis
No
Logic
verication
pass?
Yes
No
FIGURE 2.10. Diagram indicating Step 8 of anASIC design ow: post-layout timing
analysis.
AlthoughthedesignhasbeenveriedinStep3, thedesignmayhavefail-
ures in Step 9. The failures may be caused by timing glitches or race condi-
tionsduetolayoutparastics. Iftherearefailures, thedesignerhastoxthese
failuresbyeithermovingbacktoStep2(RTLcoding)orStep8(post-layout
synthesistweaks).
Whenthedesignhasnallypassedlogicverication, itproceedstotapeout.
LOGICVERIFICATION 15
Specication RTLcoding Testbench
Simulation
Pass
No
Synthesis
Yes
APR
No Yes
Tapeout
Yes
No
Yes
No
STEP9
Post-layout
timinganalysis
pass?
Logic
verication
pass?
Back
annotation
Timing
constraints
Pre-layout
timinganalysis
pass?
Pre-layout
synthesis
tweaks
Standardcell
technology
library
Post-layout
synthesis
tweaks
andsynthesis
FIGURE2.11. DiagramindicatingStep9ofanASICdesignow: logicverication.