Q1. Write an assembly program to find the smallest among two numbers.

Answer - MVI B, 30H

MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 01H
OUT PORT1
HLT
LSS: MOV A, C
OUT PORT1
HLT




2. Explain the internal architecture of 8086.
Answer-


Figure shows the internal architecture of the 8086. Except for the instruction register, which is
actually a 6-byte queue, the control unit and working registers are divided into three groups
according to their functions. There is a data group, which is essentially the set of arithmetic
registers; the pointer group, which includes base and index registers, but also contains the
program counter and stack pointer; and the segment group, which is a set of special purpose
base registers. All of the registers are 16 bits wide.
The data group consists of the AX, BX, CX and DX registers. These registers can be used to
store both operands and results and each of them can be accessed as a whole, or the upper
and lower bytes can be accessed separately. For example, either the 2 bytes in BX can be used
together, or the upper byte BH or the lower byte BL can be used by itself by specifying BH or
BL, respectively. In addition to serving as arithmetic registers, the BX, CX and DX registers play
special addressing, counting, and I/O roles:
BX may be used as a base register in address calculations.
CX is used as an implied counter by certain instructions.
DX is used to hold the I/O address during certain I/O operations.
The pointer and index group consists of the IP, SP, BP, SI, and DI registers.
The instruction pointer IP and SP registers are essentially the program counter and stack
pointer registers, but the complete instruction and stack addresses are formed by adding the
contents of these registers to the contents of the code segment (CS) and stack segment (SS)
registers. BP is a base register for accessing the stack and may be used with other registers
and/or a displacement that is part of the instruction.



3. Explain the concept of Linking and Relocation.
Answer- In constructing a program some program modules may be put in the same source
module and assembled together; others may be in different source modules and assembled
separately. If they are assembled separately, then the main module, which has the first
instruction to be executed, must be terminated by an END statement with the entry point
specified, and each of the other modules must be terminated by an END statement with no
operand. In any event, the resulting object modules, some of which may be grouped into
libraries, must be linked together to form a load module before the program can be executed. In
addition to outputting the load module, normally the linker prints a memory map that indicates
where the linked object modules will be loaded into memory. After the load module has been
created it is loaded into the memory of the computer by the loader and execution begins.
Although the I/O can be performed by modules within the program, normally the I/O is done by
I/O drivers that are part of the operating system. All that appears in the user's program are
references to the I/O drivers that cause the operating system to execute them.
The process for a particular system may not correspond but the general concepts are the same.
The arrows indicate that corrections may be made after anyone of the major stages.
1. Segment Combination
In addition to the linker commands, the ASM-86 assembler provides a means of regulating the
way segments in different object modules are organized by the linker. Sometimes segments
with the same name are concatenated and sometimes they are overlaid. Just how the segments
with the same name are joined together is determined by modifiers attached to the SEGMENT
directives.
2. Access to External Identifiers
Clearly, object modules that are being linked together must be able to refer to each other. That
is, there must be a way for a module to reference at least some of the variables and/or labels in
the other modules. If an identifier is defined in an object module, then it is said to be a local (or
internal) identifier relative to the module, and if it is not defined in the module but is defined in
one of the other modules being linked, then It is referred to as an external (or global) identifier
relative to the module.



4. Explain how virtual address is converted into physical address
Answer- The more sophisticated memory management scheme can be achieved by the
hardware dynamic address translation design. For each memory reference, the logical address
output by the CPU is translated into the physical address, which is the address sent to the
memory by the memory management hardware. Logical addresses are the addresses that are
generated by the instructions according to the addressing modes. Because the logical
addresses may be different from the physical addresses, the user can design a program in a
logical space, also called a virtual space, without consideration for the limitations imposed by
the real memory. This provides two major advantages. First, dividing a program into several
pieces with each mapped into an area in real memory, a program need not occupy a contiguous
memory section. Therefore, memory fragmentation is reduced and less memory space is
wasted. Second, it is not necessary to store the entire program in memory while it is executing.
Whenever a portion of the program that is not currently in memory is referenced, the operating
system can suspend the program, load in the required section of code, and then resume the
program's execution. This allows a program's size to be larger than the actual memory
available. In other words, a user "virtually" has more memory to work with than actually exists.
With address translation hardware, the program is divided into segments according to the
logical structure of the program and the resulting memory management scheme is called
segmentation. When using segmentation, each logical address consists of two fields, the
segment number and the offset within the segment. The number of bits representing the
segment number governs the maximum number of segments allowed in a program, and the
number of bits allocated to the offset specifies the maximum segment size.



5. Subtract the hexadecimal number 1234 from DA57 using twos complement addition
method.
Answer- Converting the given hexadecimal numbers in binary:
DA57= (1101101001010111)
2
1s compliment= (0010010110101000)
2

2s compliment=(10010110101001)
2

1234=(1001000110100)
2

1s compliment= (0110111001011)
2

2s compliment=(110111001111)
2
On subtracting the binary 2s compliment of the given numbers we get ,
(1001011010101)
2
-(110111001111)
2
=(110100001010)
2

Converting the binary number (110100001010)
2
, we get,
(D0A)
16
Therefore the solution is (DOA)
16.




6. Explain different addressing modes of 8086.
Answer-



Data related addressing modes of 8086
These modes are:
Immediate-The datum is either 8 bits or 16 bits long and is part of the instruction
Direct-The 16-bit effective address of the datum is part of the instruction.
Register-The datum is in the register that is specified by the instruction. For a 16-bit operand, a
register may be AX, BX, CX, DX, SI, DI, SP, or BP, and for an 8-bit operand a register may be
AL, AH, BL, BH, CL, CH, DL, or DH.
Register Indirect-The effective address of the datum is in the base register BX or an index
register that is specified by the instruction.
Register Relative-The effective address is the sum of an 8- or 16-bit displacement and the
contents of a base register or an index register
Based Indexed-The effective address is the sum of a base register and an index register, both
of which are specified by the instruction
Relative Based Indexed-The effective address is the sum of an 8- or 16-bit displacement and a
based indexed address



7. Write a sequence of instructions to exchange two register contents using stack.
Answer- Let say the register is AX and BX. To exchange the register's content for both by using
stack it can be done by using POP and PUSH instruction. Stack behaves as last in first out
(LIFO).


PUSH AX // ax data will be copied into the stack, Stack pointer (SP) decreased by 2
PUSH BX // bx data will be copied into the stack 'above' ax data, Stack pointer (SP) decreased
by another 2
POP AX // the data that originally came from 'bx' will be popped into AX and removed from the
stack. Stack pointer added by 2
POP BX // the data that originally came from 'ax' (remember,bx data already removed from the
stack) will be popped into AX and removed from the stack. Stack pointer added by 2.

8. What is pure code? List some applications of pure code.
Answer- The application of serially shared procedures is rather limited, and a broader form of
sharing is necessary, a form in which a procedure is shared in a time multiplexed fashion or is
concurrently reusable. This means that a procedure must be such that it can be called by
another process before the execution of the procedure due to a prior call is completed. Such a
procedure is said to be reentrant. A reentrant procedure must consist of code, called pure code,
which does not modify itself. To meet this requirement a reentrant procedure can store the data
to be modified by the routine only in memory locations that are associated with the calling
process; it cannot, even temporarily, store such data in locations that are local to it. To see this,
suppose that TEMP is a local variable in the reentrant procedure and that it is used to store an
intermediate result, and consider the following sequence of events:
1. Process 1 is running and calls the reentrant procedure.
2. The reentrant procedure puts an intermediate result in TEMP.
3. Process 2 gains control of the CPU.
4. Process 2 calls the reentrant procedure.
5. The reentrant procedure again puts an intermediate result in TEMP.



9. Differentiate between data coupling and control coupling
Answer- During a top-down design, it is important to recognize the fundamental nature of the
communication between the modules, the data coupling, and the way in which the modules call
and control each other, the control coupling It is generally unwise to break a function (e.g.,
evaluating a determinant) into modules on the same level, modules that do not form a
Sub hierarchical structure. Beyond the functional subdivision, the decisions regarding the
subdivision of a program should be based on data and control coupling
Control coupling:
Control coupling is one module controlling the flow of another, by passing it information
on what to do (e.g., passing a what-to-do flag)
Data coupling:
Data coupling is when modules share data through, for example, parameters. Each
datum is an elementary piece, and these are the only data shared (e.g., passing an
integer to a function that computes a square root)


10. Explain the 8288 Bus controller.
Answer- This circuitry is for converting the status bits S0 , S1 and S2 into the I/O and memory
transfer signals needed to direct data transfers, and for controlling the 8282 latches and 8286
transceivers. It is normally implemented with an Intel 8288 bus controller. Also included in the
system is an interrupt priority management device; however, its presence is optional.
The S0, S1 and S2 status bits specify the type of transfer that is to be carried out and when
used with an 8288 bus controller they obviate the need for the M/IO , WR , INTA , ALE, and
DT/R and DEN signals that are output over pins 24 through 29 when the processor is operating
in minimum mode. Except for the case S0 =S1= 1, S2 = 0 indicates a transfer between an I/O
interface and the CPU and S2 = 1 implies a memory transfer. The S1 bit specifies whether an
input or output is to be performed. From the status the 8288 is able to originate the address
latch enable signal to the 8282s, the enable and direction signals to the 8286 transceivers and
the interrupt acknowledge signal to the interrupt controller.