Compact Surface Potential Model for FD SOI

MOSFET Considering Substrate Depletion Region

Pradeep Agarwal, Govind Saraswat and M. Jagadesh Kumar, Senior Member, IEEE
IEEE Trans. on Electron Devices, Vol.55, pp.789-795, March 2008.

Abstract: In this paper, by solving the 1-D Poisson equation using appropriate boundary

conditions, we report a closed form surface potential solution for all the three surfaces (gate

oxide-silicon film interface, silicon-film-buried oxide interface and buried oxide-substrate

interface) of fully depleted SOI MOSFET by considering the effect of substrate charge

explicitly. During the model derivation, it is assumed that silicon film is always fully depleted

and the back silicon film surface is never inverted. The calculated values of the surface potentials

obtained from the proposed model agree well with the iterative solution of exact Poisson

equation with a maximum relative error bound of 0.3%. In the entire model, only 2 square roots,

1 exponential, 2 logarithm terms are used and the continuity and differentiability of the resultant

surface potential solutions are ensured making the proposed model computationally efficient.

Index Terms: Fully Depleted SOI MOSFET, Surface potential, Threshold voltage, Compact
modeling, Numerical solution.

Manuscript received ……
The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Hauz Khas, New Delhi 110 016, India (e-mail:
mamidala@ieee.org).

1
 I. INTRODUCTION

Surface potential based MOSFET models provide consistent and accurate expressions for

terminal currents and charges valid in all regions of operations [1]-[8]. These models have

emerged as a better alternative to the threshold-voltage based models as they are suitable for

simulating circuits with low-power supply voltages and also allow physical modeling of sub-

threshold region which were the main drawbacks of the threshold-voltage based models [9]-[15].

Many models based on surface potential approach have been developed for bulk MOSFETs and

implemented in different circuit simulators [2]-[5]. The same modeling approach has been

extended to partially depleted SOI (PDSOI) MOSFET with a special consideration to effects,

specific to PDSOI MOSFET, such as floating body and self-heating effects [16]-[17]. But

modeling of fully depleted SOI (FDSOI) MOSFET is quite different due to appearance of

depletion charge in substrate region. The previously reported FDOI models [18]–[20] do not

consider the substrate depletion and hence cannot be used for FDSOI devices having low

substrate doping. The recently published FDSOI model ‘Hiroshima University semiconductor

technology academic research centre IGFET model silicon-on-insulator (HiSIM-SOI)’ [21]

considers the substrate depletion explicitly and is based on surface potential approach . However,

the model does not derive close form single equation solution of surface potentials by solving

Poisson equation. Instead it uses iterations to compute surface potentials at differnet surfaces of

FDSOI device which makes the model computationally inefficient. Hence it becomes important

to have a close formed single equation solution of surface potential for different surfaces of

FDSOI device so that it can be used in circuit simulators. To the best of our knowledge, there is

no such solution available in the literature which solves surface potentials at all surfaces of

2
FDSOI MOSFET explicitly considering the effect of substrate depletion.

Therefore, the purpose of this work is to obtain a closed form analytical approximation for

potentials at the three surfaces of FDSOI MOSFET, namely front oxide-silicon film surface φ sf ,

buried oxide-silicon film interface φ sb , and buried oxide-substrate interface φ sbulk . For this

purpose, three different equations are obtained by solving the 1-D Poisson equation in vertical

direction and applying the boundary conditions at different surfaces. These three equations are

solved for various regions of operation and unified with the help of smoothing functions. No

discontinuity in the derivative of the surface potentials are found even though three types of

smoothing functions are used.

II. IDEAL SURFACE POTENTIAL

1-D Poisson equation of a FD-SOI MOSFET, shown in Fig. 1, can be written as [11]

∂ 2φ ( y )
=−
1
( p( y) − n( y ) − N ch ) (1)
∂y 2
ε Si

where φ ( y ) is the potential, ε Si is the dielectric constant of silicon, p(y) and n(y) are the hole and

electron concentration, respectively and Nch is the doping in the silicon layer . Equation (1) can

be further expressed as:

∂ 2φ ( y ) qN ch ⎧⎪ ⎡ ⎛ φ ( y) ⎞ ⎤ ⎛ 2φ +V ⎞⎡ ⎛ φ ( y ) ⎞ ⎤ ⎫⎪
=− ⎨ ⎢exp ⎜⎜ − ⎟⎟ − 1⎥ − exp ⎜⎜ − F CB ⎟⎟ ⎢exp ⎜⎜ ⎟⎟ − 1⎥ ⎬ (2)
∂y 2
ε Si ⎪⎩ ⎣ ⎝ φt ⎠ ⎦ ⎝ φt ⎠⎣ ⎝ φ t ⎠ ⎦ ⎪⎭

where φ F is the Fermi potential , φ t is the thermal voltage and VCB is channel-floating body

potential which varies from Vsb at source to Vsb + Vds at drain. Although VCB has been referred

to by different names and symbols in literature as channel potential (Vcb) in [17], channel

floating body potential (Vcb) in [20], and bulk referenced quasi Fermi potential (V) in [22] but

3
we will call it here as channel-floating voltage.

∂φ ( y )
Multiplying both sides of eq. (2) by 2 and then integrating from buried oxide-silicon film
∂y

interface φ sb to front oxide-silicon film surface φ sf , we get

⎧⎪ ⎡ ⎛ φ sf
2 2
⎡ ∂φ ( y ) ⎤ ⎡ ∂φ ( y ) ⎤ 2qN ch ⎞ ⎛ φ ⎞⎤
⎢ ⎥ −⎢ ⎥ =− ⎨− φt ⎢exp⎜⎜ − ⎟⎟ − exp⎜⎜ − sb ⎟⎟⎥ − (φ sf −φ sb)
⎣ ∂y φ ( y )=φ sf ⎦ ⎣ ∂y φ ( y )=φ sb ⎦ ε Si ⎪⎩ ⎣ ⎝ φt ⎠ ⎝ φ t ⎠⎦

⎛ 2φ +V ⎞⎛⎜ ⎡ ⎛ φ sf ⎞ ⎛φ ⎞⎤ ⎞⎫⎪
− exp⎜⎜ − F CB ⎟⎟ φt ⎢exp⎜⎜ ⎟⎟ − exp⎜⎜ sb ⎟⎟⎥ − (φ sf −φ sb ) ⎟⎬ (3)
⎝ φt ⎠⎜⎝ ⎣ ⎝ φ t ⎠ ⎝ φt ⎠⎦ ⎟⎪
⎠⎭

The following boundary conditions need to be used in eq. (3):

1. Electric flux (displacement) at the front oxide/Si film interface is continuous.

∂φ ( y ) V g −φ sf ε ox (4)
− =
∂y φ ( y ) = φ t ox ε Si
sf

where ε ox is the dielectric constant of the gate oxide, t ox is the front gate oxide thickness, and

V g =V GS −V FB where V GS is the gate-to-source bias voltage and VFB is the flat-band voltage.

2. Electric flux at the interface of buried oxide/Si film is continuous.

∂φ ( y ) φ −φ
= sb sbulk ε ox
(5)
−
∂y φ ( y )=φ t box ε Si
sb

where ε ox is the dielectric constant of the gate oxide, t box is the buried oxide thickness,

φ sb is the surface potential at buried oxide-silicon layer and φ sbulk is the surface potential at

the buried oxide-substrate interface.

Substituting the above two boundary conditions in equation (3) gives us

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 2
Cbox ⎧⎪ ⎡ ⎛ φ sf ⎞ ⎛ φ ⎞⎤
(V g−φ s) − 2 (φ sbulk−φ sb)2 = −γ 2 ⎨−φt ⎢exp⎜⎜ −
2
⎟⎟ − exp⎜⎜ − sb ⎟⎟⎥ − (φ sf −φ sb)
Cox ⎪⎩ ⎣ ⎝ φt ⎠ ⎝ φt ⎠⎦

⎛ 2φ +V ⎞⎛⎜ ⎡ ⎛ φ sf ⎞ ⎛φ ⎞⎤ ⎞⎫⎪
− exp⎜⎜ − F CB ⎟⎟ φt ⎢exp⎜⎜ ⎟⎟ − exp⎜⎜ sb ⎟⎟⎥ − (φ sf −φ sb ) ⎟⎬ (6)
⎝ φt ⎠⎜⎝ ⎣ ⎝ φt ⎠ ⎝ φt ⎠⎦ ⎟⎪
⎠⎭

2qN chε si ε ox
where γ = and C ox =
C ox t ox

Eq. (6) has three unknowns (namely φ sf , φ sb and φ sbulk ). Therefore, two more equations are

needed to solve it and they can be obtained by solving Poisson equation in the silicon film layer

and the substrate region as explained in Appendix-A.

C box
φ sf −φ sb = α + (φ sb −φ sbulk ) (7)
C soi

φ sb =φ s bulk +γ bulk φ sbulk (8)

2qN subε si qN cht soi2 ε ox

where γ bulk= , α= and C box =
C box 2ε Si t box

Equations (6), (7) and (8) together describe the exact Poisson equation for a FDSOI MOSFET

and are obtained without any approximation except the assumptions that the back silicon surface

and the substrate region never go into inversion and that the device always remains in fully

depleted condition. These equations can be solved iteratively to get the exact values of all three

surface potential expressions.

A single closed form solution for the surface potential cannot be obtained for the FD-SOI

MOSFET as in the case of bulk MOSFET due to non-linear nature of the equations (6), (7) and

(8). Hence separate solutions are first obtained in the weak and strong inversion regions and then

they are combined to get a single closed form expression as discussed in the following sections.

5
 III. SURFACE POTENTIAL SOLUTION

To obtain surface potential solution, it is further assumed that the MOSFET does not operate in

the accumulation region which is a quite valid assumption as the accumulation region is rarely

used except in some specific applications. Hence, when φ sf >3 φ t , equation (6) become

1⎛ 2
2⎞
⎛ ⎛ φ sf −φ sb ⎞ ⎞ ⎛ − 2φ F −V CB+φ t ⎞
⎜ (V −φ ) 2 C box
− (φ −φ ) ⎟ = (φ −φ ) + (φ )⎜1 − exp⎜⎜ − ⎟⎟ ⎟ exp⎜⎜ ⎟⎟ (9)
γ 2 ⎜⎝
sb ⎟ t ⎜ ⎟
φ φt
g sf sbulk sf sb
C ox 2 ⎠ ⎝ ⎝ t ⎠⎠ ⎝ ⎠

Finally, equations (7), (8), (9) are solved for the weak and strong inversion cases so that they can

be unified with the help of smoothing functions as in the case of bulk MOSFET.

A. Weak Inversion

The MOSFET operates in weak inversion when φ F < φ sf < φ 2 F . In this region, we can neglect

the small inversion charge appearing at the front silicon film surface as in the case of bulk

MOSFET. Fig. 2 shows the electric field variation in the vertical direction when the MOSFET is

operating in weak inversion where the solid line represents the electric field at a certain gate

voltage VGS. We define VC as the minimum voltage necessary to keep the device in fully

depleted mode. In Fig.2, the dotted line shows the electric field variation in the vertical direction

at VC. At this voltage, the electric field at the buried oxide-silicon layer surface becomes zero.

Therefore, VC can be written as:

qN Ch t soi
V C= α + (10)
C ox

Voltage Vg (= VGS – VFB) is equal to the total area under the electric field curve, shown in Fig. 2

and can be written as:

1 E b2ε Si E ε
V g −V C = + (t ox +t box ) b Si + E b t soi (11)
2 qN sub ε ox

6
 where Eb as electric field at the buried oxide/substrate surface when the device has just reached

full depletion and Nsub is the substrate doping. From Eq.(11), Eb can be written in terms of Vg as:

2
qN sub ⎛ qN sub ⎞
Eb= − + ⎜ ⎟ + 2qN sub (V g−V C) (12)
C eff ⎜ C ⎟ ε Si
⎝ eff ⎠

1 1 1 1
where = + +
C eff C ox C box C soi

Finally the value of Eb is used to obtain the expressions of all three surface potentials in weak

inversion as:

ε Sit ox qN ch t soi
φ sf ,weak =V g − (E b+ ) (13)
ε ox ε Si

1 E b2ε Si
φ sbulk , weak = (14)
2 qN sub

t box E b ε Si
φ sb , weak =φ sbulk ,weak + (15)
ε ox

Where φ sf ,weak , φ sb,weak and φ sbulk ,weak denote the front surface potential, back surface potential and

bulk surface potential in the weak inversion region, respectively.

B. Strong Inversion

In the strong inversion region, equation (9) can be rearranged as

⎛ ⎞
⎜ 1 ⎛ C 2
⎞ ⎟
⎜ 2 ⎜⎜ (Vg −φ sf ,strong) 2 − box (φ − φ sb, strong ⎟) 2
⎟ − (φ −φ ) ⎟
⎜γ ⎝
sbulk, strong sf , strong sb, strong
Cox2 ⎠ ⎟
φ sf ,strong= 2φ F +VCB +φ t λn⎜ + 1⎟ (16)
⎛ φ −φ
⎟⎞
⎛ sf , strong sb , strong ⎞
−⎜⎜
⎜ ⎜ φt ⎟⎟ ⎟
⎜ φt ⎜1 −e ⎝ ⎠
⎟ ⎟
⎜ ⎜ ⎟ ⎟
⎝ ⎝ ⎠ ⎠

Where φ sf ,strong , φ sb,strong and φ sbulk ,strong denote the front surface potential, back surface potential

7
and bulk surface potential in the strong inversion region, respectively. The value of φ sb ,strong is

given by eq (8) and φ sbulk ,strong can be obtained from eqs (7) and (8) as:

(
φ sbulk , strong = − β + β 2 −α + (φ sf , strong ) )
2
(17)

⎛ C box ⎞
where β = 0.5 γ bulk ⎜⎜1 + ⎟
⎝ C soi ⎟⎠

In equation (16), an additional 1 is added inside the logarithmic term to match the value of

φ sf ,strong obtained from this equation to the weak inversion surface potential φ sf ,weak obtained from

equation (13) at the intersection of the two regions. This ensures the continuity of the final

surface potential solution for all regions of operation.

Equation (16) is a non-linear equation in φ sf ,strong and a direct solution of it cannot be

obtained. Two approximations are suggested for equation (16) in the case of bulk and PDSOI

MOSFET cases [17, 22]. The first approximation for the surface potential ( φ sf1 ,strong ) used in [17]

is given as:

φ sf ,strong1= 2φ F +V CB (18)

But in [22], it is shown that the use of φ sf1 ,strong results in a large error at strong inversion

region. It has also been shown in [22] that a replacement of φ sf ,strong by a value several times

higher than 2 φ F + VCB results in a good modeling at strong inversion but inaccurate modeling at

moderate inversion region which is crucial for low voltage designs. Hence this approximation

was also rejected.

The second approximation φ sf2 ,strong for the surface potential φ sf ,strong is suggested as [22]:

8
 φ sf , weak − 2 φ F − V
φ sf2 , strong = 2 φ F + V CB + CB
(19)
⎛φ − 2φ F −V
2
⎞
1 + ⎜⎜ sf , weak CB
⎟⎟
⎝ ηφ t ⎠

The model for φ sf2 ,strong is a continuous function changing smoothly from 2 φ F + VCB at the onset

of strong inversion region to 2 φ F + VCB + ηφ t at the high values of gate voltages. Here,η is a

constant and its numerical value is between 4 and 6 to get a better approximation for φ s in the

case of bulk MOSFETs [17, 22]. Therefore, in the present study, η is taken as 6 for the range of

doping and oxide thicknesses used. This approximation results in a more accurate final solution.

Fig. 3 shows a comparison between the exact solution of front surface potential obtained by

solving equations (7), (8) and (9) iteratively and the analytical strong inversion surface potential

solution obtained from equations (16), (18) and (19). Approximations 1 and 2 represent the

solution of (16) with φ sf ,sttrong in the right side of the equation given by (18) and (19),

respectively.

Direct use of approximation (19) in equation (16) results in discontinuities at 2 points

which can cause serious problems in circuit simulators and therefore a sharp increase in

simulation time. Hence these discontinuities are removed by replacing 2 φ F + VCB in equation

(19) by a function f which is continuous for all values of gate voltage changes from φ sf ,weak at

weak inversion to 2 φ F + VCB at strong inversion [20, 22]:

φ sf , weak +2φ F +V CB− (φ sf , weak −2φ F −V CB) 2 +4δ 2 2

f = (20)
2

where δ 2 is a fitting parameter and its value is taken as 0.1 [20, 22]. The removal of the

discontinuities is demonstrated by Fig. 4. The figure shows the plots of weak inversion front

9
surface potential solution φ sf ,weak , strong inversion front surface potential solution φ sf ,sttrong

obtained from equations (16), (18), (19) and (20), and iterative solution of surface potential

obtained from (6), (7), and (8). Good match is achieved in both weak and strong inversion

region. Also no discontinuity is observed in strong inversion solution.

C. Single Piece Model

After obtaining separate solutions for the surface potentials in weak and strong inversion regions,

we need to unify these two solutions with the help of a good smoothing function. The smoothing

function (i) should be continuous and differentiable and (ii) should ensure that each of the

approximations for the weak and strong inversions is reduced smoothly to insignificance outside

of their respective regions of validity. Since the nature of the front surface potentials in the weak

and strong inversion conditions in our case is similar to that of a PDSOI MOSFET, we have used

a well known smoothing function to satisfy the above two requirements which has been

successfully used in the case of PDSOI MOSFET [17]. The smoothing function is given as:

φ sf , strong−φ sf , weak
⎛ ⎞
⎜
φ sf =φ sf ,strong−φ t ln 1 +e φt ⎟
⎜ ⎟ (21)
⎝ ⎠

Equation (21) relies on the fact that in strong inversion, φ sf ,strong >> φ sf ,weak , and in the weak

inversion φ sf ,strong << φ sf ,weak . The continuity and infinite differentiability of all the smoothing

functions ensure the continuity and infinite differentiability of the final φ sf . After obtaining φ sf ,

φ sb and φ sbulk are obtained by using φ sf from equation (21) in equation (7) and (8).

10
 IV. MODEL VERIFICATION

Since equations (6), (7) and (8) are obtained without making any approximations (except the

assumptions that no inversion takes place at the back surface and the silicon layer is fully

depleted), we have compared our model results to the iterative solution of Poisson equations (6),

(7) and (8). The model calculations were performed using MATLAB7. We used a large range of

parameters to verify our model. The parameters used in our simulation are given in Table 1.The

parameter ranges are chosen such that the device operates in the fully depleted mode and no

inversion of back surface or substrate takes place. Although the model is verified for all sets of

parameters given in the table, only important results are summarized here due to space

limitations.

Fig. 5 shows the variation of surface potentials φ sf , φ sb and φ sbulk versus gate voltage for a front

oxide thickness of 3 nm, buried oxide thickness of 100 nm and silicon film thickness of 50 nm.

The silicon film doping is kept sufficiently high (1017 cm-3) to ensure the absence of channel at

the back silicon layer surface. The substrate doping is selected quite low (1015 cm-3) to clearly

demonstrate the effect of substrate depletion charge on the front surface potential. When the

substrate doping is low, a large potential drop appears across the substrate depletion region,

which changes the channel inversion charge density significantly. Fig. 5 clearly shows a large

drop across substrate region given by φ sbulk . The surface potentials from analytical solution are in

close proximity with the simulation results.

To further highlight the effect of substrate depletion, we have plotted φ sbulk for different values of

substrate doping in Fig. 6. At low values of substrate doping (e.g. 1015 cm-3), a large drop

appears across the substrate depletion region. However, the voltage drop decreases as the

substrate doping is increased.

11
Fig. 7 shows variation of front surface potential φ sf with gate voltage for different values of

channel floating voltage VCB. We notice that the surface potential varies linearly in weak

inversion region and then saturates at high values of gate voltages similar to that observed in the

case of bulk MOSFETs.

The simulation results are in close proximity with the results obtained from the iterative solution

of Poisson equation for all values of the parameters given in Table 1. The maximum relative

error in the surface potentials is below 0.3% for the range of parameters used. The relative error

is calculated as

Relative Error = Analytical Solution – Iterative Solution × 100 % (22)

Iterative Solution

Equation (22) is used to evaluate relative error for various parameters and the maximum of these

errors is taken as the maximum relative error.

V. CONCLUSION

For the first time, we have reported a closed form surface potential solution for all three surfaces

of FDSOI MOSFET. The effect of substrate charge is considered explicitly. The 1-D Poisson

equation is solved in the vertical direction using appropriate boundary conditions. The model

results are compared with the iterative solution of exact Poisson equation as the Poisson equation

is known to describe the device behaviour accurately. The calculated values of the surface

potentials obtained from the proposed model agree well with the iterative solution. Maximum

relative error is within a bound of 0.3%. During the model derivation, it is assumed that the

MOSFET is operating in fully depleted mode and back silicon film surface or substrate is never

inverted, which are quite valid assumptions for modern day’s FDSOI devices. In the entire

12
model, for front silicon film surface only 2 square roots, 1 exponential, 2 logarithms terms are

used; hence the model is computationally efficient. Furthermore, the continuity and

differentiability of all the smoothing functions used ensure the continuity and differentiability of

the resultant surface potential solutions. Our model can be used in the surface potential based

models for deriving the charge and current expressions. The non-ideal effects and the specific

detour field present in the FDSOI MOSFET can be incorporated in the same way as done in

HiSIM Model.

13
 APPENDIX- A

Derivation of equation (7) and (8)

Assuming inversion at the back silicon film surface and the substrate to be absent, Poisson

equation for the substrate and silicon film are given by equations (A1) and (A2), respectively:

∂ 2φ ( y )
=−
1
(− qN sub ) (A1)
∂y 2
ε Si

∂ 2φ ( y )
=−
1
(− qN ch ) (A2)
∂y 2
ε Si

For simplicity, we have ignored the small voltage drop appearing across the front surface

inversion charge layer while writing eq. (A2).

∂φ ( y )
Multiplying both sides of eq. (A1) and (A2) by 2 and then integrating eq (A1) from the
∂y

buried oxide-substrate interface ( φ ( y ) =φ sbulk ) to deep neutral substrate region ( φ ( y )= 0 ) and eq

(A2) from a point y distance below the front oxide-silicon film interface ( φ ( y ) ) to the buried

oxide-silicon film interface ( φ ( y )=φ sb ), we arrive at following equations, respectively:

2 2
⎡ ∂φ ( y ) ⎤ ⎡ ∂φ ( y ) ⎤
⎢ ⎥ −⎢ ⎥ =
2qN ch
(φ ( y ) −φ sb ) (A3)
⎣ ∂ y φ ( y ) =φ ( y ) ⎦ ⎣ ∂ y φ ( y ) = φ sb ⎦ ε Si

2
⎡ ∂φ ( y ) ⎤
⎢ ⎥ =
2qN sub
(φ sbulk ) (A4)
⎣ ∂ y φ ( y ) = φ sbulk ⎦ ε Si

∂φ ( y ) ∂φ ( y )
By noting the identity = = E b , where Eb is the electric field at the
∂y φ ( y ) =φ sbulk ∂y φ ( y )=φ xb

buried oxide-substrate interface as shown in Fig. 2, and using this identity in eq. (A3) and (A4)

we get,

14
 2
⎡ ∂φ ( y ) ⎤
⎢ ⎥ − Eb =
2 2qN ch
(φ ( y ) −φ sb ) (A5)
⎣ ∂y φ ( y )=φ ( y ) ⎦ ε Si

Eb =
2 2qN sub
(φ sbulk ) (A6)
ε Si

Applying the Poisson equation in the charge free buried oxide region, we obtain the value of Eb

as

Eb =
(φ sb−φ sbulk ) ε ox (A7)
t box ε si

By substituting the value of Eb from eq. (A7) in eqs (A5) and (A6) and then integrating equation

(A5) from the front oxide-silicon film interface ( φ ( y ) =φ sf ) to the buried oxide-silicon film

interface ( φ ( y )=φ sb ), the following equations are obtained:

C box
φ sf −φ sb = α + (φ sb −φ sbulk ) (A8)
C soi

φ sb =φ s bulk +γ bulk φ sbulk (A9)

2qN subε si qN cht soi2 ε ε ox

where γ bulk= , α= , C soi = ox and C box =
C box 2ε Si t soi t box

Eqs. (A8) and (A9) are eqs. (7) and (8) of the main text, respectively.

15
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[13]J. Benson, N. V. D'Halleweyn, W. Redman-White, C. A. Easson, M. J. Uren, O. Faynot and

J. –L. Pelloie, “A physically based relation between extracted threshold voltage and surface

potential flat band voltage for MOSFET compact modeling,” IEEE Trans. Electron Devices,

Vol.48, no. 5, pp.1019-1021, May 2001.

[14]M. Miura-Mattausch, U. Feldmann, A. Rahm and M. Bollu, “Unified complete MOSFET

model for analysis of digital and analog circuits,” IEEE Trans. Comput.-Aided Design Integr.

Circuits Syst., vol. 15, no. 1, pp. 1-7, Jan. 1996.

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[15] M. Miura-Mattausch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and

H. Masuda, “100 nm-MOSFET model for circuit simulation: Challenges and solutions.”

IEICE Trans. Electron, vol. E86-C, no. 6, pp. 1009-1021, Jun 2003.

[16]G. Gildenblat, W. Wu, X. Li, H. Wang, G. Workman, S. Veeraraghavan and C. McAndrew,

“SP-SOI: A third generation surface potential based compact MOSFET model,” Proc. IEEE

Custom Integrated Circuits Conference, pp. 819-822, Sept. 2005.

[17]M. S. L. Lee, B. N. Tenbroek, W. Redman-White, J. Benson, and M. J. Uren, “A Physically

Based Compact Model of Partially Depleted SOI MOSFETs for Analog Circuit Simulation,”

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[19]G. F. Niu, R. M. M. Chen, and C. Ruan, “Comparisons and extension of recent surface

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Figure Captions

Figure 1 Cross-sectional view of the Fully Depleted SOI MOSFET.

Figure 2 Electric field profile from the Si/SiO2 interface of the front gate oxide towards the
substrate. The solid lines indicate the electric field distribution for a given gate
voltage. The dashed lines show the electric field when the silicon film is just
depleted.
Figure 3 Comparison of front surface potential φ sf obtained iteratively ( φ sf ,iterative from eqs. (7),

(8) and (9)) and analytically ( φ sf ,analytic from eqs. (16), (18) and (19)). Parameters used
17 -3 15 -3
are: VFB = -0.5 V, Vsub = 0 V, Nch = 10 cm , Nsub = 10 cm , tox = 3 nm, tbox = 100
nm and tsoi = 50 nm.
Figure 4 Weak inversion front surface potential ( φ sf ,weak ), strong inversion front surface

potential ( φ sf ,strong ) and front surface potential obtained iteratively ( φ sf ,iterative ) (from

eqs. (7), (8) and (9)) versus gate voltage. Parameters used are: VFB = -0.5 V, Vsub = 0
17 -3 15 -3
V, Nch = 10 cm , Nsub = 10 cm , tox = 3 nm, tbox = 100 nm, tsoi = 50 nm.
Figure 5 The three surface potentials φ sf , φ sb and φ sbulk versus gate voltage. Parameters used
17 -3 15 -3
are: VFB = -0.5 V, Vsub = 0 V, Nch = 10 cm , Nsub = 10 cm , tox = 3 nm, tbox = 100
nm, tsoi = 50 nm.
Figure 6 The substrate surface potential φ sbulk versus gate voltage for different values of
17 -3
Substrate doping. Parameters used are: VFB = -0.5 V, Vsub = 0 V, Nch = 10 cm , tox
= 3 nm, tbox = 100 nm, tsoi = 50 nm.
Figure 7 The front surface potential φ sf versus gate voltage for different values of VCB.
17 -3 15 -3
Parameters used are: VFB = -0.5 V, Vsub = 0 V, Nch = 10 cm , Nsub = 10 cm , tox =
3 nm, tbox = 100 nm, tsoi = 50 nm.

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Table 1: Device parameters used in the result verification of FDSOI MOSFET

Parameter
Front oxide thickness, tox
Silicon film thickness, tsoi
Buried oxide thickness, tbox
Silicon film doping, Nch
Substrate doping, Nsub
Value
3 nm, 5 nm, 7 nm, 10 nm
25 nm, 50 nm, 100 nm
25 nm, 50 nm, 100 nm, 200 nm
5x1016 cm-3,1017 cm-3, 3x1017 cm-3
1015 cm-3, 5x1015 cm-3, 1016 cm-3, 5x1016
cm-3, 1017 cm-3

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 Gate

Source Drain

y=0 tox Gate oxide

n+ Nch tsoi n+
y

φ sf
tbox φ sb
Buried oxide

Substrate (Nsub) φ sbulk

VSub=0

Figure 1
.

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

tox tsoi tbox

Gate Gate Silicon Buried Substrate
oxide film oxide

Eb y

Figure 2

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

1.0 Approximation 1
eq(18)
0.9
φsf,iterative,(V)’φsf,analytic(V)

0.8 Approximation 2
eq (19)
0.7

0.6
φsf,iterative
0.5

0.4
0 0.1 0.2 0.3 0.4 0. 0.6 0.7
Gate Voltage,VGS (V)

Figure 3

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

1.3
φsf,iterative,(V)’ φsf,strong,(V)’ φsf,weak,(V)

1.2
1.1 φsf,weak
1.0 φsf,strong
0.9
0.8
0.7 φsf,iterative
0.6
0.5
0.4
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Gate Voltage,VGS (V)

Figure 4

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

1.0
0.9 Model
Iteration φsf
φsf (V)’ φsb (V)’ φsbulk (V)

0.8
0.7
0.6 φsb
0.5
0.4
0.3
φsbulk
0.2
0.1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Gate Voltage,VGS (V)

Figure 5

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

0.4
Model
Iteration NSUB
0.3 = 1015 cm-3
φsbulk (V)

0.2 = 5 ×1015 cm-3

= 1016 cm-3
0.1

= 5 ×1016 cm-3
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Gate Voltage, VGS(V)

Figure 6

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Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

5.0
Model 4V
4.5
Iteration
4.0
3V
3.5
φsf (V)

3.0
2V
2.5
2.0
1V
1.5
1.0
VCB = 0 V
0.5
0
0 1.0 2.0 3.0 4.0 5.0
Gate Voltage,VGS (V)

Figure 7

27
Submitted to IEEE TRANSACTIONS ON ELECTRONC DEVICES

Pradeep Agarwal has completed his B.Tech. degree in electrical engineering from
Indian Institute of Technology, Delhi, India. Device modeling and simulation for
nanoscale applications is one of his research interests.

Govind Saraswat has completed his B.Tech. degree in electrical engineering

from Indian Institute of Technology, Delhi, India. Device modeling and
simulation for nanoscale applications is one of his research interests.

M. Jagadesh Kumar (M’95-SM’99) was born in Mamidala, Andhra Pradesh,

India. He received the M.S. and Ph.D. degrees in electrical engineering from the
Indian Institute of Technology, Madras, India.
From 1991 to 1994, he performed postdoctoral research in modeling and
processing of high-speed bipolar transistors with the Department of Electrical and
Computer Engineering, University of Waterloo, Waterloo, ON, Canada. While
with the University of Waterloo, he also did research on amorphous silicon TFTs. From July
1994 to December 1995, he was initially with the Department of Electronics and Electrical
Communication Engineering, Indian Institute of Technology, Kharagpur, India, and then joined
the Department of Electrical Engineering, Indian Institute of Technology, Delhi, India, where he
became an Associate Professor in July 1997 and a Full Professor in January 2005. His research
interests are on Nanoelectronic devices, modeling and simulation for nanoscale applications,
integrated-circuit technology, and power semiconductor devices. He has published extensively in
the above areas with two book chapters and more than 120 publications in refereed journals and
conferences. His teaching has often been rated as outstanding by the Faculty Appraisal
Committee, IIT Delhi.
Dr. Kumar is a Fellow of (i) Indian National Academy of Engineering (INAE) and (ii) the
Institution of Electronics and Telecommunication Engineers (IETE), India. He was a recipient of
the 29th IETE Ram Lal Wadhwa Gold Medal for distinguished contribution in the field of
semiconductor device design and modeling. He was also the first recipient of ISA-VSI
TechnoMentor Award given by the India Semiconductor Association to recognize a
distinguished Indian academician or researcher for playing a significant role as a mentor and
researcher. He is an Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES and an
Associate Editor of Journal of Computational Electronics. He is also on the Editorial Board
of Recent Patents on Nanotechnology; Recent Patents on Electrical Engineering;
Journal of Low Power Electronics; Journal of Nanoscience and Nanotechnology; and
IETE Journal of Research as a subject area Honorary Editor for Electronic Devices and
Components. He has reviewed extensively for different journals including IEEE
TRANSACTIONS ON ELECTRON DEVICES, IEEE TRANSACTIONS ON DEVICE AND
MATERIALS RELIABILITY, Electronics Letters, and Solid-state Electronics.

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