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2012-13

Design of a Rail-to-
Rail Class-B
Buffer with DC
Level-Shifting
Current Mirror for
LCD Column Drivers
Sharath A C

D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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CHAPTER-1
INTRODUCTION
1.1 GENERAL INFORMATION
A liquid crystal display (LCD) is a flat panel display, electronic visual
display, or video display that uses the light modulating properties of liquid crystals.
Liquid crystals do not emit light directly.
LCDs are available to display arbitrary images (as in a general-purpose computer
display) or fixed images which can be displayed or hidden, such as preset words, digits,
and 7-segment displays as in a digital clock. They use the same basic technology,
except that arbitrary images are made up of a large number of small pixels, while other
displays have larger elements.
LCDs are used in a wide range of applications including computer
monitors, televisions, instrument panels, aircraft cockpit displays, and signage. They are
common in consumer devices such as video players, gaming
devices, clocks, watches, calculators, and telephones, and have replaced cathode ray
tube (CRT) displays in most applications. They are available in a wider range of screen
sizes than CRT and plasma displays, and since they do not use phosphors, they do not
suffer image burn-in. LCDs are, however, susceptible to image persistence.
The LCD screen is more energy efficient and can be disposed of more safely than a
CRT. Its low electrical power consumption enables it to be used in battery-
powered electronic equipment. It is an electronically modulated optical device made up
of any number of segments filled with liquid crystals and arrayed in front of a light
source (backlight) or reflector to produce images in colour or monochrome. Liquid
crystals were first developed in 1888.






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CHAPTER 2
LITRATURE SURVEY
Sl.
No
Year Title Method Result
1 2011
A RAIL-TO-RAIL
CLASS-B
BUFFERWITH DC
LEVEL-SHIFTING
CURRENT
MIRROR AND
DISTRIBUTED
MILLER
COMPENSATION
FOR LCD
COLUMN
DRIVERS
A rail-to-rail
class-B buffer
with a dc
level-shifting
current mirror
and the
proposed
distributed
Miller
compensation
is presented
for liquid
crystal display
By using a dc
level-shifting
current
mirror, the
rail-to-rail
input
stage directly
turns on/off
the rail-to-rail
push-pull
output stage
without extra
comparators.
It results in a
low-power
rail-to-rail
class-B
buffer.
2 2010
A NEW COMPACT
LOW-POWER
HIGH-SPEED
RAIL-TO-RAIL
CLASS-B BUFFER
FOR LCD
Proposes a
two-stage
class-B buffer,
which
includes an
The proposed
output buffer
can
obtain fast
driving
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APPLICATIONS
input rail-to-
rail
differential
amplifier
embodying the
current
comparators
capabilities
with a limited
quiescent
current
dissipation
by exploiting
two current
comparators.
3 1999 A CLASS-B
OUTPUT
BUFFER FOR
FLAT-PANEL-
DISPLAY
COLUMN
DRIVER
Presents a low
static power,
large output
swing, and
wide operating
voltage range
class-B output
buffer
amplifier for
driving the
large column
line
capacitance in
flat-panel
display.

A comparator
is used in the
negative
feedback path
to eliminate
quiescent
current in the
output stage.
4 2004 A HIGH-SPEED
DRIVING
SCHEME AND
COMPACT
It uses
one
differential
amplifier, two
The zero
compensation
technique is
used for the
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HIGH-SPEED
LOW-POWER
RAIL-TO-RAIL
CLASS-B
BUFFER
AMPLIFIER
FOR LCD
APPLICATIONS

output driving
stages and the
compensation
resistor
stability but
the slew rate
and the
settling time
are improved
by the second
output stage.
5 2009 A RAIL-TO-
RAIL UNITY
GAIN BUFFER
AMPLIFIER
FOR LOW-
COST HIGH
RESOLUTION
TFT LCD
PANELS
A structural
rail-to-rail
high voltage
CMOS buffer
amplifier for
driving
gamma
correction
reference
voltage of
TFT LCD
panel is
presented.
A class AB
output stage
with
common-
source
transistors is
used to
achieve rail-
to-rail output.
loss exists
6 2003 LOW POWER
HIGH-SPEED
CLASS AB
BUFFER
AMPLIFIER
FOR LCD
To improve
the speed of
the buffer
amplifier, a
new slew-
enhancement
The proposed
Class AB
buffer
amplifier
improves the
transient
D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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APPLICATIONS technique
without
consuming
any static
current is
proposed.


response
without
consuming
any
additional
static current
programs
7 2010 A
SUBTHRESHOL
D TO ABOVE-
THRESHOLD
LEVEL
SHIFTER
COMPRISING A
WILSON
CURRENT
MIRROR
A novel level
shifter circuit
that is capable
of converting
subthreshold
to above-
threshold
signal is
proposed.
The circuit
does not have
a static
current path
between the
supply rails
and therefore
offers a
reduced static
power
dissipation.







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CHAPTER 3
PROJECT DESCRIPTION

OBJECTIVE:
The aim of the project is to a design rail-to-rail class-B buffer with a dc level-shifting
current mirror for liquid crystal display (LCD) column drivers with low power dissipation
and rail to rail swing.

MOTIVATION:
For high-end colour panels in portable applications, a lot of buffers are needed.
The requirements of the buffers for high-quality displays are low power dissipation,
large driving capability, small area, and large output swing.
Class b buffers have low static power, large output swing, large driving capability and
wide operating voltage range.








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LCD DISPLAY:
SYSTEM LEVEL BLOCK DIAGRAM:

Fig.1 Block diagram of LCD system
Liquid Crystal Displays (LCDs) are expected to be the dominant technology for flat panel
televisions. Television applications use much larger panels than those for computer monitors,
and the colour must be more accurate.
Computer monitors use 6 or 8 bits per colour; television panels require 10 bits per colour. To
maintain colour purity, the system also needs to compensate for temperature, ambient
lighting, and variations in panel manufacturing.
Fig.1 is a block diagram of an LCD system. A horizontal line of pixel data from the video
processor is retimed by the timing controller and distributed to the column drivers. The
column drivers are essentially 420-output digital-to-analog converters (DACs). The timing
controller also clocks the row drivers to scan the image from the top to the bottom of the
panel. The system also contains voltage references for the column drivers, power supply
components, and the LCD back plane driver.
D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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Generally, a liquid crystal driving (LCD) system is composed of column drivers, row
drivers, a timing controller, and a reference source.
A column driver includes shift registers, input registers, data latches, level shifters,
Digital-to-Analog Converters (DACs), and output buffers.
Among these components, the DACs occupy the largest area. For different display
panels, the output buffer must meet various requirements in the column drivers. For large-
size display panels, the buffers must drive a large column line capacitance.
For high-end colour panels in portable applications, a lot of buffers are needed. The
size and power dissipation of these buffers must be minimized to save the die area and battery
power. For the panels with higher gray levels, the buffers should offer a rail-to-rail
input/output operation.
In summary, the requirements of the buffers for high-quality displays are low power
dissipation, large driving capability, small area, and large output swing.














D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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LCD COLUMN DRIVER:

Fig.2 LCD column driver

Fig.2 shows the conventional column driver architecture. The column driver supplies
high analog voltages to the LCD panel. To reduce power consumption, the digital circuit uses
a low voltage power supply.
Digital display data is fed to the RGB inputs and sampled into the input registers. A
wide data latch presents one row of serial input pixel data to the level shifters inputs. The
level shifters then boost the digital signals to higher levels. The DAC of each channel outputs
a voltage level corresponding to a digital sub-pixel code. The output buffers drive the highly
capacitive data lines of the LCD panel. For a dot inversion operation, the DACs offer
voltages with positive and negative polarities for the same digital input code.

D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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Fig. 3 The layout of column driver.
Figure 3 depicts the layout of a conventional column driver. One resistor string is put
in the middle of the chip to supply the reference voltages to all channels. Each channel needs
a decoder to route the reference voltage, corresponding to the digital input code, to the
corresponding output buffer. Since several hundreds of channels are built into a single chip,
the die area of the routing lines connecting the resistor string and the decoders is very large.
For example, a 10-bit column driver IC requires 2048 metal lines. Hence, these metal
lines and the decoders occupy a very large percentage of the column driver ICs area,
especially for high colour depth displays.
To drive the data lines of the LCD panel, each channel needs an output buffer. The
output buffers, which are usually made of operational amplifiers, drive highly capacitive data
lines.






D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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CLASS B BUFFER FOR LCD COLUMN DRIVER:
BLOCK DIAGRAM OF CLASS B BUFFER:

Fig. 4 Rail-to-Rail Class-B Buffer with DC Level-Shifting Current Mirror

A simple class B buffer with DC level-shifting current mirror block diagram is
shown in Fig. 4. Class B buffers have low static power, large output swing and wide
operating voltage range.
The input stage consists of biasing circuit, differential amplifier and a dc level
shifting current mirror. The rail to rail output stage consists of a charging and discharging
transistors.
The biasing circuit provides the bias voltage to the differential amplifier in the input
stage. The differential amplifier it consists of a biasing circuit, two complementary input
pairs and two constant current sources.
In order to reduce the quiescent current, all the transistors of the input stage adopt the
large channel length and small aspect ratios.
The large line capacitance is modelled as a load capacitor to which the output is
given. The output capacitance value ranges from 10 to 1200 pF.

D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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CIRCUIT DIAGRAM:

Fig. 5 Circuit diagram of Rail-to-Rail Class-B Buffer with DC Level-Shifting Current Mirror

The transistors operate in the saturation region and the device sizes of Mp4, Mn4,
Mp6 and Mn6 are identical with those of Mp5, Mn5, Mp7 and Mn7 respectively. In Fig. 5,
Mp3 and Mn3 have the currents equal to mIB, where IB is the current in the biasing circuit.
When the output voltage is equal to the input voltage, the currents of Mp1, Mp2, Mn1 and
Mn2 is equal to mIB/2.
The transistors Mp1, Mp2, Mn4, Mn5 and Mn1, Mn2, Mp4, Mp5 constitute the
folded cascade differential amplifier. The transistors Mp6, Mp7, Mn6 and Mn7 form the dc
level shifting stage.
The output stage is a rail-to-rail output stage, which consists of a charging transistor
(Mp8) and a discharging transistor (Mn8). In order to reduce the quiescent current, all the
transistors of the input stage adopt the large channel length and small aspect ratios. It also
increases the output impedance and decreases the current mismatch. Since this rail-to-rail
folded-cascoded differential amplifier has a low bias current, the channel-length modulation
effect is neglected in the following discussions.



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The drain currents ID4 and ID6 are given by



Since MP6 andMN6 are biased by the drain voltages of the diode-connected transistors
MN4 and MP4, respectively, the voltages VSG_MP6 and VGS_MN6 are derived as

In Fig. 2, the drain current of two diode-connected transistors MN7 and MP7 is given
by


Assume ID6=ID7, the voltages VSG_MP7 and VGS_MN7 are given by

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By (3), (5) and (6), the following equality is given as

Assume that the transistors MP6 and MN6 operate at the boundary between saturation
and triode regions, i.e.,

By using (5) and (9), the voltages VSD_MP5 and VDS_MN5 are derived as

From (10), both the transistors MP5 and MN5 will also operate at the boundary between
saturation and triode regions. By utilizing this dc level-shifting current mirror, the voltages
VSD_MP5 and VDS_MN5 are lowered. Since VSD_MP5= VSG_MP8 and VDS_MN5=VGS_MN8, if
VSD_MP5 < Vtp and VDS_MN5 < Vtn, the output stage, MP8 and MN8, will be turned off in the
steady state. A dc level-shifting current mirror is used to achieve a class-B operation without
extra comparators.
By (1), (2), and (7), the class-B buffer with a dc level-shifting current mirror is shown
in Fig. 5. The output stage is a rail-to-rail output stage, which consists of a charging transistor
MP8 and a discharging transistor MN8. The input stage is a rail-to-rail folded-cascoded
differential amplifier, and it consists of a biasing circuit (MB1MB4), two complementary
input pairs (MP1 MP2 and MN1MN2), two constant current sources (MP3 and MN3), and a dc
level-shifting current mirror (MP4MP5, MN4MN5, MP6MP7, and MN6MN7). In order to
reduce the quiescent current, all the transistors of the input stage adopt the large channel
length and small aspect ratios. It also increases the output impedance and decreases the
current mismatch.
D De es si ig gn n o of f a a R Ra ai il l- -t to o- -R Ra ai il l C Cl la as ss s- -B B B Bu uf ff fe er r w wi it th h D DC C L Le ev ve el l- -S Sh hi if ft ti in ng g C Cu ur rr re en nt t M Mi ir rr ro or r f fo or r
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The following equality is obtained as


From (11), following two equalities are derived as


From (12)(13), when VDD increases, ID6 increases. The quiescent currents of the self-
biased class-B buffer are dependent on the power supply. To work under a larger supply
voltage, the channel lengths of MP4, MN4, MP6, and MN6 must be enlarged to have a low
quiescent current.


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CHAPTER 4
SPECIFIC REQUIREMENTS

SOFTWARE REQUIREMENTS:
Cadence virtuoso.
Cadence spectre.

The software which are used in project are noted above and the respective
tools are used for

CADENCE VIRTUOSO: It is used as circuit simulator.
CADENCE SPECTRE: It is used to post layout simulation.













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CHAPTER 5
PROJECT PLAN
Module Description Result Output Start Date End Date

Finalizing
the project
Done

10th sep 2012 18th sep 2012
PHASE
1
Literature
Survey
Done
Study of LCD,
Column drivers,
Different techniques
for column driver.
18th sep 2012 1 nov 2012
study and
choosing the
proper type
of buffer for
LCD
column
driver for
low power
consumption
Done
Class B buffer is
chosen
1st oct 2012 15th oct 2012

study and
choosing the
proper level
shifter for
low power
consumption
Done
Level shifter
Comprising a
Wilson Current
Mirror is chosen
6th oct 2012 10th oct 2012
study of
other low
power
technique
which can
be used.
In
progress
other methods which
can be used to lower
the power
12th oct 2012
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Phase I
report
Done

13 nov 2012 16 nov 2012
PHASE
2
Studying of
tools.
In
progress
10th dec 12 20th dec 12
Designing
the Level
shifter block
20th dec 12 20th jan 13

Designing
the
differential
amplifier

20th jan 13 1st feb 13

Designing
bias circuit
and rail to
rail output
block

2nd feb 13 26th feb 13
PHASE
3
integration
of all the
blocks
1st march 13 14th march 13

verifying
and
comparing
with the
existing
models


14th march 13 1st april 13
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making the
report
2nd april 13 28th april 13
submitting
report.
29th april 13













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REFERENCES
[1] P. C. Yu and J. C. Wu, A class-b output buffer for flat-panel-display column driver,
IEEE J. Solid-State Circuits, vol. 34, pp. 116119, Jan. 1999.

[2]D. Marano, G. Plumbo, and S. Pennisi, A new compact low-power high-speed rail-to-rail
class-b buffer for LCD applications, IEEE J. Display Technol., vol. 6, no. 5, pp. 184190,
May 2010.

[3]C. W. Lu, A rail-to-rail class-ab amplifier with an offset cancellation for LCD drivers,
IEEE J. Solid-State Circuits, vol. 44, pp. 525537,Feb. 2009.

[4]M. C. Weng and J. C. Wu, A compact low-power rail-to-rail class-b buffer for LCD
column driver, IEICE Trans. Electron., vol. E85-C, no. 8, pp. 6591663, Aug. 2002.

[5]TFT-LCD source drivers NT39360, NT3982, and NT3994. Novatek. [Online]. Available:
http://www.novatek.com.tw/

[6]Chih-Wen Lu (2009). TFT-LCD Driver IC Design, New Developments in Liquid Crystals,
Georgiy V Tkachenko (Ed.), ISBN: 978-953-307-015-5, InTech, Available from:
http://www.intechopen.com/books/newdevelopments-in-liquid-crystals/tft-lcd-driver-ic-
design

[7] C. W. Lu, C. C. Shen, and W. C. Chen, An area-efficient fully R-DACbased TFT-LCD
column driver, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 25882601,
Oct. 2010

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