Solar Cells On Glass

Contact Resistance Study on
Polycrystalline Silicon Thin-Film

Solar Cells on Glass
by

Lei Shi

Masters Thesis
School of Photovoltaic and Renewable Energy Engineering
The University of New South Wales
Sydney, Australia

June 2008
i

Originality Statement

I hereby declare that this submission is my own work and to the best of my knowledge
it contains no materials previously published or written by another person, or substantial
proportions of material which have been accepted for the award of any other degree or
diploma at UNSW or any other educational institution, except where due acknowledge-
ment is made in the thesis. Any contribution made to the research by others, with whom
I have worked at UNSW or elsewhere, is explicitly acknowledged in the thesis. I also
declare that the intellectual content of this thesis is the product of my own work, except
to the extent that assistance from others in the project's design and conception or in
style, presentation and linguistic expression is acknowledged.

Lei Shi
Sydney, 18 December 2007
ii

In memory of my beloved grandfather,
fatherly concern for me whenever, and wherever.
iii

The fabrication of ohmic contacts is still more of an art than a science
E. H. Rhoderick and R. H. Williams, 1988
iv

Abstract

Thin-film solar cells are widely recognised to have the potential to compete with fossil
fuels in the electricity market due to their low cost per peak Watt. The Thin-Film Group
at the University of New South Wales (UNSW) is engaged in developing polycrystalline
silicon (poly-Si) thin-film solar cells on glass using e-beam evaporation technology. We
believe our solar cells have the potential of significantly lowering the manufacturing
cost compared to conventional, PECVD-fabricated thin-film solar cells. After years of
materials research, the focus of the Groups work is now moving to the metallisation of
evaporated solar cells. Minimising various kinds of losses is the main challenge of the
cell metallisation procedure, within which the contact resistance is always a big issue.

In this thesis, the contact resistance of aluminium contacts on poly-Si thin-film solar
cells on glass is investigated. To the best of the authors knowledge, this is the first ever
contact resistance investigation of Al contacts on evaporated poly-Si material for
photovoltaic applications.

Various transmission line models (TLM) are employed to measure the contact resistance.
An improved TLM model is developed to increase the measurement precision and,
simultaneously, to simplify the TLM pattern fabrication process. In order to
accommodate the particular requirements of poly-Si coated glass substrates, a TLM
pattern fabrication process using photolithography is established. Furthermore, a Kelvin
sense tester is set up to ensure an accurate measurement of the contact resistance. After
establishment of the TLM technique at UNSW, it is successfully tested on
singlecrystalline silicon wafer samples. The thermal annealing process of the contacts is
also optimised. Then, the general behaviour of Al contacts on uniformly doped poly-Si
films (i.e., no p-n junction) is investigated using the verified TLM technique. The
long-term stability of the contacts is also studied. This is followed by an investigation of
the contact resistance of the back surface field and emitter layers of different types of
poly-Si thin-film solar cells. Finally, a novel contact resistance measurement model is
proposed that is believed to be able to overcome the measurement bottleneck of the
transmission line models.
v

Acknowledgements

This postgraduate work would not have been successful without the assistance and
support from some people.

First of all I would like to extend my gratitude to my supervisor, Prof. Armin Aberle, for
his academic and financial support. He is the person who guided me to the great family
of solar energy enthusiasts and consequently changed my professional career. The two
years of research under your supervision were tough, but rewarding. Not only my
knowledge and skills but also my views on life and values improved dramatically
during this period. Thanks Armin, you gave me a turning point of my life.

A huge Thank you! goes to Dr. Tim Walsh who acted as my co-supervisor and
mentor during his PhD candidature in 2005 and 2006. Armin gave me an opportunity to
do research, and Tim trained me to become a qualified researcher. Tim, I wish you a
successful career in China and I believe our friendship will last for good.

I would like to express my appreciation to Daniel Inns who offered several high-quality
samples, which led to a breakthrough of my research. My appreciation also goes to
Oliver Kunz for the valuable help and discussion of my work, as well as proof reading
parts of this thesis. It has been a fantastic experience of working with him. I thank our
ingenious undergraduate PV student, Dawei (David) Di, for assisting me in some lab
work. I am honoured to know you and work with you, David.

Bernhard Vogl is my dear office mate. We are always the last guys to leave the office
everyday and it is always a pleasure to have someone staying up together for work and
for helpful and interesting talk of semiconductor, research, life, and other things. Lots of
thanks go to my other colleagues in the PV Centre: Dr. Nicholas Shaw and Mark Silver
for offering me a part-time job; Nancy Sharopeam for kind encouragements when I was
in low spirits; Ivan Perez-Wurfl for photomask design; The list is almost endless. All
in all, it was a dreamlike experience to work with these first-class people in this
first-class institute.
vi

Finally and most importantly, a special thanks to my family for their love and constant
self-giving support.
vii

Contents

Originality Statement.......................................................................................................i
Abstract...........................................................................................................................iv
Acknowledgements.......................................................................................................... v
1 Introduction
1.1 Thin-Film Solar Cells........................................................................................ 1
1.2 Poly-Si Thin-Film Solar Cells on Glass at UNSW........................................... 4
1.2.1 EVA Solar Cell .............................................................................................. 5
1.2.2 ALICIA Solar Cell ........................................................................................ 5
1.2.3 ALICE Solar Cell.......................................................................................... 6
1.2.4 Key Processes and Glass............................................................................... 7
1.3 Aims of this Thesis............................................................................................ 9
2 Contact resistance and the transmission line models
2.1 Metal-semiconductor contacts (MS contacts)................................................. 11
2.2 Ohmic contacts and contact resistance............................................................ 12
2.3 Metal typically used........................................................................................ 15
2.4 Lumped series resistance of solar cells ........................................................... 16
2.5 The transmission line models.......................................................................... 18
2.5.1 Variable gap transmission line model (TLM) ............................................. 19
2.5.2 Improved variable gap TLM....................................................................... 24
2.5.3 The contact end resistance measurement .................................................... 25
2.5.4 Ladder network transmission line models................................................... 27
2.5.5 Circular transmission line model (CTLM).................................................. 29
2.5.6 Practical requirements of the transmission line models.............................. 32
3 Sample fabrication and characterisation
3.1 Sample cleaning .............................................................................................. 33
3.2 Aluminium evaporation .................................................................................. 34
3.3 Photolithography and pattern fabrication........................................................ 34
3.3.1 Photolithography procedures ...................................................................... 34
3.3.2 Photomask design ....................................................................................... 39
3.3.3 Pattern fabrication....................................................................................... 41
3.3.4 Process optimisation and the results ........................................................... 45
3.4 Plasma etching ................................................................................................ 48
viii

3.5 Wet-chemical etching with coloured HF......................................................... 49
3.6 Sheet resistance profiling................................................................................ 51
3.7 Spectroscopic measurements .......................................................................... 54
3.8 Dark I-V measurements .................................................................................. 55
3.8.1 Four-point probe tester................................................................................ 55
3.8.2 Curve tracer................................................................................................. 56
3.8.3 Kelvin sense measurement setup ................................................................ 56
4 Contact resistance results on sc-Si wafer samples
4.1 Motivation....................................................................................................... 60
4.2 Sample preparation ......................................................................................... 60
4.3 Results............................................................................................................. 61
4.3.1 Boron-diffused sc-Si surfaces ..................................................................... 61
4.3.2 Phosphorus-diffused sc-Si surfaces ............................................................ 64
4.3.3 The influence of baking time and temperature ........................................... 65
4.4 Discussion and conclusions ............................................................................ 67
5 Contact resistance results on uniformly doped poly-Si films on glass
5.1 Motivation....................................................................................................... 70
5.2 Sample preparation ......................................................................................... 70
5.3 Results............................................................................................................. 71
5.3.1 Boron-doped Si films.................................................................................. 73
5.3.2 Phosphorus-doped Si films with and without SiO
x
interlayer .................... 78
5.4 Discussion....................................................................................................... 85
5.5 Conclusions..................................................................................................... 92
6 Contact resistance results on poly-Si thin-film diodes on glass
6.1 Motivation....................................................................................................... 94
6.2 Contacts to the back surface field layer of PLASMA cells............................. 94
6.2.1 Sample preparation ..................................................................................... 94
6.2.2 Results......................................................................................................... 96
6.3 Contacts to the back surface field layer of EVA cells ................................... 103
6.4 Contacts to the back surface field layer of ALICIA cells ............................. 106
6.5 Contacts to the emitter layer of PLASMA cells............................................ 111
6.6 Contacts to the emitter layer of EVA cells .................................................... 116
6.7 Conclusions................................................................................................... 119
7 A novel contact resistance measurement model
7.1 Motivation..................................................................................................... 120
ix

7.2 Fabrication and underlying theory ................................................................ 121
7.2.1 Structure .................................................................................................... 121
7.2.2 Suggested fabrication procedure............................................................... 122
7.2.3 Theory ....................................................................................................... 123
7.3 Discussion and conclusions .......................................................................... 125
8 Summary and conclusions
8.1 Summary and conclusions............................................................................. 126
8.2 Possible future work...................................................................................... 128
List of symbols............................................................................................................. 130
List of references ......................................................................................................... 133
List of original contributions ..................................................................................... 139
List of publications...................................................................................................... 141
1 Introduction
1

1 Introduction

1.1 Thin-Film Solar Cells

The world is becoming increasingly aware of the significant problems associated with
global warming, such as more frequent and more intense heat waves, cold waves, floods,
droughts and storms. A major contribution to global warming comes from greenhouse
gas emissions such as carbon dioxide (CO
2
), 45% of which are from electricity
production [IPCC 2006]. Nuclear energy is powerful, but it is also well known for its
risks and hence does not seem to be suitable for worldwide use. As an alternative,
people have been developing various kinds of carbon free, sustainable and renewable
energies such as wind power, hydropower, biomass, geothermal, solar thermal and
photovoltaic energy. Although most of these energies are still more expensive than fossil
fuel, it is deemed that they will make a large contribution to the worldwide energy
supply in the medium to long term, reducing the dependence on fossil fuels.

While not being the cheapest renewable technology at present, photovoltaic (PV) energy
has a number of advantages such as its excellent scalability, noiseless and low-
maintenance operation, and temporal peak load matching (especially in countries with
heavy use of air conditioners).

The currently prevailing commercial PV technology is based on approximately 200 m
thick single- or multicrystalline silicon (c-Si) wafers. However, practically, only a small
fraction of the 200 m thick silicon wafers is used to convert the sunlight into electricity,
representing a significant waste of expensive silicon material. Moreover, the rapid
growth of the PV industry in the last decade has led to a shortage of silicon wafer
feedstock material, which currently limits the growth of the PV industry as well as the
popularisation of solar energy. The oil price has risen sharply in recent years and now
exceeds US$ 80 per barrel. Somewhat ironically, however, the relative increase of the
price of silicon feedstock has been even higher in recent years, driven by the surging
1 Introduction
2

demand from the PV sector. Unfortunately, being limited by the sawing loss and other
technical problems, it is not possible to simply cut the silicon ingots into thinner and
thinner wafers. As a consequence, a less material intensive technology - a thin-film
technology - seems necessary for a large-scale application of PV.

Thin-film solar cells, which are sometimes referred to as second-generation solar cells,
have two main advantages over conventional silicon wafer-based solar cells. Firstly, the
amount of raw materials used in thin-film cells is significantly reduced. As mentioned
above, most energy-rich solar photons are absorbed within a few microns from the
illuminated silicon surface. Thus, an efficient c-Si solar cell can be made from less than
10 m thick films. By adding a light-trapping scheme that increases the optical
pathlength of the photons through the semiconductor (resulting in a higher probability
of being absorbed), the required material thickness can be further reduced to less than 3
m. This represents a massive reduction of the Si consumption of over 99% compared
to conventional 200 m thick wafers (which have a wafering-related kerf loss of about
200 m). Therefore, moving towards thin-film PV cell production will allow a much
greater increase in manufacturing capacity compared to installing new assembly lines
for Si wafer cells.

The second advantage is a streamlined production process due to the fact that thin-film
cells can be deposited onto large-area superstrates (such as glass). They can be scribed
into many long subcells and these can be interconnected using various techniques. This
provides more freedom with regards to shape, size, and output voltage of the module,
while at the same time minimises the costs associated with cell interconnection. In first
generation (wafer-based) solar cell technology, encapsulation by a strong front-side
glass cover is usually indispensable to protect the cells from the environment (humidity,
dust, hail, wind), while this step can be omitted in thin-film fabrication process.

To sum up, the above two factors result in one single advantage: greatly reduced
manufacturing cost ($/Watt) of PV modules.

Various materials are currently used for thin-film solar cells. Some of them are briefly
reviewed.
1 Introduction
3

Amorphous silicon (a-Si:H) is the first commercialised thin-film solar cell technology.
The silicon film is deposited at low temperature (200-300C) using plasma-enhanced
chemical vapor deposition (PECVD). Amorphous Si PV modules are cheap but they
have low stabilised efficiency of about 6% for large areas. One reason behind this low
stable efficiency is the light-induced degradation effect (Staebler-Wronski effect)
[Staebler & Wronski 1977]. Researchers have developed an amorphous/microcrystalline
silicon (a-Si:H/c-Si) tandem structure [Keppner 1999] to obtain higher stable
efficiency. PV modules based on this tandem structure now have about 8-10% stable
efficiency [Tawada 2003] Both these materials are deposited on large areas by
PECVD and require a full-area Transparent Conductive Oxide (TCO) contact on the
illuminated surface for lateral current transport due to their high sheet resistance.

A compound semiconductor for PV applications is cadmium telluride (CdTe) which has
around 7-9% commercial PV efficiency [First Solar 2007]. CdTe uses toxic materials
and may harm the environment, which is a limiting factor for worldwide use.

Another remarkable compound semiconductor for thin-film solar cells is copper indium
gallium diselenide (CIGS) and its related materials (such as CIS). Although 19.5%
efficiency has been obtained for small laboratory cells, its potential for mass production
is doubted due to the use of a very rare element, indium.

There is increasing interest in polycrystalline silicon (pc-Si) thin-film material.
Compared to alternative materials, there are several advantages of using polycrystalline
silicon: silicon is comparatively cheap, non-toxic, abundant and widely used in the
semiconductor industry. Poly-Si PV cells do not degrade and TCO is not necessary for
contacting. The latter factor makes local contact schemes possible, which significantly
enlarges the scope for the methods of metallising and interconnecting the cells. CSG
Solar (formerly Pacific Solar), a spin-off company of UNSW, has developed and
commercialized a poly-Si on glass thin-film PV technology that is based on solid phase
crystallisation (SPC) of a PECVD-deposited a-Si precursor diode. This technology
(CSG) uses borosilicate glass superstrates and achieves mini-module efficiencies of
10.4% [Keevers 2007].
1 Introduction
4
1.2 Poly-Si Thin-Film Solar Cells on Glass at UNSW
At the University of New South Wales (UNSW), research is underway aiming at the
realisation of efficient, low-cost poly-Si thin-film solar cells on glass. The scientific
innovation of the work lies in the use of novel methods for glass texturing, Si diode
formation, and solar cell metallisation and interconnection. Si deposition is performed
by PECVD (industry standard, but low deposition rate) and e-beam evaporation.
Vacuum evaporation has a number of advantages over the PECVD technique such as
high deposition rate (up to 1 m/min), good Si source material usage, and avoidance of
toxic gases. Six different thin-film solar cell structures are investigated in parallel. Their
fabrication sequence is illustrated in Figure 1.1.

Figure 1.1: Process sequence of the six
poly-Si on glass thin-film solar cells
presently under development at UNSW.
All cells are designed for the super-
strate configuration, i.e., the sunlight
enters the cells through the glass
[Aberle 2006a].

Three of these six thin-film solar cells - EVA, ALICE and ALICIA - have been
investigated in the course of this thesis and hence their fabrication sequence is explained
in more detail in the following Sections. EVA and ALICIA are fabricated using a
non-UHV e-beam evaporation technology, whereas ALICE can be fabricated by e-beam
evaporation or PECVD.

1 Introduction
5

1.2.1 EVA Solar Cell

EVA stands for solid phase crystallisation of EVAporated Si. With the exception of
the Si deposition process, EVA cells are similar to the PLASMA cells shown in Figure
1.1. The EVA cell structure is glass/SiN/n
+
/p
-
(or n
-
)/p
+
. The a-Si is evaporated at low
temperature (~200C) in a non-UHV environment (deposition pressure ~10
-7
Torr, no
hydrogen added) and then crystallised ex-situ by atmospheric-pressure SPC in a
N
2
-purged tube furnace at 600C for 24 h [Aberle 2006a]. The grain size is about 1-2
m. Table 1.1 lists the typical design features of EVA solar cells.

Table 1.1: Typical design parameters of EVA cells [Aberle 2006a].

Parameter Details
Glass 3 mm (planar or textured, borosilicate)
AR coating SiN (~75 nm, n ~2.0)
Emitter n
+
(~150 nm, up to 110
20
cm
-3
P, ~200 /)
Base p (~1500 nm, ~110
17
cm
-3
B)
BSF p
+
(~150 nm, up to 510
19
cm
-3
B, ~400 /)
RTA 10 s @ 1000C or 4 min @ 900C
Hydrogenation ~15 min @ about 600C, remote plasma
Metal Al (500 nm, front & rear)

1.2.2 ALICIA Solar Cell

ALICIA stands for ALuminium-Induced Crystallisation Ion-Assisted deposition
[Aberle 2005]. The idea is to epitaxially grow the crystalline absorber layer on a
hydrogen-terminated seed layer made on glass by Aluminium Induced Crystallisation
(AIC). Because AIC seed layers have a large grain size of 10-20 m, it seems possible
that ALICIA cells have better crystal quality than EVA and PLASMA cells. The
epitaxial growth is via Ion-Assisted Deposition (IAD). This vacuum evaporation
method is capable of high-rate pc-Si growth at low temperatures of ~600C. From
sample heating to unloading, epitaxial growth of the Si cell typically takes less than 30
min. Owing to the contradictory demand of the temperature between H-terminated seed
layer surface and good epitaxial growth, an elaborate heating procedure was developed
at UNSW [Inns 2005]. Figure 1.2 schematically shows an ALICIA solar cell.
1 Introduction
6

Figure 1.2: Schematic of an
ALICIA pc-Si thin-film solar cell
on glass. Grain size and layer
thickness are not to scale [Aberle
2005].

1.2.3 ALICE Solar Cell

ALICE stands for ALuminium-Induced Crystallisation solid-phase Epitaxy [Aberle
2006b]. The idea is to deposit the absorber onto an H-terminated AIC seed layer at very
low temperature (~200C) as amorphous material, and then to crystallise the amorphous
material in a thermal anneal at elevated temperature (570-600C). Due to the presence
of the seed layer, the crystallisation process is Solid Phase Epitaxy (SPE) rather than
SPC. The a-Si precursor diode can be deposited by either e-beam evaporation or
PECVD [Aberle 2006]. Table 1.2 summarizes the design features of p
+
nn
+
ALICIA
cells.

Table 1.2: Typical parameters of p
+
nn
+
ALICIA cells [Aberle 2006b].

Parameter Details
AR coating SiN (~75 nm, n ~2.0)
Emitter p
+
(~150 nm, ~110
19
cm
-3
Al+B, ~1000 /)
Base n (~1500 nm, ~510
16
cm
-3
P)
BSF n
+
(~100 nm, ~110
19
cm
-3
P, ~1000 /)
RTA 10s @ 1000C or 4 min @ 900C
Hydrogenation ~15 min @ about 620C, remote plasma
Metal Al (500 nm, front & rear)

1 Introduction
7

1.2.4 Key Processes and Glass

The key processes and the glass used for the fabrication of the above three solar cells
are summarised below:
z Glass
All the solar cells investigated at UNSW have the glass superstrate configuration. Glass
is a standard component of todays PV modules. It has lots of advantages, but the
disadvantage is the limited thermal stability. To minimise this drawback, Borofloat33
glass is used due to good thermal stability at around 600C.
z Glass texture
A novel glass texturing method has been developed at UNSW, which is termed
Aluminium Induced Texture (AIT) [Chuangsuwanich 2004]. It creates a random array
of sub-micron sized dimples at the glass surface. The AIT process starts with the
deposition of a thin (~100 nm) aluminium film onto the glass, followed by thermal
annealing at about 600C for 30 minutes and subsequent wet-chemical etching of the Al
and the reaction products. The AIT process is performed on the silicon-facing surface of
the glass.
z SiN
After texturing, a silicon nitride layer (typical thickness 75 nm) is deposited onto the
silicon-facing side of the glass via either PECVD or RF sputtering. This SiN film acts
both as an antireflection coating in the final device and a barrier layer against
contaminants from the glass during silicon material manufacturing.
z Seed Layer
A crucial component of ALICIA and ALICE cells is a large-grained seed layer made on
glass by the AIC (Aluminium-Induced Crystallisation) process of a-Si. This technology
was pioneered at UNSW in 1998 [Nast 1998] and is a prerequisite for good SPE
material quality. It is realised by evaporation of an Al film onto an intrinsic a-Si layer
(formed by PECVD or sputtering), followed by annealing at around 500C for 12 hours
in an atmospheric-pressure tube furnace and removal of the excess Al and Si.
Apart from the AIC method, a seed layer can also be formed by SPC of a
heavily-doped a-Si layer at about 600C for 24 h. The heavily doped a-Si layer (n
+
or p
+
)
1 Introduction
8

is formed by e-beam evaporation or PECVD. The solar cells grown on SPC seed layers
are termed SOPHE (crystallised via SPE) or SOPHIA (epitaxial growth via IAD), see
Figure 1.1. Note that in the case of ALICIA and SOPHIA, the base layer and the BSF
layer of the cells are immediately grown as crystalline silicon (epitaxial Si growth),
whereas in the case of ALICE and SOPHE, these layers are deposited in amorphous
form and then crystallised in a subsequent furnace anneal.
z Post-deposition Treatments
After silicon material deposition, all types of solar cells are treated by RTA and
hydrogenation processes. The RTA process uses a lamp-based system that rapidly heats
the samples to the desired temperature (900-1000C), maintains the peak temperature
for a certain time (in the range of 1 s to 8 min), and then lowers the sample temperature
in a controlled manner to values below 200C. Hydrogenation is performed at a sample
temperature in the range of 500-620C, using a remote plasma tool (modified LPCVD
machine). The RTA process reduces the density of point defects and activates the
dopants, while hydrogenation helps to passivate many of the remaining defects (grain
boundary defects, extended defects, point defects). The open-circuit voltage approxi-
mately doubles due to hydrogenation treatment [Terry 2006].
z Metallisation
All thin-film poly-Si solar cells at UNSW are metallised with aluminium only. A novel
metallisation method for poly-Si thin-film cells on glass has been developed at UNSW.
It is based on two interdigitated comb-like grid structures (see Figure 1.3) and is
referred to as the SAMPL method (Self-Aligned Maskless PhotoLithography) [Walsh
2005]. A comb-like aluminium electrode is formed on the rear (air-side/BSF) surface of
the cell using Al evaporation and photolithographic structuring. Using the rear metal
(air-side electrode) as a mask, the Si film which is not covered by Al is removed by
plasma etching (PE). PE is not an isotropic etching process and hence a sloped Si side
wall is formed along each edge of the etched region. Next, positive photoresist is
applied to the rear surface. After pre-bake, it is then exposed to collimated UV light,
incident from the substrate side of the device, such that the remaining silicon film acts
as a self-aligned photomask, and only the photoresist on the plasma etched region is
exposed. After development and post bake, a layer of Al (~500 nm) is deposited over
the rear surface of the device and then a photoresist lift-off process is performed,
1 Introduction
9
leaving Al only in the etched region, acting as the glass-side electrode. Figure 1.4 shows
a FIB image of a metallised PLASMA solar cell.

Air side Al contact
Glass side Al contact
Si side wall

Figure 1.3: Schematic of an interdigi-
tated poly-Si thin-film solar cell on a
glass [Aberle 2006b].
Figure 1.4: Cross-sectional FIB image
of the BSF and emitter contacts of a
metallised PLASMA solar cell.

Most of the effort at UNSW over the past several years has been devoted to improving
the open-circuit voltage of the cells. However, the focus of the work is now moving to
the metallisation of the solar cells. Minimising various kinds of losses is the main
challenge of the cell metallisation procedure, within which the contact resistance is
always a big issue.

1.3 Aims of this Thesis

The aims of this thesis are to measure and optimise the contact resistance of the front
and rear contacts of EVA, ALICIA and PLASMA cells. To the best of the authors
knowledge, the present thesis represents the first ever contact resistance characterisation
study performed on poly-Si PV materials made from evaporated a-Si.

The first task of the thesis is the establishment of a reliable and accurate measurement
technique for the contact resistance of metal/silicon contacts.

1 Introduction
10

The established method is then applied to heavily doped SPC seed layers so as to
investigate the general behaviour of Al contacts to evaporated poly-Si. Then it follows
the study of the contact resistance on the back surface field (BSF) layer of completed
solar cells. The next task then is the investigation of emitter contacts. The effect of
thermal annealing (baking) of the contacts and other surface treatments are also
investigated on both SPC seed layers and completed diodes. For these tasks, several
different test structures are tried to gain a better understanding of the strengths and
weaknesses of each structure. Afterwards, a new measurement structure is to be
proposed which is able to overcome the weaknesses of the other tested structures.

Finally, process recommendations are to be established for the realisation of ohmic
contacts with low contact resistance on doped poly-Si materials.
11

2 Contact resistance and the
transmission line models

Ohmic contacts are indispensable for metallising photovoltaic devices including poly-Si
thin-film solar cells. The contact resistance is used to quantitatively evaluate the ohmic
property, while the transmission line models are used to measure the contact resistance.
The aim of this Chapter is to lay out the relevant theories to better facilitate
understanding of the experimental results presented in the subsequent chapters. A
temperature of 300 K is assumed in all discussions if not stated otherwise. The silicon
refers to singlecrystalline silicon.

2.1 Metal-semiconductor contacts (MS contacts)

A highly conductive material (e.g. metal) is indispensable for extracting current from
the bulk of the semiconductor to external circuits without significant resistive losses.
When a metal and a semiconductor are brought into intimate contact, a potential barrier
arises which is well-known as the Schottky barrier [Sze 1969, Yu 1969, Rhoderick &
Williams 1988]. If the Fermi levels E
F
of the semiconductor and the metal differ, which
is usually the case, electrons flow from the material with larger E
F
to that with lower E
F
,
creating a space charge region. The means that the conduction band E
C
and the valence
band

E
V
of the semiconductor are bent at the interface of the contact. The electron
transfer process continues until a constant Fermi level has established itself across the
entire sample, and forms the built-in potential barrier. The entire process is analogous to
the formation of a one-sided abrupt junction (p
+
-n or n
+
-p). Both Schottky barrier and
built-in potential impede the transport of electrons and holes between the semiconductor
and the metal. Figure 2.1(a) and (b) illustrate the theoretical barrier formation of Al/n-Si
contacts. Due to the different Fermi levels (work functions), a depletion region is
formed after the two materials are brought into contact.
12

q
m

q
s

E
F

E
C

E
V

E
Fi

Aluminium n-type Silicon
Vacuum level

(a)

E
F

E
C

E
V

E
Fi

q
m

Vacuum level
q
s

q
Bn

q
bi

(b)

Figure 2.1: Band diagram of Al and n-type Si.
m
is the work function of Al.
s
is the
work function of Si. (a) Before contact formation. Note that q
m
> q
s
; (b) Band
diagram of the Al/n-Si contact structure. The Schottky barrier q
Bn
, the built-in
potential q
bi
and the Fermi level of intrinsic Si E
Fi
are also shown. [Sze 1969]

The band diagram in Figure 2.1(b) represents a rectifying contact, which is unwanted
for photovoltaic devices. Ohmic contacts are usually achieved via the quantum
mechanical effect of tunnelling.

2.2 Ohmic contacts and contact resistance

The width of the depletion region depends on the doping level of the semiconductor.
More precisely, it depends inversely on the square root of the doping concentration at
the surface. And the tunnelling probability increases exponentially with decreasing
deletion region width. In brief, in order to have an ohmic contact with low tunnelling
resistance, the surface doping density needs to be as high as possible. However, owing
to other restraining factors from device design such as poor blue response, the surface
doping level cannot be increased arbitrarily. Therefore, knowing the contact resistance
is important in terms of device design optimisation.

An ohmic contact is indispensable for most semiconductor devices. It is defined as a
metal-semiconductor contact that has a negligible junction resistance relative to the total
resistance of the semiconductor device. The contact resistance, also known as the
specific contact resistance or contact resistivity,
c
(cm
2
), is an important

13
figure-of-merit for evaluating the quality of ohmic contacts. It is a resistance value that
is normalised to the area. Mathematically it is defined as the reciprocal of the derivative
of the current density with respect to the voltage across the interface, at V = 0:

2.1
1
0
=
|
.
|
\
|
V
c
dV
dJ

J is the applied current density. More detailed expressions of
c
are given below.

Figure 2.2 depicts the three main current transport mechanisms of metal-silicon contacts.
When the doping density is low (< ~510
17
cm
-3
), the depletion region is too wide (>
400 ) to enable tunnelling. Therefore, only electrons with high energy have a chance
to overcome the barrier. The process is called thermionic emission (TE). The contact
resistance is heavily Schottky barrier height dependent. When the doping is extremely
high (> ~ 10
20
cm
-3
), the depletion region is narrow enough (< 40 ) for low-energy
electrons to tunnel through it rather than travelling over it. The contact resistance is
heavily dependent on the doping level. This process is called field emission (FE). High
doping concentration may also slightly lower the Schottky barrier height [Rhoderick &
Williams 1988]. At intermediate doping levels, both current transport mechanisms
occur simultaneously. This situation is referred to as thermionic-field emission (TFE).
In the TFE process, the electrons have an energy above the conduction band edge but
enter the metal through tunnelling rather than thermionic emission. The contact
resistance is determined by both the Schottky barrier height and the surface doping
density.

E
Fm

E
Fs

q
Bn

e
E
C

V
F

(a)

|
.
|
\
|
kT
B
c
|
exp (kT >> E
00
)

14

E
Fs

V
F

e
E
C

E
Fm

(b)

|
|
|
|
|
.
|
\
|
|
.
|
\
|
kT
E
N
D
B
c
00
coth
exp
|
(kT E
00
)

Ec
V
F

e
E
Fs

E
Fm

(c)

|
|
.
|
\
|
D
B
c
N
|
exp (kT << E
00
)

Figure 2.2: Band diagrams of MS contacts under forward bias, for an n-type
semiconductor: (a) thermionic emission, (b) thermionic-field emission, (c) field
emission. The functional dependence of the specific contact resistance for each
mechanism is also listed on the right-hand side, whereby u
B
is the barrier height for
the majority carriers in the semiconductor (i.e., u
B
= u
Bn
in the case shown here).
[Yu 1970].

Both TFE and FE are responsible for ohmic contacts. In UNSWs thin-film solar cells,
TFE is believed to be the dominant current transport mechanism. In Figure 2.2 (right),
E
00
is an important characteristic energy and related to the tunnelling probability. The
ratio kT/ E
00
is a measure of the relative importance of the thermionic process in relation
to the tunnelling process. E
00
is defined as [Yu 1970]:

2.2
c t
*
00
4
E
m
N qh
D
=

where q is the electronic charge, h is Plancks constant, N
D
is the donor concentration,
is the permittivity of the semiconductor, and m
*
is the effective mass of the tunnelling
electron which depends on the surface crystal orientations, doping type and doping
density.

Figure 2.3 depicts the theoretical contact resistance vs. doping concentration for a range
of Schottky barrier heights. For large barrier heights, the contact resistance drops
steeply with increasing doping. All curves converge for doping levels above 10
20
cm
-3

confirming that the barrier height becomes less important in the high doping region.

15

Figure 2.3: Numerically calculated specific contact resistance R
c
on (a) n-type
and (b) p-type <100> Si surface for various barrier heights (in eV) at room
temperature. The effective mass m* is a function of doping density. (After Kg &
Liu 1990)

2.3 Metal typically used

Aluminium is the most commonly used metal for forming electrodes in the IC industry
as well as the PV industry due to its low cost, high conductivity, good stability at room
temperature, etc. Moreover, it is especially suitable for forming ohmic contacts as it is a
good oxide absorber during thermal annealing of Al/Si contacts. One problem for
achieving ultra-low contact resistance (< 10
-6
cm
2
) is the elimination of the oxide film
that normally exists at Al/Si interfaces, even after an HF dip. When annealing Al/Si
contacts at moderate temperature (~ 100-300C), aluminium atoms react with silicon
oxides to enable fresh Al atoms to diffuse through the aluminium oxide and reach the
silicon interface to form intimate Al/Si contacts [Neamen 2003]. This process will be
further explained and discussed in Section 4.4.

All UNSWs thin-film solar cells on glass are metallised with aluminium only. The
metal sheet resistance is found to be around 0.1 / for a typical 500 nm thick Al layer

16
evaporated at a background pressure of around 10
-5
Torr.

2.4 Lumped series resistance of solar cells

The lumped series resistance, R
s
, is the figure-of-merit for evaluating the metallisation
quality. In the case of solar cells, R
s
depends on a number of parameters, including the
emitter sheet resistance, the bulk resistance, the metal finger/busbar resistance and the
metal/semiconductor contact resistances of the two electrodes. In conventional 1-Sun
solar cells, the power loss associated with the contact resistances of the front and rear
contacts is usually insignificant compared to other sources of power loss, especially
when the back metallisation is a full-area contact. However, contact resistance becomes
very important if a low surface doping level or a point-contact metallisation scheme is
applied. For a thin-film solar cell, light trapping is of particular importance, which
usually makes a full-area back contact unacceptable. Moreover, the emitters of the
thin-film solar cells developed by our group at UNSW are metallised laterally along the
exposed sidewalls (see Section 1.2.4). Due to the thinness of the emitter, the emitter
contact area is very small. Therefore, a contact resistance study is indispensable to
optimise the metallisation scheme of our thin-film cells.

Figure 2.4 plots the fractional power loss of a typical EVA cell due to the emitter contact
resistance against the metal finger width. The curves are generated using the equations
and parameters listed in Table 2.1. The bus bar and the air-side (BSF) contact resistance
are not accounted. The total fractional power loss is the sum of each power loss. By
taking the derivative of the sum expression to zero, the minimum power loss (y axis) is
found with respect to the varied metal finger width and contact resistance.

Table 2.1: The equations and parameters used to plot Figure 2.4. S is the distance
between the middle points of the neighbouring metal fingers (BSF or emitter). It is
optimised for each W
F
value in Figure 2.4 [Green 2006]..

Factional power loss due to
resistive BSF metal fingers
F mp
mp
sheetMB
W
S
V
J
R
2
rbf
3
1 . 1
p =
Current density and voltage at
max power point:
J
mp
= 15 mA/cm
2

17
Fractional power loss due to
resistive emitter metal
fingers
F mp
mp
sheetME
W
S
V
J
R
3
1 . 1
p
2
ref
=
shading by emitter fingers
S
W
F
=
sf
p
Factional power loss due to
contact resistance
F mp
mp
c
W
S
V
J
=
cf
p
lateral current flow in
resistive BSF layer
2
Bl
12
p S
V
J
R
mp
mp
sheetB
=
lateral current flow in
resistive emitter layer
2
El
12
p S
V
J
R
mp
mp
sheetE
=
V
mp
= 380 mV

Sheet resistance of metal
fingers:
For BSF, R
sheetMB
= 83 m/
For Emitter, R
sheetME
= 36 m/

Sheet resistance of BSF and
emitter layers:
For BSF, R
sheetB
= 800 /
For Emitter, R
sheetE
= 300 /

Specific contact resistance:
c
= varied

Metal finger width:
W
F
= varied (BSF = emitter)

As can be seen in Figure 2.4, the power loss due to poor contact resistance may reach
10% in a typical EVA solar cell. Low contact resistance gives more flexibility for
optimising other parameters, such as the metal finger width. For the case of Figure 2.4,
a specific contact resistance of below 10
-4
cm
2
is believed to be sufficiently low.

Figure 2.4: Fractional power loss of a typical EVA cell due to the
contact resistance and the metal finger width of glass-side
electrode in a bifacial interdigitated scheme.

18

2.5 The transmission line models

The cross bridge Kelvin resistor [Proctor 1983], the contact end resistor [Chern &
Oldham 1984] and the transmission line model [Burger 1969] are most commonly used
to determine the contact resistance on planar devices. In this thesis, the transmission line
model (TLM) is chosen due to its good accuracy and simplicity. Moreover, the TLM
also includes the contact end resistance measurement which will be discussed later in
this section. All models can only be applied to ohmic contacts because the contact
resistance of Schottky contacts depends on the current density. Furthermore, the
contacts are required to be uniform across the investigated area.

TLM can be further categorized into three different structures. They are variable gap
TLM, ladder network TLM and circular TLM. Each one has specific advantages and
disadvantages with respect to pattern fabrication, measurement, data analysis. However,
the results obtained by any of these models should be identical if they are correctly
applied. All three models are tested, and used in the course of this thesis.
No matter what model is used, the central concept remains the same which is the
so-called current transfer length, L
T
(cm), as illustrated in Figure 2.5. When
contacting a planar device, the current does not flow uniformly into the contact.
Assuming equipotential metal contact, the decay of the voltage underneath the contact,
arising from the semiconductor resistance and the contact resistance is approximately
exponential rather than linear [Meier & Schroder, 1984]. Similarly, the voltage increases
approximately exponentially when current flows out of the contact. These mean most
current flows into or out of the contact at the contact edges. This conclusion comes from
the circuit model which is presented later.

The core contribution of the transfer length concept is that the contact resistance is
equivalent to the resistance of an additional length of semiconductor sheet. This
equivalent length is the current transfer length. It is a characteristic distance over which
the current transfers from the metal contact pad to the semiconductor sheet or vice versa.
In other words, it assumes that the current flows only in the semiconductor sheet
underneath the metal before it reaches L
T
. Therefore, the specific (i.e., area-normalised)
contact resistance,
c
(cm
2
), can be obtained from measuring the transfer length, L
T
,
19
and the semiconductor sheet resistance, R
sheet
(/) [Meier & Schroder 1984]:

2.3
2
T sheet c
L R =

This equation will be derived in Section 2.5.1.

I
2L
L
T
L
T

Metal
Semiconductor

Figure 2.5: Current flow paths under an electrically long
contact (L > L
T
). (After Meier & Schroder, 1984).

It is noted that L
T
is just a characteristic parameter arising from the circuit model to be
discussed below. Practically, there is still current flowing into the contact after the
transfer length if the contact is longer than L
T
.

Three different TLM structures exist based on this concept, as discussed below.

2.5.1 Variable gap transmission line model (TLM)

The original TLM structure, also known as the variable gap structure, is shown in
Figure 2.6(a). The fabrication and operating principle of the variable gap structure is as
follows: Several metal bars are deposited and photolithographically patterned on a
semiconductor sample, whereby the spacing between adjacent metal bars is variable. A
mesa etch step is then performed by means of plasma etching to define the active area of
the semiconductor sample (the gap between the metal bars and the edge of the active
area must be minimised). The details of the fabrication process are described in Chapter
3. Then, an I-V curve is measured between every two adjacent contacts. The total

20
resistance between two adjacent contact bars consists of the resistance of the
semiconductor material (R
semi
) and the contact resistance of two contacts (R
c
), as shown
in Figure 2.6(b):

2.4
c semi total
R R R + = 2

Then the measured voltages (the current is constant for all the I-V measurements) are
plotted versus the spacing of the neighbouring contact bars, giving a straight line using
the least square fit. See Figure 2.6(c). The transfer length L
T
and the semiconductor
sheet resistance R
sheet
are obtained from the x intercept and the slope of the fitted
straight line, respectively. The detailed mathematical model will be derived later in this
section. The y axis intercept corresponds to zero contact spacing and hence is 2 times
the contact resistance (not area-normalised). The specific contact resistance
c
(Ocm
2
) is
then obtained from the L
T
and R
sheet
as given by Equation 2.3. At least two I-V
measurements are required in order to fit a straight line. Extra measurements will
increase the measurement accuracy.

Z
L d
A/V

(a)

R
c
R
c

R
semi

A/V

(b)

(c)

(d)
Figure 2.6: Variable gap TLM (a) top view of original structure; (b) a simple model
of R
total
(cross-sectional view); (c) TLM characteristic curve; (d) circuit model of R
c

(the components are explained in the text).

The mathematical model for the conventional TLM is based on the resistor network
shown in Figure 2.6(d). The current in the semiconductor enters the contact at its
leading edge which is at point 0 and exits the semiconductor via the metal contact with
21
a length of L and a width of Z. Assuming that R
1
(each of the vertical resistors in the
graph) is the contact resistance (not area-normalised) and R
2
is the resistance of a fixed
length of semiconductor material , it follows [Zeghbroeck 2007]:

2.5
x Z
R
c
A
=
1

Z
x R
R
sheet
A
=
2

R
3
is the resistance of a fixed length of metal and close to zero, combining Kirchoff's
laws and Equation 2.5, one obtains the following relations [Zeghbroeck 2007]:

2.6
Z
x R x I
R V x V x x V
sheet
A
= = A +
) (
) ( ) ( ) (
2

2.7
c
x Z x V
R I x I x x I
A
= = A +
) (
) ( ) ( ) (
1

Thus, a set of differential equations can be constructed:
2.8
Z
R x I
dx
dV
sheet
=
) (

2.9
c
Z x V
dx
dI
=
) (

The negative marks indicate the decay of the voltage and the current.
Combining Equations 2.8 and 2.9 gives:

2.10 0
) (
2
2
=
c
sheet
R x I
dx
I d

Equation 2.10 is a second-order homogeneous linear differential equation whose general
solution is:

2.11
x x
e c e c x I
2 1
2 1
) (

+ =

The characteristic roots are:

2.12
c
sheet
R
=
2 , 1

22

The current transfer length L
T
is defined as

2.13
c
sheet
T
R
L
= =
2 , 1
1

Note that Equation 2.3 is just the transform of the positive root of Equation 2.13. Two
boundary conditions are needed to define the constants c
1,2
in Equation 2.11:

2.14
0
) 0 ( I I = 0 ) ( = L I ,

where L is the length of the contact.

Solving Equation 2.10 and utilising the transformations between the potential functions
and the hyperbolic functions, we obtain:

2.15
) sinh(
) sinh(
) (
0
T
T
L
L
L
x L
I x I
=

Then the expression of V(x) can be obtained by substituting Equation 2.15 into
Equation 2.8:

2.16
) sinh(
) cosh(
) (
0
T
T sheet T
L
L
L
x L
Z
R L I
x V

=

The total resistance arises from the contact resistance:

2.17 ) coth( ) coth(
) 0 (
) 0 (
T
sheet c
T
sheet T
c
L
L
Z
R
L
L
Z
R L
I
V
R
= =

Using Equation 2.4, the full expression for the I-V characteristic of the TLM is:

23
2.18 )] coth( 2 [
T
T
sheet
L
L
L d
Z
R
I V + = ,

where d is the spacing between two adjacent contact bars.

The expression for R
c
can be simplified for two limiting cases:

If the length of the contact is large enough (electrically long, L>>L
T
) as shown in Figure
2.5, one obtains:

2.19
Z L Z
R L
Z
R
R
T
c sheet T
sheet c
c
=

L > 2L
T
is sufficient to reduce the error to below 4%. The equation indicates that the
contact resistance does NOT drop with the increasing contact length. The effective
contact area is ZL
T
. Similarly, the I-V expression 2.18 can also be simplified:

2.20 ) 2 (
T
sheet
L d
Z
R
I V + =

If the length of the contact is electrically short (L << L
T
), one obtains:
2.21
Z L
R
c
c

L < 0.4L
T
is sufficient to ensure an error of below 5%. The equation indicates that the
contact resistance drops with increasing contact length. The effective contact area is
ZL. In this case, the contact is equivalent to a full-area contact.

Practically, for solar cell applications, L (the width of the metal contact) is always at
least several tens of times longer than L
T
. Therefore, one can not simply obtain the
specific contact resistance by using Equation 2.21, because the contacts are usually not
full-area contacts. However, the author has found that TLM is often misused in this way
in practice. Generally, Equation 2.19 is used for solar cell applications.

24
2.5.2 Improved variable gap TLM

Conventional TLM pattern fabrication requires a mesa etch step which demands a
precise alignment during photolithography step to minimise the spacing between the
contacts and the active layer edges (see Figure 2.6(a)). In order to minimise the
measurement error arising from the non-uniformity of the sheet resistance, the TLM
pattern is usually fabricated in a small area. Therefore, the contacts are usually too small
to uniformly distribute a large current. Owing to the above two disadvantages, an
improved variable gap TLM structure is developed in the course of this thesis as shown
in Figure 2.7.

Figure 2.7: Top view of the
improved variable gap TLM
structure; the darker area is the
contact, lighter area is the
semiconductor

The improved structure has a similar theory but modifies the original TLM in the
following way: Two large metal pads are added at the ends to supply the current so that
the current is more uniformly distributed and a larger current can be applied. The
voltage is again measured between neighbouring metal bars. The mesa etch defines an
area that is narrower than the width Z of the metal bars so that the error arising from the
spacing between the ends of the metal bars and the edges of the active area is eliminated
(mesa etching does not affect the metal and the buried semiconductor layer). As the
width of the active semiconductor layer can be designed mush smaller than Z, no
precise alignment is needed when mask the area from being mesa etched during the
photolithography step (lighter area in Figure 2.7). Therefore, the fabrication process is
significantly simplified. The semiconductor underneath the metal which is outside the
active area does not affect the measurement providing that the metal sheet resistance is
negligible. The improved model is also compatible with the conventional measurement.
The details of the fabrication process are described in chapter 3.

25
The mathematical model for the improved variable gap structure (Figure 2.6(b)) is
slightly different from the conventional one but very similar to the improved ladder
network structure which is described in Section 2.5.4.

2.5.3 The contact end resistance measurement

The R
sheet
used to determine the contact resistance is, strictly speaking, the sheet
resistance directly under the contact. The transmission line models assume that the sheet
resistance of the semiconductor under and outside the contact is identical. However,
exceptions can occur when sintering or alloying the contacts, leading to
metal-semiconductor reactions. As a result, the sheet resistance underneath the contact
may differ from that in the metal-free regions [Reeves & Harrison 1982]. Therefore, a
so-called contact end resistance (R
E
) measurement has to be conducted to obtain the
sheet resistance value under the contact. Most TLM structures are compatible with such
a measurement, which is schematically shown in Figure 2.8.

Figure 2.8: Experimental methods for contact end resistance
measurement. (After Reeves & Harrison 1982)

The contact end resistance (R
E
) can be measured via either of the two following ways
[Reeves & Harrison 1982]:

26
2.22
I
V
R
E
=
2.23 ) (
2
1
3 2 1
R R R R
E
+ =

However, if the contact resistance R
c
is much small than the total resistance between
two contacts, Equation 2.22 is preferred. The relation between R
E
and R
c
is given by:

2.24 ) cosh(
T E
c
L
L
R
R
=

R
c
can be yielded by the intercept of the characteristic curve shown in Figure 2.6(c).
Thus the transfer length L
T
can be found and the specific contact resistance
c
can be
obtained by:

2.25
) sinh(
1
T
T
c
E
L
L
Z L
R

Then the modified sheet resistance under the contact R
SK
is given by:

2.26
2
T
c
SK
L
R
=

Reeves and Harrison (1982) reported that significant sheet resistance alteration only
occurs when sintering contacts on lowly doped silicon. Low-temperature annealing of
the contacts on heavily doped silicon does not cause significant reaction of the contact
interface. The annealing temperature for almost all contacts in the course of this thesis is
below 300C which was found to negligibly change the sheet resistance under the
contact, both theoretically and experimentally.

27
2.5.4 Ladder network transmission line models

A. Conventional structure

The key feature of the ladder network is that the spacing between neighbouring contact
bars is constant. The conventional structure is shown in Figure 2.9. A constant current is
supplied via two contact pads at the ends. Then the voltage is measured between one
large contact pad and each of the small contact bars. During the measurement, the
spacing between two terminals is variable so that this structure becomes equivalent to
the variable gap TLM structure. The resulting voltage versus spacing curve has a slope
that is also identical to the characteristic curve of variable gap structure. However, the
width of the contact bars must be narrower than the transfer length so that no significant
error builds up when moving from left to right in Figure 2.9. Fundamentally, this
technique is always accompanied with errors and is not suitable for samples with small
transfer length.

Z
L d
A
V

Figure 2.9: Top view of the
conventional ladder network
structure. (After Mak 1989)

B. Improved structure

An improved structure, proposed by Meier and Schroder (1984), is shown in Figure
2.10(a). It is mathematically similar to the improved variable gap TLM (Figure 2.7) but
different to the conventional structure in operation principle. The transfer length is
obtained via I-V measurements between contact pads a and b, whereas the sheet
resistance is obtained via I-V measurements using pads b and c.

28

(a)

(b)

Figure 2.10: (a) top view of the improved Ladder
network structure; (b) circuit model. (After Meier and
Schroder 1984)

The corresponding resistor network is shown in Figure 2.10(b). The mathematical
model is similar to that of the conventional variable gap TLM structure. The difference
is that the current flow into the contact at L/2 and flow out at L/2. L is the contact
length. Therefore, the boundary conditions in Equation 2.14 change to the following:

2.27
0
)
2
( I
L
I =
0
)
2
( I
L
I =

Assuming zero sheet resistance of the metal (i.e., R
3
= 0 in Figure 2.10b), one obtains
the I-V characteristics [Meier and Schroder 1984]:

2.28
(
+ = )
2
tanh( 2
0
T
T
sheet
ab
L
L
L d
Z
R nI
V ,

where n is the number of gaps between pads a and b. The contact resistance is
accumulated over n gaps to improve the precision. R
sheet
is obtained from I-V
measurements via pads b and c:

29
2.29
S
Z
I
V
R
bc
sheet
=

As mentioned in Section 2.5.2, the I-V expression of the improved variable gap TLM is
similar to Equation 2.28. The only difference is that d and Rsheet are obtained via fitting
of the characteristic curve. And n is omitted as the spacing between the neighbouring
contacts is variable.

Equation 2.28 can be further reduced if L/2L
t
> 2 (with error < 4%):

2.30 ) 2 (
0
T
sheet
ab
L d
Z
R nI
V + =

This equation is very similar to the simplified I-V expression of conventional variable
gap structure (Equation 2.20).

The improved ladder network model significantly simplifies the measurement and
analysis process because no curve fitting is required, but demands a relatively rigorous
photolithography process as the number of metal bars involved is usually more than
several tens and the spacing must be strictly constant. Moreover, the resistance of the
semiconductor sheet between pad b and c must be much larger than the corresponding
contact resistance, and the sheet resistance uniformity must be superb across the entire
active area so that R
sheet
between pads b and c can be used to represent R
sheet
between
pad a and b. Due to these restrictions, this technique is convenient but not as reliable as
the variable gap TLM given the available equipments in the course of this thesis.
Therefore, the ladder network TLM was only used at the beginning of this thesis work
and was later abandoned.

2.5.5 Circular transmission line model (CTLM)

Marlow and Das (1982) proposed the circular TLM structure shown in Figure 2.11. It is
similar to the variable gap TLM but uses a circular structure. This clever change saves
the mesa etch step because the active semiconductor area is surrounded by the metal

30
contact, which dramatically simplifies the fabrication process. By passing a constant
current from the large metal pad to each of the isolated contact circles, the voltage drop
over each semiconductor ring can be measured. Then a curve of voltage against spacing
can be plotted. The transfer length and the sheet resistance of the semiconductor are
obtained by using Equation 2.31 to fit the voltage curve (least square non-linear fitting,
see Figure 2.12.

Figure 2.11: Top view of the circular TLM structure. The grey
area is the metal and the white ring-like area is the exposed
semiconductor.

2.31 )]
1 1
( ) [ln(
2 d r r
L
d r
r
R I
V
T
sheet
+ +
=
t
,

where r is the radius of the outer circle of the semiconductor ring and d is the width of
the ring (current pathlength between the outer contact pad and inner contact circle).
Note that Equation 2.31 is a simplified one and only valid when r-d is 4 times greater
than L
T
[Marlow & Das 1982], which is usually the case in practice. It can be further
reduced to Equation 2.20 (conventional variable gap TLM) with 2r = Z, if r >> d. The
error caused by this linear approximation is experimentally investigated in Figure 2.12
and Table 2.2, where the results yielded from non-linear fitting (solid lines) and the
linear fitting (dashed lines) are compared.

31
y =0.1753x +4.2311
R
2
=0.9977
-10
-5
0
5
10
15
20
25
30
-40 -20 0 20 40 60 80 100 120
spacing (m)
v
o
l
t
a
g
e

(
m
V
)
140
voltage_measured
non-linear fit
linear fit

(a)

y =0.0732x +4.2698
R
2
=0.9878
-2
0
2
4
6
8
10
12
14
16
-80 -60 -40 -20 0 20 40 60 80 100 120 140
spacing (m)
v
o
l
t
a
g
e

(
m
V
)
voltage_measured
non-linear fit
linear fit

(b)

Figure 2.12: Linear (dashed lines) and non-linear (solid lines) fitting of the CTLM
data measured from on a sc-Si wafer with p
+
surface. (a) Larger error; (b) Smaller
error

Table 2.2: Comparison of results obtained from linear and non-linear fitting of
CTLM data with different d/r ratio.

Curve Fitting d / r R
sheet
(O/) L
T
(m)
c
(Ocm
2
) Error
Linear (a) 14.5% 117 12.1 1.710
-4
+236%
Non-linear (a) 14.5% 128 7.5 7.210
-5
NA
Linear (b) 9% 96.1 28.6 7.910
-4
+37%
Non-linear (b) 9% 102.7 23.6 5.710
-4
NA

Practically, non-linear curve fitting is adopted due to the following two factors: i) it is
not wise to make CTLM patterns fulfilling the condition of r >> d owing to the
restrictions of the available photolithography technique and large lateral variations in
the sheet resistance; ii) the mathematical modelling of non-linear fitting is substantially
facilitated by resorting to numerical methods such as Excel.

32

In the course of this thesis, the CTLM was used most, followed by the improved
variable gap structure. The improved ladder network structure was only used in the
initial stages of the research until its the structural unreliability was understood. As
discussed in Section 2.5.4, a constant spacing between the metal bars is difficult to
achieve with the equipment available for this research.

2.5.6 Practical requirements of the transmission line models

The main difficulty of measuring a small contact resistance (R
c
) on a substrate with high
sheet resistance lies in the fact that R
c
is usually much smaller than the resistance arising
from the semiconductor sheet (R
semi
) if TLM technique is employed. It is a task similar
to looking for a needle in a haystack. In order to distinct the needle (R
c
), the only two
solutions are to either make the needle as large as the haystack (R
semi
) or to make the
haystack as small as the needle. Usually, the latter solution is more realistic. Equation
2.4 explains this contact resistance measurement guideline in a mathematical way:

2.32
c semi total
R R R + = 2

R
total
is easy to obtain. However, R
c
is usually so small that it can be easily smeared by
R
semi
. Theoretically, the spacing d between neighbouring contact bars does not influence
the measurement. However, practically, this parameter can be the dominant factor of
measurement reliability because no material is absolutely uniform in lateral. From the
viewpoint of device design, it is not realistic to arbitrarily decrease the sheet resistance.
Therefore, in order to reliably measure the specific contact resistance, the spacing must
be kept as small as possible. To do this, a good photolithography process is essential.
This is discussed in the next Chapter.

33

3 Sample fabrication and
characterisation

3.1 Sample cleaning

Piranha solution is used to clean the silicon sample surface by mixing 1 volumetric unit
of 98% sulphuric acid (H
2
SO
4
) and 1 volumetric unit of 30% hydrogen peroxide (H
2
O
2
).
The mixing process is exothermic and heats the resultant solution to about 120C. The
reaction of the above two liquids can be viewed as the energetically favourable
dehydration of hydrogen peroxide to form hydronium ions, bisulphate ions, and,
transiently, atomic oxygen [Wikipedia 2007]:

3.1 O HSO O H O H SO H + + +
+
4 3 2 2 4 2

The final mixture removes most organic matter as it is a strong oxidizer, and metal
particles as well due to its high acidity. It also hydroxylates the silicon surface (adds OH
groups), making it extremely hydrophilic. Therefore, the sample is typically dipped in
5% hydrofluoric acid (HF) to make the surface hydrophobic. The chemical reaction
equation is shown below. After the HF dip, the dangling bonds of the silicon atoms at
the surface are passivated by hydrogen atoms. Therefore, the surface is hydrophobic.

For the formation of metal contacts, the silicon cleaning process is usually immediately
followed by metal evaporation to minimize the chance of surface contamination and
oxidization. Within less than one hour (maximum time for handling and preparing for
metallization), less than 7 of native oxide grows on the Si surface, which does not
harm the contact properties [SNF 2007].

3.2 O H SiF HF SiO
2 4 2
2 4 + +

34

3.2 Aluminium evaporation

This is the key step of metallization. Aluminium deposition is accomplished in a
vacuum chamber via resistive evaporation, whereby a large current is passed through a
tungsten boat loaded with aluminum filaments. The process is performed in vacuum
because this allows vapor particles to travel directly to the target object, where they
condense back to the solid state. The lower the base pressure, the lower is the rate for Al
atoms to be oxidized before they reach the sample, hence the better the contact quality.
However, achieving high-vacuum conditions (< 10
-6
Torr) is very time-consuming with
the equipment available for this thesis work. The base pressure generally used in this
thesis is therefore 10
-5
Torr, which gives fairly good contact resistance and metal sheet
resistance.

3.3 Photolithography and pattern fabrication

In order to measure specific contact resistances of below 10
-4
cm
2
on a substrate with
1000 /sq sheet resistance, the measurement patterns must be fabricated as small as
possible. Therefore, a good-quality photomask and good pattern transfer are the most
important prerequisites for accurate contact resistance measurements.

3.3.1 Photolithography procedures

Photolithography is the key step for fabricating contact resistance measurement patterns.
Its basic principle is using a photosensitive and etchant resistive material (resist) to
selectively protect the substrate material by using a photomask. Subsequently, the
unprotected/exposed area of the substrate material is removed by the etchant. As a
consequence, the patterns on the photomask are accurately transferred to the substrate
material after photoresist stripping. Each photolithography process transfers one layer of
the patterns. Alignment is usually necessary when transferring multiple layers of the
patterns. Modern IC fabrication typically requires several tens of layers. The process
procedures are as follows (also see Figure 3.1):
35

Adhesion promotion
(Photo)Resist coating
Prebake
Alignment
Exposure
Post-exposure bake
Inspection
Development
Measurement and inspection
Postbake
Sample cleaning
The steps in italic
are optional.

Figure 3.1: Routine procedures of photolithography.

36

Sample cleaning: The surface of the Si sample is piranha (or oxygen plasma) cleaned to
get rid of organics and other foreign particles which may increase the surface roughness
or create observable defects after spinning the resist. Acetone and isopropanol clean is
performed prior to the piranha clean in order to strip the photoresist if the sample is
found unqualified after resist coating step.

Adhesion promotion: Resists typically do not adhere well to untreated Si surfaces and
Si-containing materials such as silicon dioxide and silicon nitride. To ensure proper
adhesion, the wafer surfaces are treated prior to resist coating, whereas this step is
omitted when coating resists on aluminium due to excellent adhesion.

Resist coating: Resist is typically comprised of organic polymers applied from a
solution. It is typically photosensitive, hence also called photoresist. Photoresist is
usually deposited by spinning at several thousands rpm and forms a thin film (typically
0.5-2.5 m) of solid resist. The high resist film thickness homogeneity of the resist as
well as the short coating times makes spin coating the most-applied resist coating
technique in the microelectronics industry. However, in case of non-rotation-symmetric
substrates, the resist forms a pronounced edge bead near the substrate edges due to the
strong air turbulences. Some regions of such samples might not be coated at all.

Photoresists can also be applied by spray coating and dip coating [Levinson 2004]. The
spray coating technique works with all arbitrary sized and shaped substrates, even with
three-dimensional bodies. Substrates with pronounced surface roughness are also easy
to be spray-coated. However, the roughness is relatively high and the attained edge bead
coverage is not satisfactory. Dip coating applies to large-scaled and arbitrary-shaped
substrates. Its thickness uniformity changes over the dimension of the substrate. All
sides of the substrate are coated, which may be an advantage or disadvantage.

The only coating technique used in this thesis is spin coating, despite the large number
of non-rotation-symmetric substrates being used in this thesis.

Inspection: Check by bare eye if there are any defects/contaminations. In the case of
small non-rotation-symmetric substrates, care has to be taken to ensure that most of the
37
surface area is coated. If the spin coating fails, restart the whole process (including the
sample cleaning step).

Prebake: The photoresist is liquid right after the resist coating step and will easily stain
and stick to the contact photomask during the exposure step. Its density is also
insufficient to support wet-chemical processing and may create many problems such as
bubbling. A bake is therefore indispensable for densifying the resist film, driving off
residual solvent and promoting adhesion.
Alignment: When transferring multiple pattern layers, good alignment ensures the new
patterns are placed at the correct position on top of the preceding layers within
allowable tolerances. Detailed alignment techniques will be discussed in Section 3.3.4.

Exposure: A mercury lamp is installed in the mask aligner to provide a broadband
UV/near-UV spectrum (Figure 3.2) and is well matched to the photoresists used (Figure
3.3 and Figure 3.4). Positive photoresists become soluble after exposure and can be
removed by a suitable solution, while negative photoresist behaves oppositely.

Post-exposure bake: This optional step drives additional chemical reactions or the
diffusion of components within the resist.

Figure 3.2: Hg light without optical
selective filters contains g- (wavelength
436 nm), h- (405 nm) and i-line (365 nm),
with an i-line intensity of ~40% of the total
emission between 440 and 360 nm [Micro-
chemicals 2007].

38

Figure 3.3: Absorption spectra of
negative photoresists ma-N400 and
ma-N1400. The negative photoresist
used in this thesis is ma-N400, which
has very similar properties as the
ma-N400 [Rohm & Haas 2007].

Figure 3.4: Absorption spectrum of
positive photoresist S1813, which has
very similar properties as the S1818
photoresist [Microresist tech. 2007].
Development: This is a wet-chemical step by which resist is removed depending upon
whether it has been made soluble by the exposure step.

Measurement and inspection: This operation is for determining if the resist features on
the substrates are sized correctly, properly overlay preceding patterns, and are
sufficiently free from defects. Although this is an optional step in industry, it is always
necessary for lab-scale processing. Failed samples have to be re-processed, starting with
the cleaning step.

Postbake: This is another optional process. Postbake is used to crosslink the photoresist
molecules, drive out volatile organic materials and water in order to (i) preserve the
vacuum integrity of the etch equipment and (ii) to further densify the resist film. The
temperature is much higher than that of the prebake.

39
3.3.2 Photomask design

It goes almost without saying that a high-quality photomask plays the most important
role in photolithographic processes. Several photomasks were designed in the course of
this thesis. The best one is presented and discussed in this section. The whole design
consists of two layers, metal layer and mesa layer. The metal patterns are first fabricated
via the metal layer mask. Then the mesa layer mask is used to define the active area of
each pattern on the substrate. (Remark: A mesa etch is not required for the CTLM
structure). Figure 3.5 gives an overview of one cell of the two-layer design drawn with
the program LAZI CAD. The main feature of the design is that each type of pattern is
repeated many times. The cell shown in Figure 3.5 is repeated 6 times to form a
complete mask for 5 by 5 cm
2
samples. Such an approach ensures flexibility with
regards to pattern fabrication and electrical measurements on samples featuring
non-idealities such as wrinkles or curved surfaces.

A
B
C
D
F
E

Figure 3.5: Overview of one cell of the 2-layer mask design (purple = metal layer;
red hatch = mesa layer). The area shown measures about 24 mm by 16 mm. Detailed
views of each of the different patterns (A-F) are presented below.

40
Detailed views of each of the patterns are shown in Figure 3.6. The patterns CTLM (A)
and TLM (B) are for measurements of the specific contact resistance
c
. The area of
each pattern is well below 5 mm
2
(note that 4-point probe measurements require a
minimum area of about 50 mm
2
), which helps to reduce problems associated with
samples featuring spatially non-uniform sheet resistance. The current pathlength
between neighbouring metal contacts is very short (in the 5-60 m range), making the
contact resistance comparable with the resistance of the semiconductor sheet. The
measurement capabilities versus the semiconductor sheet resistance of these patterns are
listed in Table 3.1.

(A)

(B)

(C)

(D)

(E)

(F)

Figure 3.6: A: Circular TLM pattern; B: In-line TLM pattern; C: Metal sheet resis-
tance measurement pattern; D: Hall effect measurement pattern; E: Semiconductor
sheet resistance pattern; F: Alignment marks and patterns.

41

Table 3.1: Relationship between the smallest measurable specific contact resistance
and the sheet resistance of the contacted silicon layer.
R
sheet
(/) < 10 100 500 1000 5000 > 10000
c
(cm
2
) < 810
-8
810
-7
410
-6
810
-6
410
-5
810
-5

Figure 3.6(C) shows a pattern for measuring the sheet resistance of a metal film. It
forces the current to flow along a long distance of the metal sheet so that the total
resistance is large enough to be measurable. The mesa etch can be omitted if the sheet
resistance of the semiconductor is much larger than that of the metal. The metal sheet
resistance is about 0.1 / for a 500 nm thick Al film, as given in Section 2.2.1.

Figure 3.6(D) shows a Hall effect measurement pattern. It can be used to measure the
free carrier concentration and the Hall mobility of the semiconductor layer. To avoid
parasitic effects due to the MS contacts, a buffer area (four red hatched pads) is
designed to connect the active area (one smaller pad at the centre) and the metal.
However, due to the unavailability of a Hall effect measurement set-up, this pattern was
not used in this thesis.

The pattern in Figure 3.6(E) is used to measure the sheet resistance of the
semiconductor without any data fitting. Figure 3.6(F) presents the alignment marks and
the vernier patterns. The horizontal and vertical venier patterns can be used to estimate
misalignments. Each one consists of two layers, metal and mesa. When there is no
misalignment, the 0 m slot of the metal venier is fitted by a gear of the mesa venier.
When misalignment happens, for example if the left and the top 20 m slots of the
metal venier are fitted by the mesa gears, the patterns on the mesa mask are misaligned
leftwards and upwards by about 20 m, respectively. Two example photos are shown in
Figure 3.12 (lower two photos).

3.3.3 Pattern fabrication

The measurement models/patterns presented in Section 2.3 can be fabricated through
either positive photoresist plus standard photolithography or negative photoresist plus a
lift-off process. These two schemes, which reach the same goals via different routes, are
42

schematically shown in Figure 3.7.

The two-step photolithography process used in this thesis is shown in Figure 3.7. Step 1
refers to metal etching and step 2 refers to mesa etching. In step 2, both the aluminium
layer and the photoresist layer act as a protecting mask for the silicon layer during
plasma etching. Plasma etching is used as it is a selective process that has a fast etch
rate for silicon but a slow etch rate for both photoresist and metal.

Etching is always a hazardous process. Thus, the lift-off process is more widely used by
people because it saves chemical etching as well as photoresist stripping steps. And
isotropical etching (e.g., wet-chemical etching) undercuts the metal underneath the
photoresist, which creates the curved sidewalls of the metal. Wide sidewalls (> 1 m)
encumber the dimension measurements of the semiconductor gaps. Moreover,
photoresists do not have good adhesion on all types of metal. On the other hand, the
lift-off process demands a very steep photoresist sidewall after the exposure step and a
relatively thin metal layer (less than half the thickness of the PR), which requires (i) a
very collimated light beam; (ii) intimate contact between the photomask and the sample
(can be relaxed for a well-collimated light beam); (iii) no light reflection inside the
sample during exposure.

43

2nd photolitho-
graphy step
PR coating
and exposure
Development
Aluminium
etching
PR stripping
PR coating
and exposure
Development
Development
Plasma etching and
PR stripping
Aluminium
deposition
Collimated UV
light beam
Photomask (opaque area)
Aluminium film
Photoresist (PR)
Silicon thin-film
Glass
Aluminium
lift-off
Standard photolithography
with positive photoresist
Lift-off photolithography
with negative photoresist
PR coating,
alignment, UV
exposure
Al
Glass
Si

Figure 3.7: Process flow of pattern fabrication (not to scale).
Aluminium
deposition

44
However, given the available equipment for this thesis, the first and second require-
ments are very difficult to fulfil (see Figure 3.8). The available light beam is not very
collimated. Overexposure creates undercut of the photoresist after development, while
underexposure creates positive-angled sidewall and enables metal to almost fully cover
the sidewall, which hinders the metal from being lifted off. Furthermore, most of the
solar cell samples investigated in this thesis are not flat (the glass bends upwards at the
corners due to the solid-phase crystallisation step at 600C or is wrinkled on the silicon
side due at the rapid thermal anneal (RTA) step at about 900C). Therefore, there is
always a gap between the photomask and the sample surface. In case of not using
vacuum to suck the sample onto the mask, the gap is even larger. This gap and the rough
sample surface are the main problems for the photolithography process, as they lead to a
non-uniform exposure of the investigated samples (typical size 5 by 5 cm
2
). Although
underexposure seems to be helpful for the lift-off process (as it creates an undercut),
underexposure of the whole surface often leads to some areas to be too weakly exposed
and hence creates incomplete patterns and lines, which may render the sample useless.

UV lamp
Photoresist
Photomask
Glass substrate with rough Si film
(texture not shown)
Exposed area in
underexposure situation
Extra exposed area
in overexposure
situation
Gap
Rough surface
UV light (not collimated)

Figure 3.8: Cross-sectional view when UV-exposing a sample with a rough surface
(not to scale).

Another limitation of the lift-off process is the required thinness of the metal layer
(< 50% of the PR layer thickness), which results in a large metal sheet resistance in
those cases where a thin photoresist layer has to be used. If the metal sheet resistance is
not negligible compared to the silicon sheet resistance, the analysis of TLM
measurements is significantly more complicated than in the standard case. The power

45

loss associated with current flow in the metal layer will also increase.

For all these reasons, the standard photolithography process is preferred for the
investigations of this thesis. Although it may also suffer from the non-uniform exposure
problem, a few process control methods/procedures were developed to alleviate its
disadvantage. As a result, a robust photolithography process on wrinkled poly-Si
samples was established. Moreover, the adhesion of the photoresist on aluminium is
excellent.

3.3.4 Process optimisation and the results

- The evaporated Al layer should be thin enough to avoid a wide sidewall after
wet-chemical etching but thick enough to ensure a negligible sheet resistance.
The thickness is ideally in the range of 300 to 500 nm.
- The gap between the photomask and the sample caused by the curved glass
substrate (after crystallisation) is usually much more problematic than wrinkles
(after RTA). One should always try to get the sample RTAd, not only to
improve its flatness, but also to reduce the density of point defects in the Si film
as well as to activate the dopants [Terry 2006]. If the glass is still bent after RTA,
then it is recommended to do another, short RTA to flatten the glass. The
flatness can be tested by placing the glass on a level polished metal surface. If
the glass does not rotate when a small rotational force is applied, then the
flatness is good enough.
- A high-quality photomask is essential for a successful photolithography process.
By using vacuum, an intimate contact can be achieved during UV exposure.
Placing the mask directly on the sample without vacuum always creates a wide
gap.
- The exposure time is the second-most important parameter in the photolitho-
graphy process. A large number of experiments performed in the course of this
thesis indicate that 5 s exposure time is ideal for the negative photoresist, while
12-15 s is best for the positive photoresist. These are the reference times for
moderately wrinkled poly-Si films. For heavily wrinkled samples or exposure
46

without a vacuum, or both, the exposure time should be increased by at least
20%.
- Remove the sample immediately from the mask aligner after exposure, as there
is still some UV light emitted by the machine.
- The ideal development time for both types of photoresist was found to be
40-45 s.
- When using hot phosphoric acid to etch the aluminium, care should be taken to
not produce too many bubbles. The bubbles are H
2
created by the chemical
reaction. The regions covered by the bubbles are etched much more slowly, and
consequently a large number of small Al islands will remain when most areas
are free of Al. A short dip in DI water after every 30-45 s etching interval was
found to be very helpful. The etchant temperature should be kept below 60C to
avoid severe overetching.
- A Measurement and inspection step should always be performed after the PR
development step and the phosphoric etching step.
- The chromium photomask should be regularly Piranha-cleaned (for example
whenever it has been used 30 times).

Below are two images representing good (left) and bad (right) photolithography
processes. The bad process can be avoided by applying the above-mentioned process
control methods.

47

Figure 3.9: Optical microscope image of
a sample with a 5 m wide arc with
smooth edges. The dark area is
aluminium and the bright area is silicon.

Figure 3.10: Optical microscope
image of a sample with a nominally 5
m wide ring. Due to underexposure,
some regions are thinner than 5 m
which renders this sample useless. The
dark area is aluminium and the bright
area is silicon.

A photo of a finished 5 by 5 cm
2
sample is presented in Figure 3.11.

Figure 3.11: Photo of a finished 5 cm by 5 cm sample. The yellowish
areas at the edges and corners are silicon layers which arise from edge
defects of the photolithography process.

48
Figure 3.12 shows a series of optical microscope images (transmission mode) of
finished patterns. The black area is metal, the dark brown area is silicon, and the light
brown area is glass covered with a very thin SiN residual layer (the SiN film was
thinned by the plasma etching step). The numbers above the verniers in the lower two
images have critical dimensions of less than 3 m. Considering that the minimum line
width obtainable with the UV exposer used in this work is 1-2 m, the photolithography
optimisation can be considered as successful.

(a)

(b)

(c)

(d)

Figure 3.12: (a) Part of CTLM and TLM patterns; (b) Hall effect pattern;
(c) Horizontal vernier with ~18 m leftward misalignment; (d) Vertical vernier with
~20 m downward misalignment.

3.4 Plasma etching

A plasma etcher with CF
4
or SF
6
gas is used to dry-etch the silicon. It consists of two

49

parallel plates as two electrodes in a vacuum chamber with moderate vacuum conditions.
The sample sits on the bottom plate which is grounded. A RF (radio frequency) power
generates an oscillating electric field which ionizes the feed gas molecules by stripping
off some of their electrons, creating a plasma. Fluorine-containing plasma species then
attach themselves to the exposed silicon surface, which leads to the creation of SiF
x

molecules via dry chemical reactions. SiF
x
molecules then leave the reacting positions
via volatilizing in the forms of SiF
2
or SiF
4
[Campbell 2001]. Due to the use of a low
power level and the grounding of one electrode, the etching process is not accomplished
through physical collisions. Therefore, the plasma etching process is more isotropic than
RIE. A U shaped sidewall is typically created by the plasma etch process, which favours
emitter electrode formation (contacting the exposed sidewall of the emitter layer).

3.5 Wet-chemical etching with coloured HF

Coloured HF is a way to wet-etch silicon isotropically. The solution consists of
potassium permanganate (KMnO
4
) and 5% HF in a certain proportion and has a purple
colour. The whole process can be divided into two steps. First, KMnO
4
oxides the
silicon; second, HF removes the oxidized layer. The two etch recipes for coloured HF
shown in Table 3.2 are used for different material and purposes. The etch rate for
poly-Si materials is approximately 15 times faster than that for sc-Si. Therefore
Recipe 1 is usually used for sheet resistance profiling and surface treatment of poly-Si
thin-films or solar cells, while recipe 2 is usually used for sheet resistance profiling of
c-Si wafers.

Table 3.2: The recipes of the coloured HF.

Recipe No. 1 2
KMnO
4
(g) 6 6
DI water (ml) 187.5 100
5% HF (ml) 12.5 100
Total volume of solution (ml) 200 200
HF concentration of solution, % 0.313 2.5
KMnO
4
concentration of solution (g/100ml) 3 3
Etch rate for c-Si (nm/s) 0.1 4

The reason why coloured HF etches poly-Si much faster than sc-Si is believed to be due
50
to the grain boundaries. Coloured HF etches grain boundaries more quickly than the
bulk of the grains, as can be seen in Figure 3.13. These images were taken with an
optical microscope in the transmission mode (left column) and reflection mode (right
column), respectively. The contrast due to the boundaries is getting stronger with
increasing etch time. The grain size is approximately 5 m.

(a)

(d)
(b)

(e)
(c)

(f)
Figure 3.13: (a)-(c) Images in transmission mode for 20 s, 45 s and 70 s etching in
coloured HF; (d)-(f) Corresponding images in reflection mode.

51
3.6 Sheet resistance profiling

In order to examine the doping uniformity of solid-phase crystallised (SPC) poly-Si
thin-films and the surface doping concentration of c-Si wafers with p
+
or n
+
-diffused
surfaces, a sheet resistance profiling method is employed [Di 2007]. A thin layer of
silicon with thickness preferably in the 10-50 nm range is removed per etching step,
using either coloured HF (KMnO
4
+ HF) or plasma etching (SF
6
). The Si etching rate of
each of these methods is approximately constant over time. The sample thickness is thus
stepwise reduced. Sheet resistance and hot-probe measurements are conducted before
every etching step, whereby the hot-probe technique determines the doping polarity of
the exposed surface. In order to minimize measurement error and to obtain better data
analysis, the sheet resistance profile curves are fitted with fourth-order polynomials.
Higher-order polynomials were found to be unsuited because they often introduce
significant errors with data fitting at low etching depths (i.e., close to the original
sample surface).

Because the doping concentration at/near the original silicon surface is most relevant for
metallization work and contact resistance studies, the data points in the range 0-250 nm
are fitted with a second-order polynomial instead of a fourth-order polynomial.
Examples for this procedure are shown in Figure 3.14. The R
2
values are close to 1,
indicating good fit quality.

Sht :`:tuu o`' `th o')uomù' `ttù_
) 0.00?x
?
0.!+99x !+8.9
k
?
0.9883
) 0.00!?x
?
0.!9x !?.!
k
?
0.99b9
) 0.00!?x
?
0.!9?x !08.3
k
?
0.993!
0
0
!00
!0
?00
?0
300
30
+00
0 0 !00 !0 ?00 ?0 300
lthù_ Dth um)
o
h
m
:um' !
:um' ?
:um' 3

Figure 3.14: Measured sheet resistance profiles (symbols) and
corresponding second-order polynomial fits (lines) of the surface regions
of three p
+
-diffused singlecrystalline n-Si wafers.

52
Assuming a uniform doping concentration within each removed thin Si layer (22 nm in
Figure 3.14), the fitted polynomials allow the determination of the resistivity of each
removed Si layer. This procedure involves a simple circuit model consisting of two
parallel resistors, as shown in Figure 3.15. The thinner each removed layer, the more
accurate the method will be.

Figure 3.15: Method of obtaining the
Si resistivity from the measured sheet
resistance. R
tot
is the sheet resistance
of the specimen in O/ measured
before an etching step. R
etched
is the
sheet resistance of the layer that is
removed in this etching step. R
remaining

is the sheet resistance of the specimen
in O/ measured after this etching
step.

The sheet resistance R
etched
of the removed layer in this etching step can be calculated by

3.3
remaining tot
etched
R R
R
1 1
1
=

The resistivity
etched
of this thin layer is the product of its sheet resistance and its
thickness:

3.4
etched etched etched
t R =

The depth-dependent resistivity profile of the silicon sample can thus be obtained. As an
example, Figure 3.16 shows the corresponding results for the three Si wafer samples of
Figure 3.14. From the resistivity profile, the majority carrier profile (i.e., the profile of
electrically active dopants) can be determined using graphs, data books or numerical
silicon device simulators such as PC1D [SPREE 2007]. As an example, Figure 3.17

53
shows the corresponding results obtained from the data of Figure 3.16. They suggest
that the highest doping densities do not occur right at the surfaces of these
boron-diffused Si wafers but at a depth of 70-90 nm below the original surfaces. This
behaviour is a well known feature of boron-diffused and subsequently oxidised Si
wafers [Sze 2001].

k:`:t`v`t) o`'
0
0.00?
0.00+
0.00b
0.008
0.0!
0.0!?
0 0 !00 !0 ?00 ?0 300
lthù_ Dth um)
:
`
:
t
`
v
`
t
)

o
h
m
.
m
)
:um' !
:um' ?
:um' 3

Figure 3.16: Resistivity profiles of the three Si wafer samples of Figure
3.14.

l:t`mutd Doù_ lo`'
0.00l00
.00l!8
!.00l!9
!.0l!9
?.00l!9
?.0l!9
0 0 !00 !0 ?00 ?0 300
lthù_ Dth um)
3
:um' !
:um' ?
:um' 3

Figure 3.17: Active dopant profiles of the three Si wafer samples of Figure
3.16. The results were obtained using PC1D modelling.

54

3.7 Spectroscopic measurements

The thickness of the investigated thin-films is obtained via reflectance measurements
using a spectrophotometer (Varian CARY 5G). This instrument is able to measure the
spectrum of reflected (or transmitted) light in the range 200-2500 nm (ultraviolet to
near-infrared). The CARY 5G is a dual-beam system. The first beam is used for
reference purposes, while the second beam is directed onto the sample using lenses and
mirrors. The set-up features an integrating sphere (diameter ~15 cm), whereby the
sample can be mounted on the rear port of the sphere (for reflectance measurements) or
on the front port (for transmission measurements). Alternatively, the sample can be
mounted inside of the sphere (centre-mount) for absorption measurements. In the case
of reflectance measurements, the second beam gets partly reflected at the sample
surface and the reflected light intensity is recorded by a detector located near the bottom
of the sphere. Two lamps are used in this system, one for measurements in the 200-350
nm range and one for the 350-2500 nm range.

After the raw reflectance data have been obtained, the average thickness value can be
obtained by using the wavelength and refractive index of every two adjacent
interference peaks. However, significant error can be produced when picking these two
parameters. Therefore a modelling program called Wvase32 is applied to acquire the
thickness value. Figure 3.18 illustrates two reflectance curves and the corresponding
fitting curves. Combined with sheet resistance measurements, the resistivity of a
uniformly doped silicon layer can be easily worked out.

55
Generated andExperimental
Wavelength (nm)
400 600 800 1000 1200
R
e
f
l
e
c
t
i
o
n
0.00
0.10
0.20
0.30
0.40
0.50
0.60
Model Fit
ExpuRb8

(a)

Generated and Experimental
Wavelength (nm)
600 700 800 900 1000 1100 1200
R
e
f
l
e
c
t
i
o
n
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
Model Fit
ExpuRb8

(b)

Figure 3.18: Wvase reflectance curve fitting of (a) an EVA
cell (1945 nm Si and 43 nm SiN) and (b) an SPC layer (933
nm Si and 60 nm SiN).

3.8 Dark I-V measurements
3.8.1 Four-point probe tester

A four-point probe tester from Signatone is used in this thesis to quickly measure the
sheet resistance of a film or a solar cell. Figure 3.19 demonstrates the operating
principle [Wenham 2006].

56

Figure 3.19: Use of a four-point probe to
measure the sheet resistance of a p-n
junction diode. The junction depletion
region between the n and p-doped layers
acts as an insulating barrier. The system
used in this thesis has a probe spacing s of
1.25 mm. t is the thickness of the layer to
be measured.

Assuming an infinitely large sample (practically a sample with the length larger than 5s
and the width larger than 2s, where s is the spacing between neighbouring needles of the
four-point probe system) with a laterally uniform sheet resistance, the sheet resistance
can be obtained from the voltage and current readings. If the layer thickness t is much
smaller than the probe spacing s, the sheet resistance is given by [Trapp 1980]:

3.5 ( ) O =
I
V
R
sheet
2 ln
t

3.8.2 Curve tracer

A Tektronix 370 programmable curve tracer is used to obtain an I-V curve over a wide
voltage range. This tracer is particularly helpful for checking if a given metal-
semiconductor contact is ohmic or rectifying. However, this machine only provides
workable two-point measurements. Therefore, a four-point measurement station was set
up in the course of this thesis to enable reliable measurements on samples with low
contact resistance.

3.8.3 Kelvin sense measurement setup

Four-point measurements (two probes for applying the current and two probes for
measuring the voltage) can also be called Kelvin sense measurements to avoid
57
confusion with the four-point probe tester discussed in Section 3.8.1. The series
resistance of a typical two-point I-V measurement setup is generally about 1 when
using two palladium probes on a highly conductive sample. This extra series resistance
is a parasitic effect that causes severe problems when measuring samples having a low
total resistance. An example for this is given in Figure 3.20. Therefore, a Kelvin sense
measurement set-up is crucial for accurate measurements of contact resistances. It
applies a constant current via one needle pair and measures the potential next to each
current-carrying needle with a separate needle. Therefore, if the current is plotted vs.
the potential difference (voltage) measured by the second needle pair, an I-V curve is
obtained (upper curve in Figure 3.20) that is free of the parasitic effect caused by the
contact resistance between the current-carrying needle and the sample. Using this
approach, lower contact resistances can be measured than with a two-point I-V tester.
Figure 3.21 shows photos of the Kelvin sense measurement set-up used in this thesis.

0.0E+00
2.0E-04
4.0E-04
6.0E-04
8.0E-04
1.0E-03
1.2E-03
0.0E+00 1.0E-01 2.0E-01 3.0E-01 4.0E-01 5.0E-01
Voltage(V)
C
u
r
r
e
n
t
(
A
)
2point probe measurement
Kelvin Sense measurement
Linear (Kelvin Sense measurement)
Linear (2point probe measurement)

Figure 3.20: Comparison of I-V curves measured on the same sample with
two different measurement methods.

The setup has the following main components (see Figure 3.21):

58
- The shading canvas is used to block the room light. However, when measuring a
sample with a heavily doped layer and with tiny exposed area (micron scale), the
shading canvas is not necessary.
- Advantest is a current/voltage generator as well as a voltage/current monitor. It
is the core part of the system for providing reliable Kelvin sense measurements.
It can perform an I-V scan over a wide current/voltage range. Advantest can be
operated manually or numerically by Darkstar (a Labview program, installed in
the computer behind the microscope). Manual operation gives more accurate
voltage measurements.
- The size of the patterns is often smaller than 10 m. Therefore, a microscope
and a light source are indispensable.
- Voltage probes with sharp tips (diameter ~5 m) are mounted on two black
micro-positioners. These are essential for a precise positioning of the probes.

Shading Canvas
Advantest
Lamp
Microscope
Darkstar
Measurement Station

(a)

59
Lamp
Microscope
Voltage Probes
Current Probes
Sample

(b)

Figure 3.21: (a) Photo of the Kelvin sense measurement setup used in this
thesis; (b) Detailed view of the current and voltage probes of the set-up.

60

4 Contact resistance results on sc-Si
wafer samples
4.1 Motivation

Due to their well-behaved nature (no grain boundaries, laterally uniform sheet
resistance), singlecrystalline silicon wafers are excellent test vehicles for verifying the
TLM and CTLM structures established at UNSW in the course of this thesis. Such a
verification is important before applying the methods to less well behaved samples such
as thin-film materials.

4.2 Sample preparation

The experiments reported in this Chapter were performed on samples that were cut off
from p-type and n-type singlecrystalline Si (sc-Si) wafers with a diameter of 4 inch. The
surfaces of the n-type wafers were heavily boron-diffused while those of the p-type
wafers were heavily phosphorus-diffused, forming a p-n junction below each surface.
The diffusion processes were conducted at high temperature in tube furnaces, using
atmospheric pressure. Upon wet-chemical removal of the surface oxides, the sheet
resistance of all diffused layers was measured and found to be about 120 O/sq,
regardless of the position on the wafers. Each wafer was then cut into four pieces of
equal size. Figure 4.1 shows the cross-sectional structures of the samples at this stage.

Formation of the contact resistance structures started with a piranha clean, followed by a
dip in 5% HF to remove any oxides. The resulting surfaces were thus hydrophobic. The
samples were then rinsed for 10 min in DI water, followed by drying with a nitrogen
gun. The samples were then immediately loaded into the evaporator chamber (no
loadlock). The chamber was then pumped down during about 60 minutes to a pressure
61
of about 10
-5
Torr. Then 300-500 nm of aluminium was evaporated onto the samples,
using resistively heated evaporation from a tungsten boat. The evaporation rate was
30-50 /s. The TLM/CTLM structures were then photolithographically patterned. A
mesa etch done by plasma etching (PE) was then conducted to constrain the current in
the silicon to only flow directly between the contact pads (not necessary for CTLM
patterns).

p
+
p
+
n
-

(a)

n
+
n
+
p
-

(b)

Figure 4.1: Structures of the investigated sc-Si wafer samples (not to scale).
(a) n-type wafer with p
+
surface diffusions; (b) p-type wafer with n
+
surface
diffusions.

4.3 Results

The contact resistances were measured before and after baking the samples at room
temperature (~300 K), using the Kelvin sense measurement system presented in Section
3.8.3. Different transmission line models were applied, and different annealing
processes are compared. All annealing processes were conducted in a nitrogen-purged
oven. All fabricated contacts were found to be ohmic. The specific contact resistance
values obtained are compared with values reported in the literature.

4.3.1 Boron-diffused sc-Si surfaces

The specific contact resistances were measured on three p
+
diffused sc-Si samples using
the improved variable gap structure and the circular TLM structure, before and after

62
baking at 250C for 30 min in a N
2
purged oven. Then the TLM/CTLM patterns were
stripped, followed by the sheet resistance profiling technique to determine the surface
doping concentrations.

Figure 4.2 shows the resulting characteristic curves (fitted lines) for (a) the variable gap
structure (linear fitting) and (b) the circular TLM structure (non-linear fitting). Figure
4.2 indicates that the mathematical models fit the experimental results very well, which
also implies uniform contact properties and uniform sheet resistance of the wafers. The
measurements in Figure 4.2 are all from the same sample. The results obtained on the
other two samples are similar and therefore not shown here.

0.0E+0
5.0E+0
1.0E+1
1.5E+1
2.0E+1
2.5E+1
3.0E+1
3.5E+1
-20 0 20 40 60 80 100 120 140 160
d(um)
A
V
(
m
V
)
DV_i
DV_i,fit

(a)

0.0E+0
5.0E+0
1.0E+1
1.5E+1
2.0E+1
2.5E+1
3.0E+1
-20 0 20 40 60 80 100 120 140
d(um)
A
V
(
m
V
)
DV_i
DV_i,fit

(b)

Figure 4.2: The measurement results and characteristic curves of
(a) the variable gap TLM structure (linear fitting) and (b) the
circular TLM structure (non-linear fitting). These results were
measured on a sc-Si sample with p
+
diffused surfaces.

63
All experimentally obtained specific contact resistance values (before and after baking)
are depicted in Figure 4.3 as a function of the surface doping level. The data points
represent the average of the values measured for different currents (ranging from 50 A
to 5000 A). The error bars represent the 95% confidence interval. As can be seen,
thermal annealing improves the specific contact resistances by about an order of
magnitude. The measured values lie well within the experimental band of values
reported in the literature (dashed region). This verifies that the transmission line models
set up at UNSW in the course of this thesis can reliably measure the specific contact
resistance of Al/p
+
-Si contacts.

4x10
18
6x10
18
8x10
18
10
19
2x10
19
4x10
19
10
-7
10
-6
10
-5
10
-4
VG
CTLM
VG
VG
CTLM
VG
F7-7-1
F7-7-2
F7-7-3
F7-7-1
F7-7-2
F7-7-3
Reported range
Surface doping density (atoms/cm
3
)
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e

(
O
-
c
m
2
)
c
before baking
c
after baking
c
experimental range
(after Schroder & Meier 1984)

Figure 4.3: Specific contact resistances measured on three boron-diffused c-Si
wafer surfaces with the variable gap structure (VG) and the circular TLM
structure (CTLM), before and after baking at 250C for 30 minutes. The error
bars
*
represent the 95% confidence interval. The corresponding sample name is
shown under each data point. The dashed region represents the range of
experimentally determined
c
values of Al/p-Si contacts reported in the literature
(after Schroder & Meier 1984).

*
All error bars shown in this thesis represent 1.96 standard deviations of the corresponding
measurements and thus represent the 95% confidence interval.
64
4.3.2 Phosphorus-diffused sc-Si surfaces

The specific contact resistance measurements of Al/n
+
-Si contacts (before and after
baking) are presented in Figure 4.4. The data points represent the average of the values
measured for different currents (ranging from 1 mA to 100 mA). The error bars again
represent the 95% confidence interval. The surface doping concentrations were
determined using the sheet resistance profiling technique. As can be seen, the improve-
ment arising from thermal annealing is much less than in the case of Al/p
+
-Si contacts.
Possible reasons for this are discussed in Section 4.4. The specific contact resistances
measured on Al/n
+
-Si contacts again lie well within the band of values reported in the
literature (dashed region in Figure 4.4). Moreover, the measured specific contact
resistances are below 110
-6
cm
2
and exhibit relatively small error bars. These are
clear indications that the measurement models and measurement system (Kelvin Sense)
are functioning well and reproducibly.

10
20
10
21
10
-8
10
-7
10
-6
10
-5
Reported range
Surface doping density (atoms/cm
3
)
S
p
e
c
i
f
i
c
c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e

(
O
-
c
m
2
)
c
before baking
c
after baking
c
experimental range
(after Schroder & Meier 1984)

Figure 4.4: Specific contact resistances measured on phosphorus-diffused Si wafer
surfaces using the circular TLM structure, before and after baking at 250C for 30
min. The error bars represent the 95% confidence interval. The error bars of the
unbaked samples are not shown in the graph. The dashed region represents the
band of experimentally determined
c
values of Al/n-Si contacts reported in the
literature [Schroder & Meier 1984].

65

4.3.3 The influence of baking time and temperature

In the early stages of this thesis, most samples were baked sequentially (sequential
baking) while some were baked only once. In order to distinguish between the effects
of the baking time and baking temperature, two types of annealing experiments were
conducted on p
+
diffused Si wafer samples. These small samples were cut from the
samples that were cut from the 4-inch wafers. Due to the good lateral uniformity of the
p
+
diffusion across the 4-inch wafers, the small samples all had essentially the same
surface properties. Thus, the lateral deviation of the doping density across the entire
sample produces a negligible error in the contact resistance.

In the first experimental run, three p
+
diffused samples were used. Each bake had a
duration of 30 minutes. The first sample was baked at 150C, then at 200C, and then at
250C (sequential baking). The second was baked at 200C, while the third was baked
at 250C. As can be seen from Figure 4.5, a single 30-min bake at 250C gives better
contact resistance than a 150/200/250C sequential bake. Thus, for a fixed bake duration
of 30 minutes, sequential baking does not seem to be advantageous compared to a single
bake. As shown in Chapter 3, the contact edges are exposed to the air. The edges are the
critical part to determine the contact resistance rather than the whole contact area. Both
the aluminium and the silicon at the contact edges can be slightly oxidized when
cooling the sample at the air after baking. And the sequential baking has more cooling
times than a single bake. Therefore, sequential baking improves the contact slightly less
than a single bake.

66
0 150 200 250
1E-6
1E-5
1E-4
1E-3
110.6
108.5
105.5
105.9
112.4
115.8
104.7
129.6
No Baking
Sequential Baking
200C Baking
250C Baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
Baking temperature (C)

Figure 4.5: Al/Si specific contact resistance of three p
+
diffused Si wafer samples
after baking under different baking conditions. The sheet resistances (in /) are
shown next to each data point.

The above finding is further supported by the second experimental run where three p
+

diffused samples were baked at a fixed temperature of 250C. The first was baked for
30 min, the second for 60 min, and the third for 90 min. The contact resistance results
are presented in Figure 4.6. Considering the slightly different starting values for
c
, the
specific contact resistance values after the bake reveal that a bake duration of 30
minutes is fully sufficient at 250C.

67
0 30 60 90
1E-7
1E-6
1E-5
1E-4
127.8
127.0
117.5
112.7
129.3
114.6
90 m Baking
60 m Baking
30 m Baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
Baking time (minute)

Figure 4.6: The specific contact resistance of three p
+
diffused Si wafer samples as
a function of the baking time at 250C. The sheet resistances (in /) are shown
next to each data point.

Combining the results from both experimental runs, the conclusion can be drawn that
the baking temperature is the dominant parameter for the specific contact resistance of
Al contacts on heavily doped singlecrystalline silicon surfaces. The effect of the baking
time on the contact resistance saturates for annealing times above about 30 minutes.
However, sequential baking can be helpful for samples with poor lateral doping
uniformity, as shown in Chapter 5.

4.4 Discussion and conclusions

In this chapter, Al contacts on n
+
and p
+
diffused singlecrystalline Si wafer surfaces
were investigated. All TLM structures were found to give specific contact resistance
values that lie well within in the band of experimental values reported in the literature.
Baking at low temperatures (150-250C) had little effect on the contact resistance of n
+

samples, whereas it improved the contact resistance massively for p
+
samples.
The reason for this different behaviour of p
+
and n
+
samples has to do with the fact
that real silicon surfaces, even if carefully cleaned and HF dipped, have a thin (< 10 )

68
native oxide layer on them [SNF 2007]. If an Al film is evaporated onto this thin oxide
layer (tunnel oxide), the structure shown in Figure 4.7(a) results. It is well known in
the literature [Blakers & Green 1981] that the resulting as-fabricated (i.e., not baked)
MIS contact has good ohmic properties if the silicon is n-type but poor ohmic properties
if the silicon is p-type doped. Thus, baking will have a negligible effect on the ohmic
properties of Al/n
+
-Si contacts, a behaviour confirmed by the results in Figure 4.4.

heavily doped Si
SiO
x
Increasing thermal budget
Al
SiO
x
Al
AlO
y
SiO
x
Al
AlO
y
<

1
0

heavily doped Si heavily doped Si

As metallised

(a) (b) (c)

Figure 4.7: Cross-sectional view showing structural changes of Al/SiO
x
/Si contacts due
to increasing thermal budget. (a) Al/(SiO
x
/)Si contacts as metallised; (b) Si oxides
converting into Al oxides during thermal annealing; (c) Al spikes through the interface
layers and into the silicon substrate due to higher baking temperature (~300C)
[Bierhals 1998]. (not to scale)

The reason why Al/oxide/n
+
-Si contacts are ohmic is the reduction of the band bending
and the Schottky barrier height at the silicon surface due to a sheet of fixed positive
charge within the oxide, and the passivation of interface states at the Si-SiO
x
interface
which reduces the negative charge trapped at this interface [Sze & Ng 2007]
[Sritharathikhun. 2007].

To understand why baking helps p-type contacts, it is necessary to consider the
structural changes that occur in Al/oxide/silicon contacts during baking [Bierhals 1998].
These structural changes are schematically shown in Figure 4.7. They are due to the fact

69

that Al is more reactive (less noble) than Si, leading to the conversion of the upper
regions of the SiO
x
film into AlO
y
:

4.1 4Al + 3SiO
2
2Al
2
O
3
+ 3Si

If the baking is continued for a sufficient amount of time (increased thermal budget), Al
spikes will start to locally penetrate into the AlO
y
and SiO
x
layers, see Figure 4.7(b).
For even higher thermal budget the Al spikes will eventually penetrate through the
oxide layer into the underlying silicon material. The Al spikes locally shunt the
insulating layers and provide good ohmic contact regions to the underlying heavily
doped silicon. In the non-spiked regions the device has poor ohmic properties due to the
band bending at the semiconductor surface caused by workfunction differences between
Al and Si and the fixed oxide charge [Sritharathikhun 2007].

In conclusion, the contact resistance measurements performed in this chapter on heavily
doped singlecrystalline silicon surfaces demonstrate that the transmission line models
set up at UNSW in the course of this thesis can reliably measure the specific contact
resistance of Al on both n
+
and p
+
doped silicon. The dominant parameter in the baking
process for the contact resistance is the baking temperature, whereby hotter is better.
Baking has negligible effects on the ohmic properties of Al on n
+
-Si surfaces, however,
the specific contact resistance of Al on p
+
-Si surfaces improves massively (factor 10 or
more) due to baking at sufficiently high temperature and for sufficiently long times. As
the aim of this chapter is to preliminarily test the contact resistance measurement system
before applying this technique to the different poly-Si thin-film solar cells investigated
at UNSW, and due to the fact that the performance of those cells degrades after
annealing at higher temperatures (> ~300C) [Terry 2007], the effect of baking at
temperatures higher than 250C is not systematically investigated in this Chapter.
70

5 Contact resistance results on uniformly
doped poly-Si films on glass
5.1 Motivation

Uniformly doped evaporated polycrystalline silicon thin-films on glass (i.e., no p-n
junctions) are well suited to investigate the contact resistance because of their simpler
structure and better surface quality (no hydrogenation-induced damage) as compared to
completed solar cells. The results can be a good reference when moving the scope to
completed solar cells. As Al/Si contacts on singlecrystalline wafers are well studied and
understood, comparing the results presented in this Chapter to the results based on sc-Si
reported in the literature can give a good insight into the general features of aluminium
contacts on evaporated silicon material for solar cell application. All TLM structures
which were verified in Chapter 4 (except the conventional ladder network model) were
employed in this Chapter.

5.2 Sample preparation

All experiments reported in this Chapter were performed on uniformly doped SPC
poly-Si thin-films. The fabrication sequence is as follows: First, a phosphorus or
boron-doped a-Si film (thickness in the range of 1001000 nm) was evaporated onto
SiN-coated glass substrates (planar or textured) using e-beam evaporation. Then the a-Si
film was crystallised by SPC (solid-phase crystallisation) in a nitrogen-purged furnace
at 600C for 48 hours [Song 2006]. Most of the samples then received a rapid thermal
anneal (RTA) at 900C for 4 minutes to activate dopants and reduce the density of point
defects [Terry 2007]. RTA also flattens the glass substrates which can deform signifi-
cantly during the SPC process. The importance of having a flat substrate for TLM
patterning was discussed in Chapter 3. The samples did not receive any hydrogenation
71

treatment. All films have fairly uniform thickness (the deviations from the average value
are < 10%). The doping density is above 110
18
cm
-3
for all films (both p-type and
n-type). To quantify the active doping level, the thickness of each poly-Si film was
measured via spectroscopic measurements and from this together with the measured
sheet resistance, the films electrical resistivities were determined. For heavily doped
poly-Si thin-films, the active doping concentration is only slightly higher than that of
singlecrystalline Si wafers with the same resistivities. The doping ratio of these two
materials varies less than a factor of 2 [Seto 1975, Monkowski 1979].

Formation of the contact resistance structures started with a piranha clean, followed by a
dip in 5% HF to remove the surface oxide. The resulting surfaces were found to be
hydrophobic. The samples were then rinsed for 10 min in DI water, followed by a blow
dry in N
2
gas. Then, the samples were immediately loaded into the evaporator chamber
(no loadlock). The chamber was pumped down during about 60 min to a pressure of
about 10
-5
Torr. A 300-500 nm thick Al film was then evaporated onto the samples at
30-50 /s, using resistively heated evaporation from a tungsten boat. Prior to the Al
evaporation, some of the n-type poly-Si samples were baked in an atmospheric oven at
150C for 30 min in order to form an Al/SiO
x
/n
+
poly-Si contact structure. Finally, the
TLM patterns (conventional/improved variable gap, improved ladder network, circular
TLM) were made via photolithographic structuring of the Al film. A mesa etch done by
plasma etching (PE) was then conducted to constrain the current in the silicon to only
flow directly between the contact pads (not necessary for CTLM patterns).

5.3 Results

All contact resistance measurements were performed at room temperature (~300 K),
before and after baking the samples by using the Kelvin sense measurement system
described in Section 3.8.3. In order to ensure good measurement precision, the current
range used for each measurement covered three orders of magnitude, within the range of
5 A to 100 mA. All transmission line models discussed in Chapter 2, except the
conventional ladder network model, were applied. The long-term stability and the
thermal annealing effect of Al/poly-Si contacts are studied. Moreover, the specific
72
contact resistance values of SPC poly-Si films are compared to the reported
experimental values obtained on sc-Si wafers and LPCVD-grown poly-Si films, and
analysed in terms of doping density and Schottky barrier height. Note that the term
poly-Si used in this thesis refers to evaporated SPC poly-Si films fabricated at UNSW.
Other technologies used are explicitly mentioned.

Al/Si contacts have been reported to be long-term stable [Ponpon & Siffert 1978] at
room temperature, provided the Al film is thick enough (> 100 ) to prevent the
diffusion of atmospheric oxygen through the Al. To verify this behaviour for Al/poly-Si
contacts, the specific contact resistance of several baked samples (both p
+
and n
+

poly-Si) were re-measured after 3 months of storage in air. As can be seen from Figure
5.1, the contact resistance of all samples was stable.

0 3
10
-5
10
-4
10
-3
Months of storage
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
Al/SiO
x
/n-Si Al/n-Si 1 Al/n-Si 2 Al/p-Si

Figure 5.1: The measured contact resistance of baked Al/poly-Si samples before and
after storage in air for 3 months. Prior to the first measurements, the samples were
baked at 250C for 30 minutes. The maximum error bar of each set of measurements
is shown in the legend.

73
5.3.1 Boron-doped Si films

A. Evidence of ohmic contact

All p
+
doped poly-Si films were metallised without intentionally growing an oxide layer
on the surface. Figure 5.2 shows an example of I-V measurements taken on two
adjacent Al bars/pads/circles separated by a resistive p-type poly-Si film. The contact
was not baked. As can be seen, the I-V curve is linear over the entire measured voltage
range of 3.5 V, showing that Al makes good ohmic contact to p
+
doped poly-Si films
without baking.

R
2
=1
-1.E-02
-8.E-03
-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
8.E-03
1.E-02
-4 -3 -2 -1 0 1 2 3 4
volts
a
m
p
s

Figure 5.2: A typical measured I-V curve between two Al contacts
on p
+
doped poly-Si (resistivity = 25.5 mOcm). The measurement
was performed on as-metallised (i.e., non-baked) samples.

B. The effect of thermal annealing on the specific contact resistance

Figure 5.3 shows the improvement of the Al/p
+
poly-Si contact resistance due to
sequential baking at increasing temperature in a N
2
-purged oven. The duration of each
bake was 30 min. The number next to each data point is the electrical resistivity of the
poly-Si film in units of mOcm. It can be seen that baking improves the specific contact
resistance by more than one order of magnitude. Good contact resistance values of

74
about 110
-4
Ocm
2
were obtained after sufficient baking. However, the effect of
annealing on the specific contact resistance saturates for annealing temperatures higher
than 250C. This is due to the fact that most of the silicon oxide film that exists on the
Si surface prior to the aluminium evaporation is consumed by Al during
low-temperature baking (< 250C). This oxide film is detrimental to Al/p-Si contacts as
it contains fixed positive charges, as discussed in Chapter 4 [Sze & Ng 2007]. Because
intimate contacts are already formed, additional baking at 300 and 350C does not
further improve the specific contact resistance of the Al/p
+
poly-Si contact.

0 100 150 200 250 300 350 400
10
-5
10
-4
10
-3
10
-2
26.39
27.27
26.73
25.16
24.75
No Baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e

c

(
O
-
c
m
2
)
Annealing temperature (C)

Figure 5.3: The specific contact resistance of Al/p
+
poly-Si contacts during successive
bakes at increasingly hotter temperature. The duration of each bake was 30 min. The
electrical resistivities of the films are also shown beside the data points (in mOcm).
The error bars represent the 95% confidence interval.

C. Doping density dependence of the specific contact resistance

Figure 5.4 illustrates the relation between the silicon resistivity and the specific contact
resistance of Al/p
+
poly-Si contacts (before and after a single bake at 250C for 30 min).

75
The data points (all symbols) represent the experimental measurements on evaporated
p
+
doped poly-Si films. Only a random selection of samples was baked after the first
contact resistance measurement. Note that the resistivity decreases with increasing
doping level. For heavily doped poly-Si, the active doping concentration is only slightly
higher than that of singlecrystalline silicon with the same resistivity. As can be seen, the
specific contact resistance drops dramatically with reducing Si resistivity (increasing
doping level). Generally, baking reduces
c
by more than one order of magnitude on
average, which is in good agreement with the baking experiments on p-type contacts
presented in Figure 5.3 and Chapter 4.

100 10 1 0.1
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
c
of Al/p
+
poly-Si contact before baking
c
of Al/p
+
poly-Si contact after baking
c
of Al/p
+
poly-Si contact
before baking (O contaminated)
c
of Al/p
+
poly-Si contact
after baking (O contaminated)
Experimental
c
range of Al/p
+
sc-Si
contact (after Schroder & Meier 1984)
Experimental
c
range of Al/p
+
poly-Si
contact (after Ford 1983)
Doping level (cm
-3
)
10
21
10
20
10
19
10
18
Resistivity of Si layer (mO-cm)
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 5.4: Measured specific contact resistance of Al/p
+
poly-Si contacts versus Si
resistivity at room temperature (~300 K), before and after a single bake at 250C for
30 min (not all samples were baked). The two parallel dot-dashed lines outline the
trend of these measurements. The band of experimental
c
values of Al/p-Si contacts
on sc-Si wafers (dash-hatched area) reported by Schroder and Meier [1984] and
Al/p-Si contacts on poly-Si (dot-hatched area) reported by Ford [1983] are also
presented. The doping level axis shown on the top is produced from the corresponding
sc-Si resistivity. For heavily doped poly-Si, the active doping concentration is higher
than the one of sc-Si with the same resistivity by a factor of less than 2. For the sake of
clarity, no error bars are shown for the experimental data points. Representing 95%
confidence interval, the error of each data point is generally 40%.

76

In Figure 5.4, the results with triangle symbols (filled and empty ) are outside the
main data region (defined by the two parallel dash-dotted lines) of measured values.
These results represent samples which were very likely heavily oxygen-contaminated
during a-Si deposition and/or the rapid thermal annealing process. One supporting
evidence for this interpretation is that, after dipping these samples in 5% HF for a
sufficient time in order to remove the surface oxide before metallisation, the surfaces
were not completely hydrophobic. The normal samples did not show this behaviour.
Moreover, these abnormal samples were all fabricated in one experimental run. Oxygen
contamination is always detected in the UNSW thin-film solar cells through SIMS
measurements [Terry 2007]. The oxygen atom density near the surface can even be one
to two orders of magnitude higher than the intended density of dopant atoms. Oxygen is
known to be able to act as an n-type dopant in silicon and hence introduces donor states
at the silicon surface. It is noted that only a certain fraction (<< 50%) of the existing
oxygen atoms in silicon show donor-like behaviour [Kimerling & Benton 1981,
Ourmazd 1984]. Under thermal equilibrium, these donor states are positively charged
resulting in heavier silicon band bending at the interface. A high interface state density
may cause the silicon Fermi level at the surface to be pinned [Rhoderick 1988, Sze &
Ng 2007]. This effect, together with the heavier band bending, causes the Schottky
barrier height of p-Si to be increased. Both the higher Schottky barrier height and the
heavier surface band bending (depletion conditions) cause poorer ohmic properties than
in the cases of low O contamination. Therefore, as can be seen in Figure 5.4, to reach
the same specific contact resistance level as for the normal samples (lightly O
contaminated) (squares ), the heavily O-contaminated samples (triangles ) need
the resistivities to be about 5 times lower (higher doping level). Thermal annealing may
eliminate the fixed positive charge due to the SiO
x
interfacial layer as discussed
previously, but cannot annihilate the positive charges arising from O contamination.
Therefore, thermal annealing at 250C for 30 min does not offer a significant improve-
ment of the specific contact resistance for heavily O contaminated p
+
poly-Si samples.

Another interesting finding from Figure 5.4 results from a comparison of the
experimental specific contact resistance values of Al/p-Si contacts made from i)
evaporated poly-Si (lightly O contaminated, squares ); ii) LPCVD poly-Si
(dot-hatched region) [Ford 1983]; iii) sc-Si (dash-hatched region) [Schroder & Meier
77

1984]. In the figure, the two parallel dash-dotted lines define the measurement range for
normal category i) samples and exhibit the trend of the specific contact resistance versus
the silicon resistivity (doping density). The dot-hatched region shows the trend of
c
for
Al contact on LPCVD-fabricated poly-Si, and the dash-hatched region shows the trend
of
c
for Al contact on sc-Si. The LPCVD poly-Si was reported to be deposited on a
SiO
2
layer grown on a <100> n
-
sc-Si wafer and then doped via ion implantation. Then,
a 10 thick Al film (with a Si content of 1.5%) was evaporated onto the sample. The
samples were then annealed at 450C for 20 min in forming gas. Note that the silicon
was added to the Al to minimise silicon diffusion into the aluminium film during post-
metallisation annealing. This Si content has negligible impact on the specific contact
resistance if a sufficiently hot and long annealing process is conducted [Faith 1982].

It can be seen in Figure 5.4 that
c
of Al/ LPCVD poly-Si contacts is slightly higher than
that of Al/sc-Si contacts at high doping levels, but the slopes of their trends are similar.
The higher
c
is due to the granular nature and higher tunnelling effective masses of
poly-Si [Ford 1983]. However, the trend of
c
of Al/evaporated poly-Si contacts (region
defined by the two parallel dash-dotted lines) exhibits a much steeper slope than for the
other two contacts. In other words,
c
drops much more quickly with decreasing
resistivity than for the other two contact types. The cross-over occurs at a Si resistivity
of about 10 mcm. Thus, the specific contact resistance of evaporated p-type poly-Si is
better than the one of LPCVD poly-Si and sc-Si if the silicon is more heavily doped
(> ~510
18
/cm
3
). Furthermore, it can be also seen in Figure 5.4 that
c
of Al/poly-Si
contacts cover a larger range than for Al/sc-Si contacts. This is believed to be due to the
random crystal orientations of poly-Si films crystallised via SPC [Song 2006].

So far, to the best of the authors knowledge, there is no solid model to explain the
behaviour of Al/poly-Si contacts. Furthermore, Figure 5.4 reveals that the evaporated
SPC poly-Si films made at UNSW behave differently compared to poly-Si samples
reported in the literature. For relatively lowly doped silicon (< ~110
19
/cm
3
),
c
of
Al/evaporated poly-Si contacts is higher than for the other two types of contacts
considered in the figure. This difference is believed to be due to the higher Schottky
barrier height which dominates the specific contact resistance for metal contacts on
lowly or moderately doped silicon, where the dominant current transport mechanism is
78

thermionic emission over the barrier [Sze & Ng 2007]. Grain boundaries can increase
the barrier height because interface states and depletion layers at grain boundaries
produce variable potential barriers to carrier flows [Monkowski 1979]. The grain size
for evaporated solid phase crystallised poly-Si is 0.8-1.5 m [Song 2006]. In more
highly doped region (> ~110
19
/cm
3
),
c
of Al/poly-Si contacts is found to be lower than
that of the other two types of contacts. The potential barrier which arises from grain
boundaries reduces significantly. Furthermore, it is speculated that evaporated p
+

poly-Si has lower tunnelling effective mass and hence higher effective Richardson
constant than both LPCVD p
+
poly-Si and p
+
sc-Si, which in turn reduces the electron
tunnelling resistance. The possible reason is as follows. If the silicon surface is heavily
or degenerately doped, the dominant current transport mechanism is free carrier
tunnelling through the depletion region whose width is inversely proportional to the
surface doping level [Sze & Ng 2007]. Decreasing the tunnelling resistance will
definitely increase the tunnelling current. More detailed modelling and discussion are
given in Section 5.4.

5.3.2 Phosphorus-doped Si films with and without SiO
x
interlayer

A. Evidence of ohmic contact

Figure 5.5 shows an example of I-V measurements taken on two adjacent Al
bars/pads/circles separated by a resistive n-type poly-Si film. The contact was not baked.
As can be seen the I-V curve is linear over the entire measured voltage range of 3.5 V,
showing that Al makes good ohmic contact to n
+
doped poly-Si films without baking.
Al/SiO
x
/n
+
poly-Si contacts were also found to be ohmic before and after baking.

79
R
2
=1
-1.E-02
-8.E-03
-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
8.E-03
1.E-02
-4 -3 -2 -1 0 1 2 3 4
volts
a
m
p
s

Figure 5.5: A typical measured I-V curve between two Al contacts on
n
+
doped poly-Si (resistivity = 26.2 mOcm). These measurements were
performed on as-metallised (i.e., non-baked) samples.

B. The effect of thermal annealing on the specific contact resistance

Figure 5.6 shows the improvement of the Al/n
+
poly-Si contact resistance due to
sequential bakes at increasing temperature in an N
2
-purged oven (sequential baking).
The duration of each bake was 30 min. It can be seen that baking improves the contact
resistance by less than an order of magnitude. Good contact resistance values of about
110
-4
Ocm
2
are obtained after sufficient baking. However, the improvement is not as
significant as in the case of Al/p
+
poly-Si films (see Figure 5.3). This finding agrees
well with that obtained on sc-Si in Chapter 4. The reason for this behaviour has been
discussed in detail in Chapter 4. Baking at 300C in a N
2
-purged oven is found
detrimental to Al/n
+
poly-Si contacts, which agrees with the findings on sc-Si material
reported in the literature [Faith 1983]. Being a p-type dopant in silicon, Al introduces
ionised acceptor atoms at the n-Si surface during the annealing process, which may even
lead to an Al/p
+
-Si/n-Si contact structure [Finetti 1980]. Baking at 300C may not yet
cause a heavily doped p-type poly-Si interfacial layer, but will definitely deteriorate
Al/n
+
poly-Si contacts and hence increase the specific contact resistance.

80
0 150 200 250 300
710
-5
10
-4
10
-3
1.68
1.70
1.69 1.66
1.66
1.64
1.57
1.61
1.50
1.56
No Baking
Al/n
+
poly-Si_sample1
Al/n
+
poly-Si_sample2
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
Baking temperature (C)

Figure 5.6: The specific contact resistance of Al/n
+
poly-Si contacts during sequential
bakes at increasing temperature. The duration of each bake was 30 min. The
resistivities of the films are also shown beside the data points (mOcm). The error bars
represent the 95% confidence interval.

The thermal annealing experiments were also conducted on Al/SiO
x
/n
+
poly-Si contacts
.
The baking process is again the sequential baking. The duration of each bake was 30
minutes. As can be seen in Figure 5.7, there is no significant improvement due to
baking up to the temperatures of 200C. However, the specific contact resistance drops
abruptly during baking at 250C, which implies that at this temperature aluminium
penetrates into the SiO
x
interfacial layer and approaches the optimum distance from the
silicon interface where the remaining SiO
x
interfacial layer is thin enough to be easily
tunnelled by the electrons while thick enough to maintain a high density of fixed
positive charge (which helps n-type contacts). Finally, baking at 300C increases the
specific contact resistance. This is due to the elimination of the beneficial Si oxide
interlayer and the interaction of Al and n-type

poly-Si as discussed above.

The compound SiOx is stoichiometric when x = 2 and nonstoichiometric in all other cases.
81
0 150 200 250 300 350
10
-5
10
-4
10
-3
1.76
1.82
1.55
1.58
1.60
2.04
1.67
1.64 1.61
1.84
1.73
1.53
Al/SiO
x
/n
+
poly-Si_sample1-2
Al/SiO
x
/n
+
poly-Si_sample2-2
No Baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

(a)

0 150 200 250 300 350
10
-6
10
-5
10
-4
10
-3
2.08 2.12
2.09
2.07
2.05
2.02
1.66 1.64
1.66
1.65
1.65
1.63
2.48
2.68
2.17
2.07
2.03
2.04
Al/SiO
x
/n
+
poly-Si_sample1-1
Al/SiO
x
/n
+
poly-Si_sample2-1
Al/SiO
x
/n
+
poly-Si_sample3-1
No Baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

(b)

Figure 5.7: The specific contact resistance of Al/SiO
x
/n
+
poly-Si contacts during
sequential bakes at increasing temperature. The duration of each bake was 30
minutes. The resistivities of the films are also shown beside the data points (mOcm).
The error bars represent the 95% confidence interval. (a) Samples with TLM patterns
of smaller dimensions; (b) Samples with TLM patterns of larger dimensions. The
measurement results are not affected by the dimensions of the TLM pattern used.

82

Comparing Figure 5.6 and Figure 5.7 it can be seen that, for a given Si resistivity,
Al/SiO
x
/n
+
poly-Si contacts have much lower specific contact resistance than Al/n
+
poly-Si contacts, after baking at sufficiently high temperature. This indicates that
growing a thin native silicon oxide layer before Al deposition improves Al/n-type
poly-Si contacts significantly.

C. Doping density dependence of specific contact resistance

Figure 5.8 illustrates the relation between the silicon resistivity and the specific contact
resistance (before and after a single bake at 250C for 30 min) for Al/n
+
poly-Si
contacts as well as Al/SiO
x
/n
+
poly-Si contacts. The data points (all symbols) represent
the measurements on evaporated n
+
doped poly-Si films. Only a random selection of
samples was baked after the first contact resistance measurement. As can be seen, the
specific contact resistance drops by more than three orders of magnitude if the Si
resistivity decreases by a factor of about 5. A thin SiO
x
interfacial layer was formed on
some of the samples (diamonds ) by baking in an atmospheric oven at 150C for 30
minutes just before the Al evaporation step. Generally, baking slightly reduces
c
for
contacts without SiO
x
interfacial layer () but significantly reduces
c
for contacts with
SiO
x
interfacial layer (). This finding agrees well with the results of the baking
experiments presented previously in this Chapter and in Chapter 4. Evidently, after
sufficient baking, a thin SiO
x
interfacial layer improves Al contact on n
+
doped poly-Si
contact drastically.

83
100 10 1 0.1
10
-6
10
-5
10
-4
10
-3
10
-2
Doping level (cm
-3
)
10
21
10
20
10
19
10
18
10
17
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 5.8: Measured specific contact resistance of Al/n
+
poly-Si and Al/SiO
x
//n
+
poly-Si contacts versus the Si resistivity at room temperature (~300 K), before and
after a single bake at 250C for 30 min (not all samples were baked). The two
parallel dot-dashed lines outline the trend of these measurements. The band of
experimental
c
values of Al/n-Si contacts on sc-Si wafers (dash-hatched area)
reported by Schroder and Meier (1984) and Al/n-Si contacts on poly-Si (dot-hatched
area) reported by Ford (1983) are also presented. The doping level axis shown on
the top is produced from the corresponding sc-Si resistivity. For heavily doped
poly-Si, the active doping concentration is higher than the one of the sc-Si with the
same resistivity by a factor of less than 2. Error bars are omitted for the sake of
clarity. Representing 95% confidence interval, the error of each and data point
is generally 15%; the error of each and data point is generally 30%;the error
of each and data point is generally 70%..

84

In Figure 5.8, the results with triangle symbols (filled and empty ) are outside the
main data region (between the two parallel dash-dotted lines) of measured values.
Similar to some of the results shown in Figure 5.4 (p-type contacts), these results were
obtained from the samples fabricated in one experimental run, which got very likely
heavily oxygen-contaminated during a-Si deposition and/or the rapid thermal annealing
process. As discussed in Section 5.3.1, oxygen introduces positive charges (ionised
donors). Being different from the p-Si case, these positive charges reduce the Schottky
barrier height of Al/n-Si contacts, whose mechanism is similar to the fixed positive
charge introduced by the SiO
x
interfacial layer. Thermal annealing may eliminate the
oxide related fixed positive charge, but cannot annihilate the positive charges arising
from O contamination, as discussed in Section 5.3.1. Therefore, annealing does not
bring those triangle data points back to the main data region. As the result of a lower
Schottky barrier height, heavily O contaminated samples (triangles ) have better
ohmic properties than lightly O contaminated samples (squares ). Thus, these
samples reach the same
c
level with a resistivity that is almost one order of magnitude
higher (i.e., lower doping level) than in the case of samples with low O contamination.

Similar to the presentation in Figure 5.4 (Al/p-Si contacts), the comparison among the
experimental specific contact resistance values of three types of Al/n-Si contacts are
also given in Figure 5.8. They are Al contacts on i) e-beam evaporated n
+
poly-Si
(lightly O contaminated, filled and empty squares , ); ii) LPCVD n-type poly-Si
(dot-hatched region) [Ford 1983], and iii) n-type sc-Si (dash-hatched region) [Schroder
& Meier 1984]. The fabrication process of LPCVD n-type poly-Si is the same as the one
introduced in Section 5.3.1, except that the dopants are phosphorus atoms. Again, in the
figure, the two parallel dash-dotted lines on the right define the range of main normal
measurements of category i) samples (squares ) and exhibit the trend of the specific
contact resistance versus the silicon resistivity (doping density). The trend of Al contact
on n
+
poly-Si fabricated by e-beam evaporation roughly agrees with the one of Al
contacts on LPCVD n
+
poly-Si and n
+
sc-Si. Comparing Al/poly-Si contacts to Al/sc-Si
contacts, the latter has higher
c
in lower doped region and has lower
c
when the
silicon is more highly doped. This result is similar to the one presented in Figure 5.4
(Al/p-Si contacts), and the possible reasons were already given in Section 5.3.1.

85

5.4 Discussion

In order to further understand the behaviour of Al/poly-Si contacts, it is necessary to
discuss their Schottky barrier heights. First of all, the barrier height of the well-studied
Al/sc-Si contacts is briefly reviewed.

The Schottky barrier height is a figure-of-merit of MS contacts. Under ideal conditions
(i.e., no defects at the interface, no interface states, no barrier lowering, no insulator
interfacial layer, no effect from the contacting metal or other anomalies), the Schottky
contact barrier height can be predicted by the Schottky model if the metal work function
m
and semiconductor affinity are known. Figure 5.9 illustrates the band diagrams of
ideal aluminium contacts on (a1) n-Si and (a2) p-Si, as well as the corresponding
calculated Schottky barrier heights. If the Si is lowly doped, free carriers with high
energy can overcome the barrier and form a current (thermionic emission). If the Si is
highly doped, a current can be formed via thermionic emission as well as free carrier
tunnelling through the barrier. The theoretical Schottky barrier heights q
B
are 0.27 eV
for Al/n-Si contacts and 0.85 eV for Al/p-Si contacts [Neamen 2003]. Both the barrier
height and the built-in voltage (arising from the band bending) are smaller for Al/n-Si
contacts than for Al/p-Si contacts. However, experiments give the opposite result.

It has been found that the Schottky model cannot be applied directly to practical cases
[Sze 1969, Cheng 1977, Rhoderick & Williams 1988]. In practice, the Schottky barrier
height is found to be relatively independent of the metal work function for common
semiconductors like Ge, Si and GaAs. A rule of thumb is that the barrier height is
roughly two-thirds of the bandgap for n-type semiconductors and one-third of the
bandgap for p-type semiconductors [Schroder & Meier 1984], which indicates that the
actual barrier heights are a function of the bandgap. The empirical (experimentally
determined) Schottky barrier values are 0.3-0.4 eV for Al/p-Si contacts and 0.6-0.8 eV
for Al/n-Si contacts [Yu 1970, Chang 1971, Andrews 1974, Pramanik & Saxena 1983,
Schroder & Meier 1984, Neamen 2003, Sze & Nk 2007].

The equations below indicate that the Schottky barrier height
B
is determined by the
metal work function
m
and the semiconductor affinity
s
, as well as semiconductor
86
bandgap E
g
and the surface state neutral level
0
, while the interface state density D
it
is
a weighted factor [Rhoderick & Williams 1988].

5.1 ) )( 1 ( ) (
0
| _ | | q E q q
g m B
+ = ,
where
5.2
it i
i
D q o c
c
2
+
=

i
is the permittivity and is the thickness of the interfacial layer. Bardeen first pointed
out the importance of the energy states in the bandgap induced by the imperfections or
impurities at the semiconductor surface which are known as surface states or interface
states [Bardeen 1947]. The atoms inside a crystalline solid are arranged in a
well-ordered structure. However, the situation at the surface is different due to dangling
(or unsatisfied) bonds which arise from the absence of neighbouring atoms. Surface
states may also result from impurities and defects. There is generally a continuous
distribution of surface states within the silicon bandgap at the surface, characterised by a
neutral level q
0
which is measured from the top of the valence band. The states above
the neutral level are of acceptor type and those below this level are of donor type. Due
to these states the silicon surface is charged, which causes band bending even before
depositing a metal film, see Figure 5.9(b1). Note that there is always a thin native oxide
layer on the silicon surface before metallisation [SNF 2007]. The dangling or
unsatisfied bonds at the semiconductor surface can be passivated by bonding other
foreign atoms to form a more stable compound. Therefore, a native oxide layer helps to
reduce the surface state density and causes the actual barrier height of the contact to be
closer to the ideally expected value.

Equation 5.1 can be simplified for two limit conditions:
i) When D
it
0, then 1 and

5.3 _ | | =
m B
q q

This case indicates a negligible interface state density and the classical Schottky model
applies. The Schottky barrier height is determined by the metal work function
m
and
the electron affinity
s
of the semiconductor. Practically, for Si, D
it
must be smaller than

87
10
12
eV
-1
cm
-2
[Schroder & Meier 1984, Rhoderick & Williams 1988].
ii) When D
it
, then 0 and

5.4
0
| | q E q
g B
=

This case indicates an infinite interface state density and the Bardeen model applies.
The Fermi level at the interface is pinned by the interface states at the value q
0
above
the valence band. The Schottky barrier height is independent of the metal work function
and the electron affinity of the semiconductor but determined entirely by the property of
the semiconductor surface. Practically, for Si, D
it
must be larger than 10
14
eV
-1
cm
-2
in
order to observe a strong Fermi level pinning [Rhoderick & Williams 1988]. In the
Bardeen model, an interfacial SiO
x
layer must be assumed when the MS contact is
formed. This layer is thin enough (< 50 ) to allow electron tunnelling but thick enough
to withstand an electric potential across it. As the Fermi levels of metal and
semiconductor must line up after the MS contact is formed and the Schottky barrier and
the built-in potential at the semiconductor surface are already fixed even before
contacting the metal, the interfacial layer is then responsible for balancing the
voltage/energy difference between systems (metal and semiconductor) after the contact
is formed, see Figure 5.9(b2). The magnitude and polarity of the voltage drop across the
oxide with thickness is determined by the metal work function
m
, semiconductor
work function
s
and the built-in potential
bi
.

Experimentally determined parameters of n-type silicon surfaces are summarised in
Table 5.1. It can be seen that the surface state density of silicon is very high,
approaching the threshold of the Bardeen limit (10
14
eV
-1
cm
-2
). The value of q
0
can be
used to calculate the Schottky barrier height q
Bn
for Al/n-Si contacts, which is 0.8 eV
if assuming that the Fermi level is pinned (Equation 5.4). This value roughly agrees
with the experimentally obtained q
Bn
value of 0.60.8 eV. The corresponding value for
Al/p-Si contacts q
Bp
can then be found via Equation 5.5 [Rhoderick & Williams 1988],
giving 0.3 eV. This again roughly agrees with the experimentally obtained q
Bp

[Pramanik & Saxena 1983]. Note that Equation 5.5 holds regardless of whether the
interface is ideal or not.

88
Table 5.1: Selected properties of the surfaces of
n-type sc-Si (after Cowley & Sze 1965, Sze 2007)

D
it
(eV
-1
cm
-2
) q
0
(eV) q
0
/E
g
0.27 2.710
13
0.3 0.27

5.5
g Bp Bn
E q q + | |

Although the interface state density of silicon has been found to be very high, the Fermi
level E
F
may not be completely pinned at the neutral level q
0
. The Schottky barrier
height still has to be found via Equation 5.1 rather than via the simplified equations. D
it

may also depend on the silicon fabrication technique and possible surface treatments.
Moreover, because there is generally a thin silicon oxide layer on the silicon surface
prior to metallisation (which introduces a fixed positive interface charge and which
passivates the interface), the precise calculation of the Schottky barrier heights for both
Al/n-Si and Al/p-Si contacts is further complicated. A large number of experiments on
singlecrystalline silicon reported in the literature shows that the Schottky barrier heights
are 0.3-0.4 eV for Al/p-Si contacts and 0.6-0.8 eV for Al/n-Si contacts. These values
should be compared with the ideal ones, which are 0.85 eV for Al/p-Si contacts and 0.27
eV for Al/n-Si contacts. Owing to the large discrepancy of empirical and theoretical
barrier height values, as well as the structures of MS contact band diagrams of Al/Si
contacts, it can be speculated that the silicon interface states are mainly acceptor type.
This produces a net negative charge at the interface, see Figure 5.9(b1) and (b2). This
charge is detrimental to n-type contacts but beneficial to p-type contacts. If the silicon is
heavily O contaminated (which introduces a large density of positive charge due to
ionised donors), the overall interface charge arising from the interface states will be
reduced, and hence cause the practical MS contact to become closer to the ideal
situation. See Figure 5.9(c1) and (c2).

89

e
e
e
E
F

E
C

E
V

E
Fi

q
m

Vacuum level
q
s

q
Bn


q
Bn
=
m
= 0.27 eV
(a1)

h
h
h
E
Fi

E
C

E
V

E
F

Aluminium
q
m

Vacuum level
p-type Silicon
q
Bp

q
s

q
Bp
= E
g

(
m
) = 0.85 eV
(a2)

SiO
x
n-type Silicon
q
0

E
F

E
C

E
V

E
Fi

q
bi

q
bi

q
s

Vacuum level
q
s

(b1)

E
F

E
C

E
V

E
Fi

SiO
x
n-type Silicon
q
Bn
= E
g
- q
0

Aluminium

q
m

q
bi

q
bi

Vacuum level
q
s

q
(b2)
+
+
+
+
+
E
F

E
C

E
V

E
Fi

Vacuum level
Bn

SiO
x
n-type Silicon Aluminium
O contaminated
q
Bn
= 0.6- 0.8 eV
(c1)

+
+
+
+
+
E
Fi

E
C

E
V

E
F

Vacuum level
Bp

SiO
x
p-type Silicon Aluminium
O contaminated

q
Bp
= 0.3- 0.4 eV
(c2)

Figure 5.9: Band diagrams of Al/Si contacts. (a1) and (a2) are ideal Schottky models;
(b1) and (b2) are Bardeen models where the Fermi level is pinned; (c1) and (c2) are
practical Al/Si contact band diagrams with and without heavy oxygen contamination of
the silicon. The equations correspond to the contacts which are not heavily oxygen
contaminated.

90

Now let us move the focus to UNSWs poly-Si films fabricated by SPC of e-beam
evaporated silicon.

As discussed in Chapter 2, if the silicon is moderately to heavily doped (110
17

110
20
cm
-3
), the specific contact resistance of intimate metal/semiconductor contacts is
a function of both the Schottky barrier height and the silicon doping density. However,
this conclusion was drawn from (and is usually verified by) the contact resistance
investigation on singlecrystalline silicon. It has not yet been verified on evaporated SPC
poly-Si films for solar cell applications.

Figure 5.10 illustrates the dependence of the specific contact resistance of Al/poly-Si
contacts on the Schottky barrier height and the silicon resistivity. As can be seen,
c
of
Al contacts on both n-type and p-type poly-Si drops dramatically with decreasing
resistivity (i.e., increasing silicon doping density). More specifically, the specific
contact resistance values of Al/p
+
poly-Si contacts fall in the p-type barrier height range
of 0.2-0.4 eV. The specific contact resistance values of Al/n
+
poly-Si contacts fall in the
n-type barrier height range of 0.7-0.85 eV and fit the specific contact resistance curve
reported by Trapp [1980] (the corresponding barrier height is unknown). Overall, the
Schottky barrier height dependence of
c
of both types of MS contacts shown in Figure
5.10 agrees with what is reported in the literature. More precisely, the barrier height of
Al/p
+
poly-Si contacts is close to the lower bound of the reported values while the
barrier height of Al/n
+
poly-Si contacts is close to the upper bound of the reported
values. The sum of the p-type and n-type Schottky barrier heights of Al/poly-Si contacts
is about 1.1 eV, which is the bandgap of sc-Si (Equation 5.5).

As discussed in Section 5.3.1 and Section 5.3.2, some of the investigated samples are
suspected to be heavily oxygen contaminated, giving rise to an abnormal specific
contact resistance in terms of the silicon resistivity (doping density). The Schottky
barrier heights of those samples are suspected to be altered due to this contamination.
Figure 5.11 illustrates the Schottky barrier height and silicon resistivity dependence of
those abnormal samples. As can be seen, the
c
values of Al contacts on heavily O
contaminated n-type and p-type poly-Si fall in the barrier height region of 0.4 eV
(n-type) and 0.5-0.7 eV (p-type), which is very different from the normal Al/Si barrier
91
heights shown in Figure 5.10. This finding agrees with the speculation discussed in
Section 5.3.1 and Section 5.3.2.

100 10 1 0.1
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
|
Bp
=0.4eV
<100>
|
Bp
=0.4eV
<111>
|
Bn
=0.6eV
<111>
|
Bp
=0.3eV
<100>
|
Bp
=0.2eV
<100>
|
Bp
=0.2eV
<111>
|
Bn
=0.6eV
<100>
|
Bn
=0.7eV
<100>
Trapp
|
Bn
=0.85eV
<111>
|
Bn
=0.8eV
<100>
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 5.10: The Schottky barrier height and silicon resistivity dependence of the
specific contact resistance of evaporated SPC poly-Si films. Each Schottky barrier
height curve is labelled with the barrier height value and the silicon crystal
orientation. The doping density axis is not shown as both n-type and p-type contacts
are plotted together. All the data points are taken from Figure 5.4 and Figure 5.8.
Therefore, the error information is not repeated here.

92
100 10 1 0.1
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
|
Bp
=0.5eV
<100>
|
Bn
=0.4eV
<100>
|
Bn
=0.4eV
<111>
|
Bn
=0.3eV
<100>
|
Bp
=0.7eV
<100>
|
Bp
=0.6eV
<100>
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e

c

(
O
-
c
m
2
)

Figure 5.11: The Schottky barrier height and silicon resistivity dependence of the
specific contact resistance of evaporated SPC poly-Si films. The silicon film is
heavily oxygen contaminated. Each Schottky barrier height curve is labelled with
the barrier height value and the silicon crystal orientation. The doping density axis
is not shown as both n-type and p-type contacts are plotted together. (All the data
points are taken from Figure 5.4 and Figure 5.8. Therefore, the error information is
not repeated here.)

5.5 Conclusions

In this Chapter, Al contacts on uniformly doped n
+
and p
+
poly-Si films on glass were
systematically investigated. These films were deposited via e-beam evaporation and
crystallised via SPC. The transmission line models set up at UNSW in the course of this
thesis were found to be well suited to determine the contact resistance of evaporated

93

poly-Si films on glass. All contacts fabricated were found to be ohmic, both before and
after baking. Annealing at low temperatures (150-250C) massively improved the
contact resistance for Al/p
+
poly-Si contacts and Al/SiO
x
/n
+
poly-Si contacts. Higher
baking temperatures ( 300C) had either no effect on the contact resistance (Al/p
+

poly-Si) or degraded the contact resistance (all other investigated contacts).

The Al/SiO
x
/n
+
poly-Si contact structure was found to improve the contact resistance
significantly after sufficient baking as compared to Al/n
+
poly-Si contacts. The trend of
the dependence of Al/n
+
poly-Si contact resistance on resistivity (doping density) agreed
with the trends obtained on sc-Si and LPCVD poly-Si materials which were reported in
the literature. However similar experiments on Al/p
+
poly-Si contacts revealed a much
steeper dependence trend, which implies a different Si surface property from heavily
doped p-type sc-Si and LPCVD poly-Si.

The Schottky barrier height is a figure-of-merit of MS contacts. A series of curves
representing different Schottky barrier heights were reproduced from the literature and
used to fit the measured specific contact resistance of Al contacts on evaporated p
+

poly-Si and n
+
poly-Si in order to determine the barrier heights of Al/poly-Si contacts.
The Schottky model and the Bardeen model were employed to discuss and explain the
results. It was found that the fitted Schottky barrier heights agree well with those
reported in the literature and can be explained with the existing MS contact models.

A fraction of the measurements on both types of contacts were found to be abnormal.
We believe that this is the result of a heavy oxygen contamination of the poly-Si films,
whereby this contamination has occurred either during the a-Si deposition step and/or
the subsequent rapid thermal annealing step. The oxygen contamination caused the MS
contact band structure to change. This change can be explained with the MS contact
models. Experimental evidence for this change was provided by fitting the
measurements with a series of curves representing different Schottky barrier heights.

94

6 Contact resistance results on poly-Si
thin-film diodes on glass

6.1 Motivation

The results from the previous Chapters of this thesis form a sound basis for analysing
complete poly-Si thin-film diodes. In this Chapter, the contact resistance measurement
models and systems established in the course of this thesis are employed to characterise
and improve the aluminium contacts to finished poly-Si thin-film solar cells (diodes) on
glass. The aim is to achieve ohmic contacts to the back surface field (BSF) layers and
the emitter layers of the solar cell samples, with sufficiently low specific contact
resistance.

6.2 Contacts to the back surface field layer of PLASMA
cells
6.2.1 Sample preparation

In this Section, experiments are performed on PLASMA solar cells. Three samples are
used BSPC1, BSPC2 and BSPC3. Each sample has a size of around 5 by 5 cm
2
. The
general design structure and fabrication processes are very similar to EVA solar cell
introduced in Chapter 1, expect that the silicon material is deposited by using PECVD
rather than e-beam evaporator. The specific fabrication parameters of the solar cells
used in this Section are listed in Table 6.1. PLASMA cells were deposited in amorphous
form using PECVD and then crystallised via solid-phase crystallisation (SPC). Emitter,
base and BSF layers were all intended to be uniformly doped. After crystallisation, the
grain size is in the range of 1-2 m. Rapid thermal annealing (RTA) and hydrogenation
(HYD) were then performed on the cells to improve their electrical properties. The RTA
95

system at UNSW uses halogen lamp arrays to heat the sample in a short period of time
in order to activate the dopants as well as passivate point defects in the sample. The
hydrogenation process was performed in a parallel-plate rf PECVD system which is
located in a cluster tool. The main function of this process is defect passivation.
Hydrogenation is a key process of crystalline silicon thin-film solar cell fabrication. It
improves the open-circuit voltage of UNSW poly-Si thin-film solar cells by a factor of
about 2 [Terry 2007].

Table 6.1: Structural parameters of the PLASMA solar cells investi-
gated in this Section.

Parameter Details
Glass 3 mm (planar, borosilicate)
AR coating SiN (~70 nm)
Emitter (PECVD) n
+
(~100 nm, ~110
20
cm
-3
P, ~500 O/)
Base (PECVD) p
-
(~1200 nm, ~510
16
cm
-3
B)
BSF (PECVD) p
+
(~70 nm, ~310
19
cm
-3
B, ~2000 /)
Crystallisation (SPC) 32 hrs @ 615C
RTA 5 min @ 900C
Hydrogenation 90 min @ 400C, direct plasma

Formation of the contact resistance structures on PLASMA samples started with a
piranha clean, followed by a dip in 5% HF to remove the surface oxide. The resulting
surfaces were found to be hydrophobic. The samples were then rinsed for 10 min in DI
water, followed by drying with a nitrogen gun. Next, the samples were immediately
loaded into the evaporator chamber (no loadlock). No oxide layer was intentionally
grown. The chamber was pumped down during about 60 minutes to a pressure of about
10
-5
Torr. Then 300-500 nm thick aluminium was evaporated onto the samples, using
resistively heated evaporation from a tungsten boat. The evaporation rate was 30-50 /s.
The TLM/CTLM structures were then photolithographically patterned. A mesa etch
done by plasma etching (PE) was conducted to constrain the current in the silicon to
only flow directly between the contact pads (not necessary for CTLM patterns).

In this Section, all contact resistance measurements were performed at room
temperature (~300 K) on the back surface field (BSF) layer of PLASMA samples, by
using the Kelvin sense measurement system described in Section 3.8.3. In order to
ensure good measurement precision, the current range used for each measurement
96
covered three orders of magnitude, within the range of 5 A to 100 mA.

6.2.2 Results

Figure 6.1 shows the I-V curves measured from a TLM pattern on the BSF layer of the
PLASMA sample BSPC1 (no surface or contact treatment), and the corresponding fitted
TLM characteristic curve (inset). The measurement was done by using an in-line TLM
pattern which consists of several Al contact bars separated by a resistive poly-Si sheet
with variable length. A linear least square fit was used to fit the measured data points.
Evidently, the contacts are not ohmic or homogeneous and the data points do not show a
linear trend. Therefore, in this case the contact resistance can not be obtained via the
TLM technique.

-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2
volts
a
m
p
s
23 mspacing
15 mspacing
43 mspacing
64 mspacing
84 mspacing
104 m spacing
124 m spacing
145 m spacing

Figure 6.1: I-V curves measured from an in-line TLM pattern on PLASMA sample
BSPC1 (no surface or contact treatment). The inset is the corresponding fitted TLM
characteristic curve (linear fitting).
y =-0.0017x +1.0286
R
2
=0.053
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 50 100 150
spacing (m)
v
o
l
t
a
g
e

(
m
V
)

As shown in Table 6.1, the surface layer was intended to be heavily doped. The results
obtained in Chapter 5 showed that Al contacts on heavily doped poly-Si are ohmic even
without baking. The reason why ohmic contacts cannot be achieved on the virgin BSF

97
layers of PLASMA solar cells is believed to be due to the hydrogenation process.

As a plasma process, hydrogenation is known to alter the silicon surface properties in
two ways. First is surface damage. During the hydrogenation process, particle
bombardment occurs which may introduce heavy lattice damage in an up to 30 nm thick
surface layer [Jeng 1988, Neamen 2003]. Second is dopant neutralisation due to hydro-
genation, which strongly decreases the doping density of the surface layer [Jeng 1988].
Research in our group has shown that boron is much more easily neutralised than
phosphorus [Widenborg 2007].

Figure 6.2 shows the measured I-V curves and the corresponding fitted TLM
characteristic curve (inset) from an in-line TLM pattern on a non-hydrogenated
PLASMA sample (BSPC2). This sample has the same structure and similar fabrication
parameters as BSPC1, but no hydrogenation process was conducted. Evidently, this
sample exhibits ohmic and homogeneous contacts as well as a linear characteristic curve
without any contact or surface treatment. The measured specific contact resistances on
different positions of this sample are in the order of 10
-4
Ocm
2
, as listed in Table 6.2.

-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2
volts
a
m
p
s
16.5 mspacing
25 mspacing
45.5 mspacing
66.5 mspacing
86.5 mspacing
106.5 mspacing
127 mspacing
147 mspacing

Figure 6.2: I-V curves measured from an in-line TLM pattern on PLASMA sample
BSPC2 (no hydrogenation, no surface or contact treatment). The inset is the
corresponding fitted TLM characteristic curve (linear fitting), giving
c
= 3.510
-4

Ocm
2
.
y =0.6349x +3.8552
R
2
=0.9987
0
10
20
30
40
50
60
70
80
90
100
0 20 40 60 80 100 120 140 160
spacing (m)
v
o
l
t
a
g
e
(
m
V
)

98

Table 6.2: Specific contact resistances and sheet resistances
measured on different BSF positions of the non-hydrogenated
PLASMA sample BSPC2, using TLM and CTLM structures.

Pattern R
sheet
(/)
c
(Ocm
2
) Current range (A)
TLM 3810 4.310
-4
5-5000
TLM 3000 2.310
-4
5-5000
CTLM 2934 4.810
-4
5-5000
CTLM 3088 2.110
-4
5-5000
CTLM 2916 7.810
-4
5-5000

Two approaches were used to solve hydrogenation-induced surface degradation. One is
baking of the contacts. During thermal annealing, aluminium atoms diffuse into silicon
and react with Si atoms. This process happens more quickly where there is a high defect
density [Neamen 2003]. As a large defect density is introduced to the solar cell surface
during the hydrogenation process, it is believed that low temperature baking (< 300C)
can cause the aluminium to penetrate through the heavily damaged surface layer and
form ohmic contacts to the lightly damaged Si layer underneath.

After completion of the first measurements (Figure 6.1), sample BSPC1 was
sequentially baked at 150, 200, 250 and then 300C in an N
2
purged oven. The duration
of each bake was 30 minutes. Figure 6.3(a) (d) are a series of figures showing how the
contacts are dramatically improved via baking. After annealing at 250C for 30 min, the
R
2
value of the TLM characteristic curve approaches 0.99, which is close to the R
2

values of Al contacts on Si wafers and poly-Si thin-film samples investigated in the
previous Chapters. The contacts become ohmic and homogeneous enough to perform a
reliable TLM measurement. Annealing at 300C for 30 min further increases the homo-
geneity of the contacts and lowers the contact resistance. However, high temperature
annealing (> 300C) degrades the electrical performance of the device due to loss of
hydrogen [Terry 2007]. Hence, 250C is the optimum baking temperature for
minimising hydrogenation -induced Si surface damage in PLASMA cells.

99
-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2 1.5
volts
a
m
p
s
15 mspacing
23 mspacing
43 mspacing
64 mspacing
84 mspacing
104 mspacing
124 mspacing
145 mspacing

y =0.0013x +0.8619
R
2
=0.1169
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 50 100 150
spacing (m)
v
o
l
t
a
g
e

(
m
V
)

(a)
-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
volts
a
m
p
s
15 mspacing
23 mspacing
43 mspacing
64 mspacing
84 mspacing
104 mspacing
124 mspacing
145 mspacing

y =3.0993x +298.26
R
2
=0.8872
0
100
200
300
400
500
600
700
800
900
0 50 100
spacing (m)
v
o
l
t
a
g
e

(
m
V
)
150

(b)
-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
volts
a
m
p
s
15 mspacing
23 mspacing
43 mspacing
64 mspacing
84 mspacing
104 mspacing
124 mspacing
145 mspacing

y =2.8233x +100.21
R
2
=0.9877
0
100
200
300
400
500
600
0 50 100
spacing (m)
v
o
l
t
a
g
e

(
m
V
)
150

(c)
-6.E-03
-3.E-03
0.E+00
3.E-03
6.E-03
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
volts
a
m
p
s 15 mspacing
23 mspacing
43 mspacing
64 mspacing
84 mspacing
104 mspacing
124 mspacing
145 mspacing

y =2.7657x +54.785
R
2
=0.9967
0
50
100
150
200
250
300
350
400
450
500
0 50 100
spacing (m)
v
o
l
t
a
g
e
(
m
V
)
150

(d)
Figure 6.3: Measured I-V curves from in-line TLM patterns on the BSF layer of
sample BSPC1 and the corresponding fitted TLM characteristic curves of the contacts
after baking for 30 min at (a) 150C,
c
= not measurable; (b) 200C,
c
= 2.810
-2

Ocm
2
; (c) 250C,
c
= 5.310
-3
Ocm
2
; (d) 300C,
c
= 1.810
-3
Ocm
2
.

100
In the literature it is reported that, during plasma processing, the first several
nanometres of silicon are most heavily damaged and dopant-neutralised [Graves 1994].
Therefore, the other approach is to remove a thin surface layer so that ohmic contacts
can be formed on less heavily damaged silicon material. PLASMA sample BSPC3 was
cut into several small samples. Before performing the routine cleaning and the TLM
patterning processes, some of these samples were wet-chemically etched using coloured
HF for different durations. The etch rate is around 15 /s for our poly-Si (without seed
layer)
. Then all samples were cleaned and TLM/CTLM patterned. After the first
measurement, the contacts were baked at 250C for 30 min in a N
2
purged oven. Figure
6.4 illustrates the typical I-V curves measured from one CTLM pattern on the BSF layer
of one of these samples (a) with and (b) without surface treatment before contact
annealing. As can be seen, the contacts become ohmic and homogeneous after the
surface treatment.

-6.0E-2
-4.0E-2
-2.0E-2
0.0E+0
2.0E-2
4.0E-2
6.0E-2
-4 -3 -2 -1 0 1 2 3 4
volts
a
m
p
s
5 m spacing
10 m spacing
15 m spacing
20 m spacing
25 m spacing
30 m spacing

(a)

All coloured HF solutions used in this Chapter were made using the same recipe.
101
-6.0E-2
-4.0E-2
-2.0E-2
0.0E+0
2.0E-2
4.0E-2
6.0E-2
-3 -2 -1 0 1 2 3
volts
a
m
p
s
5 mspacing
10 mspacing
15 mspacing
20 mspacing
25 mspacing
30 mspacing

(b)

Figure 6.4: The measured I-V curves from the CTLM patterns on the BSF
layers of two samples cut from BSPC3, (a) before and (b) after coloured HF
etching of the surface for 5 sec.

The improvement of the specific contact resistance
c
arising from baking and coloured
HF etching is compared in Figure 6.5. Due to difficulties with precisely measuring the
active layer thickness, the sheet resistance is used instead of resistivity to evaluate the
doping density. The thickness of the BSF layer is believed to be laterally uniform. Note
that the peak doping level occurs near the surface and is constant over a certain
thickness but drops abruptly when approaching the p-n junction. Therefore, the etching
duration must be optimised to a point that the most heavily damaged layer is removed
while high surface doping density is still maintained. As can be seen in Figure 6.5, both
baking and coloured HF etching improve
c
to values in the order of 10
-5
Ocm
2
. On
average, 10 seconds of etching yields the lowest
c
of around 110
-5
Ocm
2
. With
increasing etching duration, the sheet resistance increases as the thickness of the BSF
layer decreases. After etching for 25 sec,
c
becomes higher as the surface is close to the
p-n junction and with a lower doping density. After the etched samples were baked at
250C for 30 min, the specific contact resistance became too low to be measurable and
hence is not shown.

102
1.2k 1.6k 2.0k 2.4k 8.0k 12.0k 16.0k
10
-6
10
-5
10
-4
10
-3
250C baking for 30m
5s coloured HF etching
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
Sheet resistance (O/)

Figure 6.5: The specific contact resistances of Al on the BSF layers of PLASMA
samples cut from BSPC3. The error bars represent the 95% confidence interval.

In conclusion, both approaches (surface etching and contact annealing) can solve the
contact problem arising from hydrogenation-induced surface degradation, giving ohmic
contacts and sufficiently low contact resistances. This finding is used for guiding
contact resistance experiments on other types of UNSW poly-Si thin-film solar cells.

103

6.3 Contacts to the back surface field layer of EVA cells

In this Section, an EVA solar cell sample (EVA1) is investigated. The size was around 5
by 5 cm
2
. The general design structure and fabrication processes have been introduced
in Chapter 1. The specific fabrication parameters of the solar cell used in this Section
are listed in Table 6.3. EVA solar cells are deposited using e-beam evaporation and
crystallised via SPC. Emitter, base and BSF layers are all intended to be uniformly
doped. After crystallisation, the grain size is in the range of 0.8-1.5 m [Song 2006].
Similar to PLASMA cells, RTA and HYD were then performed on the cells to improve
their electrical properties.

Table 6.3: Structural parameters of the EVA solar cells investigated in
this Section.

Parameter Details
Glass 3 mm (planar, borosilicate)
Emitter (e-beam) n
+
(~100 nm, ~110
20
cm
-3
P)
Base (e-beam) p
-
(~1500 nm, ~510
16
cm
-3
B)
BSF (e-beam) p
+
(~100 nm, ~510
18
cm
-3
B, ~1500 /)
Crystallisation (SPC) ~24 hrs @ about 600C
RTA 4 min @ 900C
Hydrogenation 20 min @ 585C, remote plasma

Formation of the contact resistance structures on the BSF layers of EVA samples and the
contact resistance measurement are exactly the same as PLASMA samples. Again, the
I-V measurements on the untreated surface and the unbaked contacts indicate
non-ohmic behaviour due to hydrogenation-induced surface degradation, as shown in
Figure 6.6(a). However, the homogeneity of these contacts is much better than that of
the PLASMA sample shown in Figure 6.1. This is believed to be due to the different
plasma conditions used in the hydrogenation process. After baking at 250C for 30 min
in a N
2
purged oven these contacts were ohmic, as can be seen in Figure 6.6(b). It was
also found that coloured HF etching can make the contacts ohmic.

104
-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-3 -2 -1 0 1 2 3 4
volts
a
m
p
s
5 m spacing
10 mspacing
15 mspacing
20 mspacing
25 mspacing
30 mspacing

(a)

-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-2.0 -1.0 0.0 1.0 2.0 3.0
volts
a
m
p
s
5 m spacing
10 m spacing
15 m spacing
20 m spacing
25 m spacing
30 m spacing

(b)

Figure 6.6: Measured I-V curves from a CTLM pattern on the BSF layer of an
EVA sample cut from EVA1, (a) before and (b) after baking the contacts at 250C
for 30 min.

Figure 6.7 illustrates the specific contact resistance
c
of Al contacts to the p-type BSF
layers of EVA samples. These samples were cut from sample EVA1. The effects of
baking and coloured HF etching (5 sec and 10 sec, before and after baking) are

105
compared. All bakes were conducted at 250C for 30 min in a N
2
purged oven.
Generally,
c
drops with decreasing sheet resistance. Again, it is found that either
contact annealing or surface etching can eliminate the contact anomaly arising from
hydrogenation-induced surface degradation. A specific contact resistance of below 10
-4

Ocm
2
can be achieved via baking and/or surface treatment.

800 1000 1200 1400 1600 1800 2000
10
-7
10
-6
10
-5
10
-4
10
-3
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)
250C baking for 30m
5s coloured HF etching +bake
10s coloured HF etching +bake

Figure 6.7: Measured specific contact resistances of Al contacts to the BSF layers of
EVA samples cut from EVA1, after different surface or contact treatments. The error
bars represent the 95% confidence interval.

106

6.4 Contacts to the back surface field layer of ALICIA
cells

In this Section, experiments were performed on ALICIA solar cells. Two samples were
used IAD1 and IAD2. Each sample was 5 by 5 cm
2
. The general design structure and
fabrication processes have been introduced in Chapter 1. The specific fabrication
parameters of the solar cells used in this Section are listed in Table 6.4. ALICIA solar
cells are deposited using e-beam evaporation. However, in contrast to EVA and
PLASMA cells, ALICIA cells are epitaxially grown on a seed layer using the IAD
(Ion-Assisted Deposition) technology. The seed layer on the SiN-coated glass is made
by AIC (Aluminium-Induced Crystallisation) of a-Si. The grain size of ALICIA material
is in the range of 10-20 m [Aberle 2005]. Then, RTA and HYD are performed on the
solar cells to improve their electrical properties. Note that a standard ALICIA cell has an
n-type BSF, an n-type base, and a p-type emitter.

Table 6.4: Structural parameters of the ALICIA solar cells investigated in this Section.

Parameter Details
Seed layer (AIC) p
+
(~75nm, ~110
19
cm
-3
Al)
Emitter (IAD) p
+
(~50 nm, ~110
19
cm
-3
Ga)
Base (IAD) n
-
(~1200 nm, ~710
16
cm
-3
P)
BSF (IAD) n
+
(~80 nm, up to 110
20
cm
-3
P at the surface, ~500 - 2000 /)
RTA 205 sec @ 900C
Hydrogenation 15 min @ 600C, remote plasma

Formation of the contact resistance structures on the BSF layers of ALICIA samples and
the contact resistance measurements are exactly the same as for the previous two types
of solar cells. In contrast to the findings on PLASMA and EVA samples, the I-V
measurements from the CTLM patterns on the BSF layers of samples IAD1 and IAD2
(no surface etching or contact baking), shown in Figure 6.8(a) and (b), indicate a nearly
ohmic property. The linearity of these curves is substantially better than that of
PLASMA and EVA samples. This is believed to be due to two factors. First, a remote
plasma was used in the hydrogenation process instead of the more energetic direct
107
plasma used for PLASMA cells. Therefore, the ion bombardment during the
hydrogenation process was diminished. Second, as mentioned in Section 6.2.2, the
dopant neutralisation effect is much weaker for phosphorus than for boron. As a result
of these two factors, the hydrogenation process induces only a slight degradation of the
n
+
doped BSF layer of ALICIA cells. Therefore, ohmic contacts immediately exist after
Al deposition and there is no need for resorting to any surface or contact treatment.

-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
-0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20
volts
a
m
p
s
10 m spacing
20 m spacing
30 m spacing
40 m spacing
50 m spacing
60 m spacing

(a)

-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
volts
a
m
p
s
10 m spacing
20 m spacing
30 m spacing
40 m spacing
50 m spacing
60 m spacing

(b)

Figure 6.8: Measured I-V curves from a CTLM pattern on the BSF layer of
ALICIA sample (a) IAD1 and (b) IAD2 (no contact baking or surface etching).

108

After the first contact resistance measurement, sample IAD2 was baked for 30 min at
about 240C
in a N
2
purged oven and sample IAD1 was Al-stripped to receive the
surface treatment. After surface cleaning and a 5% HF dip, sample IAD1 was then
etched in coloured HF solution for 30 sec. Then, it was metallised and CTLM patterned
again. Due to the larger grains (smaller grain boundary density), the Si etch rate in
coloured HF was found to be much lower for ALICIA cells than for PLASMA and EVA
cells. After 30 sec of etching, the average sheet resistance only increased by around 20%,
from 560 / to 670 /, which implies that the BSF layer was only slightly thinned.
Figure 6.9(a) and (b) illustrate the I-V measurements from a CTLM pattern on each
ALICIA sample. Evidently, the I-V curves become non-ohmic as compared to Figure
6.8. In contrast to the results on PLASMA and EVA samples, baking and surface etching
were found to be detrimental to the contacts on ALICIA BSF layers (which have an
Al/n
+
poly-Si contact structure).

The reason why baking deteriorates the BSF contacts of ALICIA samples is believed to
be due to the reaction between the Al layer and the n-type BSF layer. As discussed in
Chapter 5, annealing of Al/n-Si contacts may cause Al to introduce ionised acceptor
atoms at the n-Si surface and lead to an Al/p-Si/n-Si contact structure which increases
the contact resistance. The higher the annealing temperature, the more severely the
contact is degraded. And according to SIMS measurements on ALICIA solar cells, the
BSF surface doping density is very low, of the order of 10
18
cm
-3
[Terry 2007].
Therefore, 240C baking for 30 min may introduce sufficient thermal budget to change
the contacts qualitatively, i.e., lose the ohmic property. Again, according to SIMS
measurements, the doping density below the surface of ALICIA cells is not uniform but
decreases steeply in the first 100 nm. This is the believed reason why removing a thin
layer from the surface leads to non-ohmic and inhomogeneous contacts as the surface
doping concentration becomes lower. Comparing Figure 6.9(a) and (b), it can be found
that surface etching degrades the contacts more severely than baking. Note that the
resistance from every I-V measurement consists of the contact resistance R
c
and the
resistance of BSF layer sheet R
semi
. The I-V curves in (a) twist with each other, which
implies that the R
c
becomes so high that it dominates the total measured resistance
instead of the R
semi
. After the measurement in Figure 6.9(a), sample IAD1 was also

The used oven failed to reach the intended baking temperature (250C) during the baking process for unknown
reason.
109
baked at 240C for 30 min. The contact was not improved as expected and hence the
results are not shown here.

-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
volts
a
m
p
s
10 mspacing
20 mspacing
30 mspacing
40 mspacing
50 mspacing
60 mspacing

(a)

-6.E-03
-4.E-03
-2.E-03
0.E+00
2.E-03
4.E-03
6.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
volts
a
m
p
s
10 m spacing
20 m spacing
30 m spacing
40 m spacing
50 m spacing
60 m spacing

(b)

Figure 6.9: Measured I-V curves from a CTLM pattern on the BSF layer of
ALICIA sample (a) IAD1, after 30 sec coloured HF etching of the surface; and
(b) IAD2, after baking the contacts at 240C for 30 min.

110
The measured specific contact resistances
c
of samples IAD1 and IAD2, before and
after baking, are presented in Figure 6.10. Evidently,
c
drops with the decreasing sheet
resistance. It can be seen that baking not only increases the
c
values but also causes
larger error bars due to the fact that the TLM technique is unreliable for non-ohmic
contacts. Generally, owing to the different surface doping levels, the specific contact
resistance of as-metallised ALICIA BSF layers is of the order of 10
-3
cm
2
. Due to the
severely degraded I-V characteristics of sample IAD1 after surface etching, the contact
resistance could not be measured and hence is not shown.
10
2
10
3
10
4
10
-4
10
-3
10
-2
10
-1
IAD1 as metallised
IAD2 as metallised
IAD2 after baking
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 6.10: Measured specific contact resistances of Al contacts on the BSF layers of
ALICIA solar cell samples IAD1 and IAD2. The error bars represent the 95%
ce interval.

confiden

111

6.5 Contacts to the emitter layer of PLASMA cells

In this Section, PLASMA solar cell sample BSPC3 is investigated. Its structure is
shown in Table 6.1 (see Section 6.2). All samples used in this Section were cut from this
5 by 5 cm
2
sample (done in Section 6.2). The sample preparation steps are as follows:
The BSF and base layer of the sample were etched off by using plasma etching (PE). A
hot-probe station was used to detect the polarity of the remaining layer. The reason of
using PE is to i) mimic the standard solar cell metallisation processes which was
introduced in Chapter 1; ii) investigate the impact of PE on the contact resistance of the
emitter layer. The formation of the CTLM patterns on the emitter layer is exactly the
same as on the BSF layer. In order to find out if hydrogenation and/or plasma etching
damages the surface, some samples were etched in coloured HF solution for 20 seconds
prior to the metallisation step. A top view of a finished sample is shown in Figure 6.11.
The dark areas are the aluminium patterns (CTLM and the others). Al thickness is
around 300 nm. The yellowish area is n-type poly-Si (emitter layer), with a thickness in
the centre of the glass piece of around 100 nm. Due to inhomogeneity issues with our
plasma etching process, the silicon was etched more quickly in the periphery than in the
centre of the substrate. As a result, there is a Si thickness slope towards the edges of the
glass after PE. A cross-sectional sketch of the samples is shown in Figure 6.12.

112

Figure 6.11: Photograph (top view) of the CTLM and other Al patterns
(dark) on a plasma etched PLASMA sample. The glass is slightly
wrinkled. The yellowish layer is the emitter. The three CTLM patterns
indicated by the arrows correspond to the three patterns depicted in
Figure 6.12.

a
b c
Glass
SiN
CTLM
pattern
poly-Si

Figure 6.12: Cross-sectional sketch of the sample shown in Figure
6.11 (not to scale). The three labelled CTLM patterns correspond to
the three patterns indicated in Figure 6.11 and the three graphs in
Figure 6.13.
c
b
a

Depending on exactly where the CTLM patterns sit on the emitter layer, the resulting
I-V characteristics are different, as shown in Figure 6.13(a), (b) and (c). Each CTLM
pattern (a, b and c as shown in the two figures above) yields four valid I-V curves: (a)
for the pattern sitting entirely on the slope between poly-Si and glass, the contacts are
all ohmic; (b) for the pattern sitting partly on the slope, some contacts become
non-ohmic; (c) for the pattern sitting beyond the slope but near the centre, the contacts
are all non-ohmic. This phenomenon is believed to be due to the varied doping density

113
over the thickness of the etched emitter layer. The peak doping density is expected to
occur at the emitter surface on the glass side (next to the SiN layer). With increasing
distance from the glass-side surface, the doping density drops. On lowly doped n-Si,
intimate Al/Si contacts are not ohmic. This is why the evolution of the I-V
characteristics of those three CTLM patterns (a, b and c) occurs as shown in Figure
6.13.

-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
volts
a
m
p
s
10 m spacing
30 m spacing
40 m spacing
50 m spacing

(a)

-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-2.0 -1.0 0.0 1.0 2.0 3.0
volts
a
m
p
s
20 m spacing
30 m spacing
50 m spacing
60 m spacing

(b)

114
-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
volts
a
m
p
s
15 mspacing
20 mspacing
25 mspacing
30 mspacing

(c)

Figure 6.13: I-V curves measured on the three CTLM patterns on the emitter
layer of a PLASMA sample cut from BSPC3 (no contact or surface treatment).
(a) The pattern sits entirely on the sloped silicon region; (b) the pattern sits
partly on the sloped silicon region; (c) the pattern sits in the central region of
the sample.

Figure 6.14 presents the specific contact resistance
c
of Al contacts to the plasma
etched n-type poly-Si emitter layers of PLASMA samples. The impact of the surface
treatment is also illustrated. Again, due to difficulties with precisely measuring the
thickness of the active layer, the sheet resistance is used instead of the resistivity.
However, it can not be used to evaluate the doping density as the thickness of the
emitter was not constant after PE. Evidently, coloured HF etching has nearly no affect
on the contact resistance and hence is not necessary for forming ohmic Al contacts to
the emitter layers of PLASMA solar cells. This is believed to be due to two factors: 1)
The emitter layer is buried under the base of the solar cell. Therefore,
hydrogenation-induced surface damage does not exist. 2) The dry etching process
during PE is not accomplished through physical collisions and hence very little surface
damage occurs. The other interesting finding in Figure 6.14 is that the contact resistance
drops with increasing sheet resistance. This is due to the non-uniform doping profile of
the emitter layer. The closer the contact is to the glass side surface, the higher the
doping density and the sheet resistance will be. This finding agrees with the results of

115
I-V measurements in Figure 6.13. However,
c
tends to stabilise at the thickness where
the sheet resistance of the poly-Si layer underneath the contacts is larger than ~300 /,
which implies that the doping density tends to be constant near the glass side surface.
The effect of baking on the contact resistance of Al contacts to the emitter of PLASMA
cells was also investigated. No significant improvement was found and hence the results
are not shown here.

100 150 200 250 300 350 400
10
-6
10
-5
10
-4
10
-3
10
-2
no coloured HF etching
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 6.14: The specific contact resistance, with and without surface treatment, of
Al contacts to the emitter layers of PLASMA samples cut from sample BSPC3. The
trend line of the dependence of
c
on the sheet resistance is also shown. The error
bars represents the 95% confidence interval.

116
6.6 Contacts to the emitter layer of EVA cells

In this Section, the EVA solar cell sample EVA1 is investigated. Its structure is shown in
Table 6.3 (see Section 6.3). All samples used in this Section were cut from this 5 by 5
cm
2
sample (already done in Section 6.3). The emitter layer preparation and CTLM
pattern formation procedures are exactly the same as those of PLASMA sample BSPC3.
The resulting sample topology is also similar as BSPC3 (Figure 6.11 and Figure 6.12).
Again, the I-V characteristics were found dependent on the exact positions of the
measurement patterns, as shown in Figure 6.15(a), (b) and (c). The reason is believed to
be the same as for PLASMA samples.

-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
volts
a
m
p
s
25 m spacing
20 m spacing
30 m spacing
60 m spacing

(a)

117
-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
volts
a
m
p
s
10 m spacing
20 m spacing
30 m spacing
40 m spacing
50 m spacing
60 m spacing

(b)

-6.E-02
-4.E-02
-2.E-02
0.E+00
2.E-02
4.E-02
6.E-02
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
volts
a
m
p
s
10 m spacing
20 m spacing
30 m spacing
40 m spacing
50 m spacing
60 m spacing

(c)

Figure 6.15: I-V curves measured from the three CTLM patterns on the
emitter layer of an EVA sample cut from EVA1 (no contact or surface
treatment). (a) The pattern sits entirely on the sloped silicon region; (b) the
pattern sits partly on the sloped silicon region; (c) the pattern sits in the
central sample region.

Figure 6.16 illustrates the measured specific contact resistance
c
of Al contacts to the
plasma etched n-type poly-Si emitter layers of the EVA samples. The effect of surface
treatments is also investigated. Again, coloured HF etching was found to not improve
118
the contact resistance. However, coloured HF etching should not harm the contact. The
large discrepancy between data point s6 and s3 at the sheet resistance of around 300
/ is believed to be due to the non-uniformity of the EVA emitter doping density. The
trend line in Figure 6.16 shows that the contact resistance drops with the increasing
sheet resistance, but stabilises at the thickness where the sheet resistance is around 275
/ (if data point s6 is ignored). Similar to the finding on PLASMA samples, this
implies that the doping level of the EVA emitter layer becomes constant when the
glass-side surface is approached. Again, baking was found to not improve the contact
resistance significantly and hence the results are not shown here.

100 150 200 250 300 350
10
-6
10
-5
10
-4
10
-3
s3
s3
s3
s3
s6
s2
no coloured HF etching
S
p
e
c
i
f
i
c

c
o
n
t
a
c
t

r
e
s
i
s
t
a
n
c
e
c

(
O
-
c
m
2
)

Figure 6.16: The specific contact resistance, with and without surface treatment, of
Al contacts to the emitter layers of the EVA samples which were cut from sample
EVA1. The label beside each data point denotes the name of the sample where the
measurement was performed. The trend line of the dependence of
c
on the sheet
resistance is also shown. The error bars represents the 95% confidence interval.

119

6.7 Conclusions

In this Chapter, the contact resistance of Al contacts to PLASMA, EVA and ALICIA
solar cells was investigated. The p-type back surface field layers of PLASMA and EVA
cells were found to be degraded during the hydrogenation process (surface damage,
dopant neutralisation). As a consequence, the Al/poly-Si contacts were found to be
non-ohmic and inhomogeneous. Two methods, thermal annealing and coloured HF
etching, were employed to solve this problem. The resultant contacts were ohmic, with
specific contact resistances of below 10
-4
cm
2
. However, baking and surface treatment
were found to be detrimental to Al contacts on the n-type back surface field layers of
ALICIA solar cells. The specific contact resistance measured right after Al evaporation
was in the order of 10
-3
cm
2
, which is adequate for the interdigitated metallisation
scheme of our thin-film solar cells.

The contact resistance of the n-type emitter layers of PLASMA and EVA solar cells was
also investigated. It was found that the hydrogenation and plasma etching processes did
not introduce any anomalies. However, the doping profile was not uniform across the
whole emitter layer (the doping density was found to decrease with increasing distance
from the glass-side silicon surface). Good ohmic contacts with specific contact
resistances of below 10
-4
cm
2
were only obtained on heavily doped emitter layers (last
several tens of nanometres). Considering that the interdigitated metallisation scheme
forms the emitter contacts by partly covering the sidewalls of the grooved silicon
thin-film diode (i.e., the metal is in contact with both the highly and the lowly doped
emitter regions, see Chapter 1 for details), the contact resistance of the emitter layers of
PLASMA and EVA solar cells is believed to be sufficiently low and hence it is not
necessary to resort to any contact or surface treatment.

120

7 A novel contact resistance
measurement model
7.1 Motivation

As discussed in Chapter 2, in order to measure a low contact resistance on a semicon-
ductor layer that has a high sheet resistance, the TLM pattern has to be designed as
small as possible. This is due to the fact that the contact resistance can only reliably and
accurately be measured if it is not much smaller than the semiconductors sheet
resistance. This directly follows from the functional dependence among the total
measured resistance, the sheet resistance, and the contact resistance:

7.1
c semi total
R R R + = 2

R
total
is measured via an I-V measurement between two contacts which are spaced by a
resistive semiconductor sheet. It consists of the contact resistance R
c
(in the unit of )
and the resistance arising from the semiconductor sheet, R
semi
. However, patterns with
contact spacing smaller than 1 m are not easy to fabricate and measure with the infra-
structure that was available for this thesis work. This represented the main limit for the
TLM and other indirect contact resistance measurement models in this thesis. Direct
measurements, for example on 6-terminal Kelvin test structures [Proctor 1983], require
very precise photolithography processes and hence the sample preparation is very
complicated and demanding. In this Chapter, an innovative indirect measurement model
for the contact resistance is introduced. It is named FCM (Full-Area Circular Contact
Model). This model has higher measurement precision compared to the current TLM
structures but nevertheless is easy to fabricate.

121

7.2 Fabrication and underlying theory

There are three ways to ensure R
c
is comparable to R
semi
: 1) To reduce the semicon-
ductor sheet resistance; 2) to reduce the contact spacing of the measurement pattern; 3)
to reduce the contact area so as to increase the contact resistance effect. The first
method is usually not a good idea from the viewpoint of device fabrication. The second
is limited by the capabilities of the photolithography process and is the main bottleneck
of TLM technique. The full-area circular contact model (FCM) utilises the third method
to ensure R
c
has a significant impact in the measurements.

In the TLM technique, if the sheet resistance is relatively high, the contact area is
usually the product of the current transfer length L
T
and the contact width Z. Decreasing
Z results in a linear increase of both R
semi
and R
c
, and hence only L
T
should be
decreased to reduce the contact area. However, the accuracy of the L
T
value is
correlated to the contact spacing of the TLM pattern. If L
T
is smaller than 5% of the
average contact spacing, it cannot be measured accurately (and hence the contact
resistance cannot be measured accurately). The purpose of the new model (FCM) is to
tackle this problem.

7.2.1 Structure

A typical FCM structure is schematically shown in Figure 7.1. There is no harm to use a
silicon diode on a transparent substrate as the starting material. Other possible structures
for the starting material are discussed later.

Viewed from the top, the FCM is identical to the CTLM introduced in Chapter 2. The
circular design eliminates the mesa etching step and hence greatly simplifies the pattern
fabrication process. The cross-sectional view shows that the thin-film diode consists of
two semiconductor layers. Layer 1 is lowly doped and has a sheet resistance that is
much larger than that of layer 2. Layer 2 is highly doped and is the layer for which the
contact resistance is measured by the FCM. The metal covers the entire sidewall of
122
layer 2 (full-area contact) and the lower parts of the sidewall of layer 1. An I-V
measurement is performed on each of the ring patterns. The results are fitted with the
mathematical model described below, from which the specific contact resistance and the
sheet resistance of layer 2 can be determined. As layer 1 is lowly doped, the current will
flow primarily in layer 2.

Substrate Transparent substrate
Silicon
Layer 1
Metal
p-n junction
Silicon
Layer 2
I/V

Figure 7.1: Top view (top) and cross-sectional view (bottom) of an FCM pattern.

7.2.2 Suggested fabrication procedure

The whole fabrication process consists of two photolithography steps. First, the starting
silicon material is photolithographically patterned into ring structures (yellow area in
Figure 7.1), using plasma etching (or another isotropic etching process) so that the
sidewalls of the silicon are slightly sloped. This favours the later metal contact
formation. Then the sample is blanket-coated with positive photoresist and baked (to
pre-bake the PR), Then the PR is exposed to collimated UV light, incident from the
123
substrate side. UV light passes through the transparent substrate but is fully absorbed by
the silicon thin-film. As a result the remaining silicon (ring-shaped) acts as a
self-aligned photomask, and only the photoresist (PR) on the etched regions is exposed.
The photoresist is then developed and post-baked. Next, a layer of metal is deposited
over the surface and a PR lift-off process is performed, leaving the metal only in the
etched regions as shown in Figure 7.1. The metal layer slightly ramps up at the
sidewalls because the sidewalls are slightly sloped.

7.2.3 Theory

The mathematical model is based on Equation 7.2 which is similar to Equation 7.1. R
total

can be easily obtained via an I-V measurement on the structure shown in Figure 7.1.
R
semi
is the resistance arising from the silicon sheet between two contacts, as shown in
Figure 7.2. R
c1
and R
c2
are the contact resistances of the inner contact (radius r
1
) and the
outer contact (radius r
2
) respectively, in the unit of .

7.2
2 1 c c semi total
R R R R + + =

R
semi
can be calculated via integration over the width of the semiconductor ring, from r
1

to r
2
:

7.3
1
2
ln
2 2
1
2
r
r R
x
dx R
R
sheet
r
r
sheet
semi
= =
)
t t
,

where R
sheet
is the sheet resistance.

As it is a full-area contact, no current transfer length is involved. R
c1
is then inversely
proportional to the contact area:

7.4
t r A
R
c c
c

= =
1
1
2t

,

where A is the contact area,
c
is the specific contact resistance (unit cm
2
) and t is the

124
thickness of the layer under test (layer 2 in Figure 7.1). Note that the error in t arising
from the slightly sloped sidewall is neglected in the above equations.

Similarly, R
c2
is:

7.5
t r
R
c
c

=
2
2
2t

Substituting Equations 7.2, 7.3 and 7.4 into Equation 7.5, we finally obtain:

7.6
|
|
.
|
\
|
+ +
|
|
.
|
\
|
=
2 1 1
2
1 1
2
ln
2 r r t r
r R
R
c sheet
total
t
t

If r
1
, r
2
and t are known, the total resistance obtained from the I-V measurement is
determined by R
sheet
and
c
. Therefore, at least two I-V measurements are required to
enable a fit using Equation 7.6 in order to obtain these two values. Extra I-V
measurements will increase the accuracy of the results.

r
2

r
1

Ax

Figure 7.2: Modelling of a single
ring pattern (top view). The white
region is the silicon. The grey region
is the metal. The hatched region is a
silicon ring with an infinitesimal
width.

In the FCM, the contact area A is directly proportional to the thickness t of the target
layer. As discussed at the beginning of Section 7.2, the contact area of TLM structures is
usually directly proportional to L
T
which is the counterpart of t in FCM. Practically, a
reliable TLM measurement demands L
T
to be larger than 1 m. However, the thickness

125

of a target layer in a poly-Si thin-film PV device is usually of the order of 0.1 m. As a
result, the contact area of the FCM can be several tens of times smaller than that of the
TLM. Hence, the contact resistance can be measured more accurately. This is the key
idea behind the FCM structure.

7.3 Discussion and conclusions

In this Chapter, a novel contact resistance model called the full-area circular contact
model (FCM) has been introduced. Theoretically, the FCM can significantly boost the
measurement precision compared to the TLM. However, due to time limitations of this
thesis, the experimental work of this method has not finalised yet.

As shown in Figure 7.1, the structure preferred for this method is a two-layer
semiconductor diode on a transparent substrate. The semiconductor can be poly-
crystalline Si, but any other semiconductor that has a very high absorption coefficient
for UV light works equally well. The semiconductor can consist of a single layer or
multiple layers on a transparent substrate, as long as the other layers do not interfere in
the measurement of the target layer. If a thin single layer is used, the UV light may not
be fully absorbed by this layer and hence the overlying photoresist may be developed.
As a result, the metal layer may ramp onto the silicon surface after the lift-off step and
dramatically increase the contact area. Therefore some process controls are needed to
avoid this phenomenon. A modification of the second photolithography step is
suggested as follows: Use a positive PR that needs a higher UV exposure dose, or use a
less powerful UV lamp so that the duration of the exposure step is sufficiently long to
enable good control over the UV exposure step. After the PR is coated onto the sample
and pre-baked, underexpose the sample from the substrate side. Consequently, after
development, a thin PR layer remains on the etched region (substrate and part of the
sidewall). The unetched regions will then still be covered by a relatively thick PR layer.
The thin PR layer can be removed by RIE using an oxygen plasma (the etch rate is in
the order of /s), while the thick PR layer is not excessively etched. Finally, a standard
metal deposition and lift-off process are performed, as described in Section 7.2.2.
126

8.1 Summary and conclusions

In the course of this thesis, the contact resistance of aluminium contacts on poly-Si
films and poly-Si thin-film solar cells on glass was investigated. To the best of the
authors knowledge, this is the first ever contact resistance investigation of Al contacts
on evaporated poly-Si material for photovoltaic applications.

Various transmission line models (TLM) were employed to measure the specific (i.e.,
area-normalised) contact resistance. Based on conventional TLM structures, an
improved variable gap model was developed to increase the measurement accuracy and
to simplify the pattern fabrication process. Among all the models, the improved variable
gap TLM was found to provide the best measurement accuracy. However, the circular
TLM structure gave the best compromise between the fabrication complexity and the
measurement precision and hence was most frequently used in this thesis.

Due to the practical requirements of specific contact resistance measurements on
materials with high sheet resistance, the TLM patterns must be fabricated as small as
possible. A number of process control methods/procedures were developed and some
multifunctional photomasks were designed to pattern the TLM structures with a
minimum feature size of 3 m on rough glass substrates using the available equipment
infrastructure. A Kelvin sense tester was set up in the course of this thesis to precisely
measure the contact resistance of micrometer-sized samples, using a wide
current/voltage range. A numeric approach was developed to facilitate the data analysis.

Before applying the TLM technique to poly-Si thin-film materials, it was first tested on
singlecrystalline silicon wafer samples. The specific contact resistance dependence on
the surface doping concentration was found to agree well with what is reported in the
literature. The thermal annealing process of the contacts was also optimised. It was
127

found that the temperature is the dominant parameter in improving the contact
resistance if the annealing duration is longer than 30 minutes.

Then the Al/poly-Si contact resistance on poly-Si films on glass (i.e., no p-n junctions)
was investigated, by using the verified TLM measurement system. The results revealed
that the Al/n
+
poly-Si contact resistance agrees with what is reported in the literature
using sc-Si and LPCVD-fabricated poly-Si materials. The results for the Al/p
+
poly-Si
contact resistance suggest that evaporated boron-doped SPC poly-Si has a different
surface property than sc-Si and LPCVD poly-Si materials. Next, all the obtained contact
resistance values were fitted using different Schottky barrier heights. The barrier heights
of Al contacts on p-type and n-type poly-Si were found to be in the range of 0.2-0.4 eV
and 0.7-0.85 eV, respectively. These results agree with the findings on sc-Si. As oxygen
contamination is commonly present in our poly-Si thin-film solar cells, Al contacts on
heavily oxygen contaminated samples were also investigated. It was found that oxygen
contamination improves Al/n-Si contacts but degrades Al/p-Si contacts. Furthermore,
the long-term stability of Al contacts on poly-Si was found to be good. The contact
annealing experiments discovered that 250C is the optimum baking temperature for
both types of the contacts.

After the successfully tests on both sc-Si wafers and poly-Si films, the TLM
measurement system was employed to measure the contact resistance of three types of
poly-Si thin-film solar cells, PLASMA, EVA and ALICIA. Surface degradation of
different extents was detected via I-V measurements on virgin back surface field layers
of these solar cells. This is due to the surface damage and dopant neutralisation caused
by the hydrogenation process during solar cell fabrication. In order to reliably measure
the contact resistance of BSF layers using the TLM technique, two approaches, contact
annealing and BSF surface etching, were utilised to minimise the anomalies caused by
surface degradation. However, for n-type BSF layers of ALICIA cells, metallisation
immediately forms ohmic contacts. Any contact or surface treatment was found to be
detrimental to these contacts. The specific contact resistance of Al contacts to p-type
BSF layers was below 110
-4
cm
2
, while for n-type ones it was in the order of 10
-3

cm
2
. These values are believed to be sufficiently low for the metallisation scheme of
our poly-Si thin-film solar cells. The contact resistance measurement was also
128

performed on the emitter layers of PLASMA and EVA cells. No surface degradation
was detected. However, the doping profile of the emitter layers was found to be
non-uniform. Good ohmic contacts with specific contact resistance values of below
110
-3
cm
2
could only be obtained on heavily-doped regions. Nevertheless, this
should not constitute a hazard to the interdigitated metallisation scheme for our
thin-film solar cells.

Finally, the concept of an innovative contact resistance measurement model was
introduced. The model is termed FCM, standing for Full-Area Circular Contact
Model. Theoretically, the FCM can overcome the measurement bottleneck of the TLM
and boost the measurement precision by at least several tens of times. A standard
fabrication procedure was described and some process controls were suggested to
accommodate various sample structures. However, due to time constraints, no
experimental results were presented in this thesis.

In conclusion, a contact resistance measurement station was constructed by the author
during the course of this thesis. The specific contact resistance of poly-Si thin-film solar
cells on glass was successfully and reproducibly measured. Generally, the contact
resistance is believed to be sufficiently low for our interdigitated metallisation scheme.
Some surface properties of poly-Si films were revealed by means of the contact
resistance. A novel contact resistance model was developed but has not yet
experimentally been tested.

8.2 Possible future work

The author believes that there are three projects worth further pursuing.

The first one comes from the Discussion Section of Chapter 5. The Schottky barrier
height is the figure of merit for the contact resistance. So far, the barrier heights for
Al/poly-Si contacts have not yet been directly measured. Such an investigation may also
reveal the possible problems introduced by the BSF surface degradation to the entire
solar cell and hence may further benefit the design of whole solar cells.
129

The second territory remaining to be perfected is the FCM structure described in
Chapter 7. Experimental results are indispensable to demonstrate the advantage of the
FCM over the TLM.

The last one is the contact resistance measurement on another UNSW thin-film solar
cell, ALICE. It includes the measurement on both the BSF layer and the emitter layer.
Due to the lack of samples, the contact resistance study on ALICE solar cell was not
conducted in this thesis.

As the ALICIA solar cell was recently put on hold by the group due to the lack of
sufficient resources, there is no need to investigate its emitter contact resistance for the
time being.

List of symbols
130

List of symbols

Symbol Description Unit
A Contact area cm
2
d The spacing between the neighbouring metal bars/circles in
the transmission line models
cm
D
it
Interface state density eV
-1
-cm
-2
E
g
Energy bandgap of semiconductor eV
h Planck constant J-s
J Current density A/cm
2
J
mp
Current density at maximum power point A/cm
2
L Half length of the metal bar in the transmission line models cm
L
T
Current transfer length cm
m
*
Effective mass kg
n The number of semiconductor gaps between pads a and b in
improved ladder network structure
--
N
D
Donor impurity concentration cm
-3
p
bl
Fractional power loss due to lateral current flow in resistive
BSF layer
%
p
cf
Factional power loss due to contact resistance %
p
el
Fractional power loss due to lateral current flow in resistive
emitter layer
%
p
rbf
Factional power loss due to resistive BSF metal fingers %
p
ref
Fractional power loss due to resistive emitter metal fingers %
p
sf
Fractional power loss due to shading by emitter fingers %
q Unit electronic charge = 1.6 10
-19
C C
r Radius of the outer circle of the semiconductor ring in the
circular transmission line model
cm
R
C
Contact resistance
R
E
Contact end resistance

List of symbols
131

R
etched
Sheet resistance of the removed silicon layer in sheet
resistance profiling
/
R
remaining
Sheet resistance of the remaining silicon layer in sheet
resistance profiling
/
R
s
Lumped series resistance -cm
2
R
semi
Resistance arising from the semiconductor sheet in between
two metal contacts
R
sheetB
Sheet resistance of back surface field layer /
R
sheetM
Sheet resistance of emitter layer /
R
sheetMB
Sheet resistance of back surface field metal fingers /
R
sheetME
Sheet resistance of emitter metal fingers /
R
tot
Sheet resistance of the sample before each etching step in
sheet resistance profiling
/
R
total
Total system resistance between two metal contacts sitting
on a semicondcutor sheet
S Distance between the middle points of the neighbouring

metal fingers; Spacing between metal pads b and c in
improved ladder network structure
cm
T Absolute temperature K
t Thickness of the contacting layer cm
t
etched
Thickness of the etched silicon layer in sheet resistance
profiling
cm
V Applied voltage V
V
mp
Generated voltage at maximum power point V
W
F
Metal finger width cm
Z Width of the metal bar in the transmission line models cm

List of symbols
132

Thickness of the interfacial layer cm
Permittivity of semiconductor F/cm, C/V-cm
i
Permitivity of the interfacial layer F/cm, C/V-cm
c
Specific contact resistance -cm
2
etched
Resistivity of the etched silicon layer in sheet resistance
profiling
-cm
0
Surface state neutral level V
bi
Built-in potential at equalibrium V
m
Metal work function V
s
Semiconductor work function V
s
Electron affinity V
B
Schottky barrier height V
Bn
Schottky barrier height on n-type semiconductor V
Bp
Schottky barrier height on p-type semiconductor V

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List of original contributions
139


[Remark: The term poly-Si used in this thesis refers to evaporated SPC poly-Si
thin-films on glass, fabricated for photovoltaic applications.]

- Developed an improved transmission line model using the variable gap structure
to improve the measurement accuracy and simplify the pattern fabrication
process.

- Measured the specific contact resistance of aluminium contacts on poly-Si
(p-type and n-type).

- Investigated the long-term stability of Al/poly-Si (p-type and n-type) contacts
stored in room ambient.

- Investigated the annealing effect at intermediate temperatures (150-350C) on
the contact resistance of Al/poly-Si (p-type and n-type) contacts.

- Demonstrated the improvement of the contact resistance arising from an
Al/SiO
x
/n
+
poly-Si contact structure.

- Investigated the doping level dependence of the specific contact resistance of
aluminium contacts on typical poly-Si and on heavily oxygen contaminated
poly-Si (p-type and n-type).

- Indirectly determined the Schottky barrier heights of Al/poly-Si contacts (p-type
and n-type) via the measurement of the specific contact resistance and the
doping level (resistivity).

- Utilising coloured HF etching of the poly-Si surface and contact annealing to
minimise the hydrogenation-induced surface degradation.
140

- Measured the contact resistance of the back surface field layers of PLASMA,
EVA and ALICIA poly-Si thin-film solar cells, as well as the emitter layers of
PLASMA and EVA poly-Si thin-film solar cells.

- Proposed a novel contact resistance measurement model (FCM) to significantly
boost the measurement precision.
List of publications
141

List of publications

Journal papers

- D. Inns, L. Shi, and A.G. Aberle, Silica nanospheres as back surface reflectors
for crystalline silicon thin-film solar cells, Progress in Photovoltaics (2008, in
press).

Conference papers

- L. Shi, T. Walsh, D. Di and A.G. Aberle, Al/Si contact resistance study on
evaporated solid-phase crystallised poly-Si thin-films on glass, Proceedings
22nd European Photovoltaic Solar Energy Conference, Milan, Italy, Sep. 2007,
pp. 2048-51.

- A.G. Aberle, P. Widenborg, P. Campbell, A. Sproul, M. Griffin, J. Weber, D. Inns,
M. Terry, T. Walsh, O. Kunz, S. He, B. Hoex, L. Shi, T. Sakano, F. Bamberg, S.V.
Chan, D. Di, E. Mitchell, Y. Zhou, F. Fecker, S. Pohlner, Poly-Si on glass
thin-film PV research at UNSW, Conference Proceedings 22nd European
Photovoltaic Solar Energy Conference, Milan, Italy, Sep. 2007, pp. 1884-89.

- O. Kunz, J. Wong, T.M. Walsh, D. Di, L. Shi, and A.G. Aberle, Elimination of
severe shunting problems due to air-side electrode formation on evaporated
poly-Si thin-film solar cells on glass (EVA), abstract submitted to the 33rd
IEEE Photovoltaic Specialists Conference, San Diego, California, U.S.A, May
2008.
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