Lecture 5 ECE 425

Lecture 6 -- Clocked Structures and Latches

Lecture 5 ECE 425
Outline
Efficient XOR circuits
Tri-state buffers
Clocking
Latches
Lecture 5 ECE 425
XOR
Recall that XOR is a maximally-bad function to implement
with AND/OR gates
Cleverer circuit
Note that does not always provide active drive -- have
to be careful about putting in series
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Tri-State Inverter
Has high-impedance (disconnected) state
In
Enable
Out
Lecture 5 ECE 425
Clocking
So far, weve seen combinational circuits -- data flows
from input to output directly
Most useful circuits are sequential -- they involve
feedback and memory
Finite State Machines are an important class of sequential
circuit
We control timing of sequential circuits with a centralized
clock signal
Sequential Logic
2 storage mechanisms
positive feedback
charge-based
COMBINATIONAL
LOGIC
Registers
Outputs
Next state
CLK
Q D
Current State
Inputs
Naming Conventions
In our text:
A latch is a level sensitive device
An edge-triggered element is a register
Any bistable component (cross-coupled gates) is a flip-flop
There are many different naming conventions
For instance, many books call edge-triggered elements flip-flops;
this leads to confusion however
Memory classification
Foreground (embedded into logic: registers)
Background (large arrays)
Memory classification
Static / Dynamic
Timing Definitions
t
CLK
t
D
t
c 2 q
t
hold
t
setup
t
Q
DATA
STABLE
DATA
STABLE
Register
CLK
D Q
Characterizing Timing
Register
Latch
Clk
D Q
t
C 2 Q
Clk
D Q
t
C 2 Q
t
D 2 Q
Maximum Clock Frequency
F
F

s
LOGIC
t
p,comb

Also:
t
cdreg
+ t
cdlogic
> t
hold
t
cd
: contamination delay =
minimum delay
Data is hold long enough
so it can be output
t
clk-Q
+ t
p,comb
+ t
setup
= T
Latch versus Register
Latch
stores data when
clock is low
D
Clk
Q
D
Clk
Q
Register
stores data when
clock rises
Clk Clk
D
D
Q Q
Latches
In
clk
In
Out
Positive Latch
CLK
D
G
Q
Out
Out
stable
Out
follows In
In
clk
In
Out
Negative Latch
CLK
D
G
Q
Out
Out
stable
Out
follows In
transparent
transparent
In
clk
In
Out
Positive Latch
CLK
D
G
Q
Out
Out
stable
Out
follows In
In
clk
In
Out
Negative Latch
CLK
D
G
Q
Out
Out
stable
Out
follows In
Latch-Based Design
N latch is transparent
when = 0
P latch is transparent
when = 1
N
Latch
Logic
Logic
P
Latch

Writing into a Static Latch

D
CLK
CLK
D
Converting into a MUX
Forcing the state
(can implement as NMOS-only)
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
CLK
D
Q
Mux-Based Latches
Negative latch
(transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
CLK
1
0 D
Q
0
CLK
1 D
Q
In Clk Q Clk Q + = In Clk Q Clk Q + =
Mux-Based Latch
Number of transistor that the clock has to drive is an important metric.
In this case, there are 4 (four) transistors in the CLK line
CLK
CLK
CLK
D
Q
Master-Slave Register
Multiplexer-based latch pair
Q
M
Q
D
CLK
T
2
I
2
T
1
I
1
I
3
T
4
I
5
T
3
I
4
I
6
Lecture 5 ECE 425
Complimentary Single-Phase Clocking
Back-to-back level-sensitive latches create an edge-
triggered latch
This implementation requires that true and inverted
clock signals be exactly synchronous
Lecture 5 ECE 425
Complimentary Single-Phase Clocking
In practice, this never happens
Lecture 5 ECE 425
Two-Phase Clocking
Use non-overlapping clocks to tolerate skew
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Generating Two-Phase Clocks
Could take two clock inputs from off chip
More often, want single-phase external clock signal
Lecture 5 ECE 425
Recommended Clocking Strategies
Single-phase clocking should be used with purely static
logic
Mainly used in gate array/standard cell designs
Two-phase clocking is better when you have RAMs,
PLAs, or other structures as well as static gates
Well use two-phase clocking in the MPs
In high-speed designs, generating non-overlapping clocks
is difficult, and eats into cycle time
More and more high-performance designs are using
single-phase clocking
Can exploit pipeline structure to make single-phase
clocking work better
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Pipeline Design With Latches
Simple, but requires even division of logic between stages
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Pipeline Design With Level-Sensitive Latches
Can borrow time from one stage to the next
Requires that the longest path between two latches of
the same phase be < cycle time
Lecture 5 ECE 425
Clock Distribution
Want to minimize skew between clock edges at any two
points on chip
Lecture 5 ECE 425
Clock Distribution in Modern Chips
Getting harder and harder to generate global clocks with
acceptable skew
Wire delays becoming large relative to cycle time
Process, temperature, etc. cause variances in
performance of different clock buffers
Many designs starting to use Globally Asynchronous,
Locally Synchronous (GALS) approach
Divide chip into regions
Within a region, use single clock
Between regions, add circuits to deal with clock skew
Also used to clock different regions of chip at different
rates
Lecture 5 ECE 425
Static Latch Structures
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Edge-Triggered Latch With Cross-Coupled Inverters
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Dynamic Latches Require Fewer Transistors
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Wrapping Up
Reading -- Section 1.4.7, 7.1-7.4
Next time: Gate and Circuit Delay