Lecture 8 ECE 425

Lecture 8 -- Gate-level Delay Estimation

Lecture 8 ECE 425
Outline
Estimating delay of single gates and multi-gate circuits
Lecture 8 ECE 425
Talking About Delays
Three common measurements of gate performance:
Delay time (t
d
or t
pd
) -- Delay between when the input
signal to a gate reaches the 50% point and when the
output signal reaches the 50% point.
Rise time (t
r
) -- time it takes for a signal to go from 10% to
90% of its output range
Fall time (t
f
) -- time it takes for a signal to go from 90% to
10% of its output range
Lecture 8 ECE 425
Pictorial View
Lecture 8 ECE 425
Why do we care?
Its pretty obvious why we care about gate delay, in that
we like circuits to go fast
Rise/fall times matter for a number of reasons
Theyre a component of total gate delay
While the inputs to a gate are rising or falling, a
conductive path exists between power and ground
Power dissipation
Can potentially harm the chip if too much current
flows
For signals that have high inductance, overly short
rise/fall times can lead to di/dt-induced swings
Mostly relevant on chip I/O pins
Lecture 8 ECE 425
Estimating Delay
Gate delays are determined by how quickly the driving
gate can charge/discharge its load capacitance
Lecture 8 ECE 425
Estimating Delay
Gate delay may vary depending on which inputs are
changing -- generally use the worst case
Lecture 8 ECE 425
General Approach
Divide circuit into DC-connected components, solve for
each component
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Fall Time Analysis
During the fall time one or more nMOS transistors
discharge the energy stored in the output capacitance
Lecture 8 ECE 425
Fall Time Analysis
During the fall time, the nMOS transistor starts in the
saturated region and passes into the linear region
Lecture 8 ECE 425
Fall Time Analysis
Divide fall time into two components: t
f,sat
and t
f,linear
In saturation, current through the transistor is constant
Lecture 8 ECE 425
Fall Time
This becomes
Define t
1
, t
2
such that V
o
(t
1
) = 0.9V
dd
and V
o
(t2) = V
dd
- V
t
.
Then,
And t
f, sat
is:
Lecture 8 ECE 425
Fall Time
In the linear region, current through the transistor
depends on V
o
And t
f, linear
becomes
Lecture 8 ECE 425
Fall Time
Integrating, we get t
f, linear
=
And
For many processes, V
t
~= 0.2V
dd
, allowing us to
approximate
Lecture 8 ECE 425
Rise Time
Redoing the same analysis for the pMOS transistor in pull-
up gives
Note that beta for pMOS tends to be about 1/2 beta for
nMOS given equivalent size devices, so typically want
pMOS about twice as wide as nMOS to get equivalent
rise and fall times
Lecture 8 ECE 425
Gate Delay Estimation
Somewhat more complicated -- depends on rise and fall
times of the input signals.
Assuming (unrealistically) that the input rises or falls in
zero time, then the gate delay can be approximated as
half of the rise or fall time for the gate, and averaged to
Since gates are generally driven by other gates, we need
a better approximation for real circuits
Could just simulate the design, but that wouldnt give
much insight
Simulation is good for verifying that something works
the way you want but not for designing it to do so
Lecture 8 ECE 425
Circuit Delay Estimation
1. Divide circuit into DC-connected blocks as we talked
about at the start of lecture.
2. Compute a simple delay model for each block
3. Add the delays for each block to get overall delay.
In CMOS, a DC-connected block (stage) will be either:
1. A single logic gate
2. A transmission-gate network and the gates driving it
In the simple case, a block switches in response to a single
signal changing at one of its inputs, called the trigger
signal
Lecture 8 ECE 425
Making the System Tractable
As weve seen, solving even simple transistor networks
analytically requires solving differential equations that
change at region boundaries
For example, the rise and fall time derivations we
presented really only apply for inverters, and
computing them for larger gates is more complex
Now think about doing that for a 100-transistor
network, much less anything bigger
Solution: linearize the transistor equations by replacing
each transistor with an equivalent resistor, R
eff
Lecture 8 ECE 425
Computing R
eff
R
eff
for a transistor depends on what region its operating
in
Example: R
eff
= dV
ds
/dI
ds
= infinity in saturation
In linear region,
During switching, a transistor travels through different
regions of operation
We want a single R
eff
that approximates the behavior of a
transistor during the entire rise/fall time
R
eff
will be different depending on whether the
transistor is transmitting a zero or a one.
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Case One -- nMOS Transistor, Logic 0
nMOS transistor, discharging capacitor to ground
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nMOS Transistor, Logic 0
Want to model as a single network with R
eff
, C
Choose R
eff
so that both circuits have the same fall time
Lecture 8 ECE 425
nMOS Transistor, Logic 1
Back to the I-V curve
Lecture 8 ECE 425
nMOS Transistor, Logic 1
Problem: V
O
never makes it to 0.9 V
dd
in this case,
assuming V
t
= 0.2V
dd
, so cant try to match the full rise
time
If we try to match the time it takes to hit 0.5V
dd
, we get
Note that this is about 3x larger than the discharging
case. Why does this make sense?
Lecture 8 ECE 425
pMOS Transistors
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Estimating Stage Delay
Need to decide whether each transistor is off, transmitting
a logic 0, or transmitting a logic 1.
Then, can replace the stage with an RC network
Lecture 8 ECE 425
Estimating Stage Delay
This is still too complex -- solving these networks exactly
requires solving several simultaneous differential
equations.
Simplify further by reducing to an equivalent single-RC
network with time constant
Lecture 8 ECE 425
Example of the Process
Lecture 8 ECE 425
Estimating Stage Delay
At most one node should be the input node to the stage,
corresponding to either V
dd
or V
ss
Generally, were interested in the delay at a specific
output node
Question: how to compute R
eq
and C
eq
?
When the RC-network is a tree (no loops), there is a good
estimate that is also easy to compute.
This estimate of is called the Elmore Time
Constant
Lecture 8 ECE 425
Estimating the Stage delay
1. Identify an input node and an output node, and the
unique path between them. Call the path P
2. For every node n in the tree other than the input node
1. Identify the unique path between the input node and n
2. Identify the sub-path that is the intersection of this
path and P
3. Sum the resistances along the sub-path, call it R
n
4. If Cn is the capacitance at n, create a !
n
= R
n
C
n
3. Sum the !
n to get
!
eq
for the network
4. Given !
eq
, can select R
eq
and C
eq
values to match, but
generally dont need to, !
eq
is enough
Lecture 8 ECE 425
Example
Lecture 8 ECE 425
Example
Lecture 8 ECE 425
One Note
If a node n is already at the voltage it will have after the
transition, set !
n
= 0, since the node will not be charging
or discharging
Example:
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Cascade of Stages
Suppose stage 1 feeds stage 2
If the time constant of stage 1 is !
1
, when is stage 2
triggered? (I.e., when does it start switching)
Time for yet another approximation
Lecture 8 ECE 425
Cascade of Stages
By convention, assume that stage 2 is triggered when the
output of stage 1 has completed 90% of its logic swing
and is thus well within V
t
of one of the rails
Thus, the delay through stage 1 is
Thus, if stage 1 triggers at time 0, stage 2 triggers at time
2.3 !
1
, stage 3 triggers at time 2.3 !
1
+ 2.3 !
2
, etc.
Lecture 8 ECE 425
Interconnect Delay
Interconnect delay can be a big issue, particularly for
systems larger than a few gates
Interconnect delay is a function of interconnect length
To be fully accurate, youd treat interconnects as
transmission lines and analyze them that way
Were not going to do that, surprise surprise
Lecture 8 ECE 425
Interconnect Delay
Instead, break long lines into lumped RC-segments
Lecture 8 ECE 425
Interconnect Delay
Lecture 8 ECE 425
Interconnect Delay
Lecture 8 ECE 425
Rules of Thumb
Formally, lowest delay of an interconnect occurs when the
delay of each wire segment equals the delay of the buffer
With this model, interconnect delays become linear, not
quadratic
Lecture 8 ECE 425
Next Time
Logical effort: a way of making circuits fast, not just
knowing how slow they are.