PE Lab Manual 2013 Autonomous

1
POWER ELECTRONICS
Laboratory Manual

Department of Electrical and Electronics Engineering

Gokaraju Rangaraju I nstitute of Engineering & Technology
BACHUPALLY, MIYAPUR, HYDERABAD-500072

2

POWER ELECTRONICS
LABORATORY

Name:______________________________
Roll No:_________________ Section:____
Branch:____ Academic year:___________

Gokaraju Rangaraju I nstitute of
Engineering & Technology
BACHUPALLY, MIYAPUR, HYDERABAD-500072
3

CONTENTS
Name of the experiment PAGE NO
1) Generation of Cosine Waveform 4
2) Design of DC power supply circuit 7
3) Inverse Cosine control Scheme 10
SIMULATION CIRCUITS
4) 1-Phase Half Wave controlled converter with R-load 16
5) 1-Phase Half Wave controlled converter with RL-load 20
6) 1-Phase Full controlled converter with R-load 24
7) 1-Phase Full controlled converter with RL-load 28
8) 1-Phase semi converter with RL-load 33
9) 1-Phase AC Voltage controller with R-Load 37
10) 1-Phase AC voltage controller using RL-load 41
11) 1-Phase Cyclo converter using R-Load 45
12) 555- Timer Triggering circuit 49
HARDWARE DESIGN CIRCUITS USING THE TRIGGERING CIRCUITS
PROJECT WORK
13) AC voltage controller Using UJT triggering circuit 54
14) Semi converter using UJT triggering circuit 57
15) Full controlled converter Using UJT Triggering circuit 60
16) Basic Step Down chopper using 555 Timer 63
17) Basic Step up chopper using 555-Timer 66
18) Semi Converter using Inverse Cosine Control scheme 69
19) Half wave controlled converter using Inverse Cosine control scheme 72
20) Full controlled converter using Inverse Cosine control scheme 75

4

EXPERIMENT-1
GENERATION OF COSINE WAVEFORM
AIM: To Generate cosine waveform
APPARATUS:
230V AC supply
230/8-0-8 Center tapped Transformer
10k resistor
0.22uF, 63V capacitor
47uF, 63V capacitor
GPCB
BURGER STICKS
CRO
CRO probes -2

CIRCUIT DIAGRAM:

5

THEORY:
Generation of the cosine wave form is required for the inverse cosine control scheme. Usually adopted in line
commutated thyristor control circuits.
WAVEFORMS:

6

Waveforms:

Result:

7

EXPERIMENT-2
DESIGN OF DC-POWER SUPPLY
AIM: Design of DC- power supply circuit
APPARATUS:
PCB
Center tapped transformer 230/15-0-15
230V AC power supply
7812, 7912 voltage regulators
1N4007 Diodes
1000uF, 35V capacitors 2
220uF, 35V capacitors 2
0.1uf capacitors 4
CRO
CRO probes
JUMPERS
CIRCUIT DIAGRAM:

8

THEORY:
The circuit Diagram for generation of 12V DC power supply is shown. It consists of AC
supply, center tapped transformer, diode bridge rectifier, voltage regulators, capacitors.
230V, 50Hz AC supply is given to primary side of center tapped transformer. This voltage is stepped
down to a voltage of 15VAC, 50Hz which is available at the secondary side of the transformer. This
15VAC voltage is converted to DC voltage by using a diode bridge rectifier as shown. The capacitors
are used to eliminate the filters and Harmonics. The output voltage (15V) of bridge rectifier is
regulated to 12DC by using voltage regulators 7812 and 7912.
We can observe the +12V DC at the output terminal of regulator 7812 and -12V DC at the output
terminal of regulator 7912.

WAVEFORMS:

9

Waveforms:

Result:

10

EXPERIMENT-3
INVERSE COSINE CONTROL SCHEME
AIM: Design of Firing Circuit to Trigger a Thyristor using Inverse cosine method
APPARATUS:
Transformers 230/12-0-12 2
CRO probes, CRO
Connecting wires, multimeter
Soldering Rod, lead
Resistors:
2.2k 4 0.5w
10k 4 0.5w
47k 4 0.5w
4.7k 3
820k 2
27k 2
22k 4
3.3 ohms 2
220 ohms 2
1k 6
100 ohms 4
Potentiometer
10K 1 1w
Capacitors:
0.022pf 2
0.1uf 2
47uf 2
DIODES: 1N4148 14
Z10 2
ICS
LM741 2
11

LM339 1
LM555N 2
Transistors:
2222A 2
2218 2
Pulse Transformer
1:1:1 2
IC bases:
16 pin 1
8 pin 4
Burg sticks 4 strips

12

CIRCUIT DIAGRAM:

13

THEORY:
The circuit diagram of firing pulse generation is as shown in above figure. Firing
pulses are generated by using inverse cosine control scheme. Cosine wave is given as
input to this firing circuit .This is compared with the DC voltage to generate firing
pulses. The pulses in the positive half cycle are generated by comparing the Inverse
cosine wave with the DC voltage and pulses in the negative half cycle are generated by
comparing the cosine wave with the DC voltage. By varying the DC voltage value
from +12v to -12v the firing angle is varied accordingly. These pulses are given as
triggering pulses to the Thyristors.

WAVEFORMS:
Case1: Firing angle () <

Case2: Firing angle () =

14

Case3: Firing angle () >

15

Waveforms:

Result:

16

Experiment No 4
1-PHASE HALF WAVE CONTROLLED CONVERTER
WITH R-LOAD

Aim: To study the performance of a single phase half wave controlled converter
with R-load.

Apparatus: 1. Power Electronics Trainer Kit
2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; the SCR is forward biased. Then
current through the load and voltage drop across the load are zero, and all the
supply voltage appears between the anode and cathode of the SCR. Let the SCR be
triggered at an angle of (0<<).Then the supply terminals are connected to the
load through the SCR and the current starts flowing through the load via SCR.
Therefore the supply appears across the load with a drop of R and the voltage drop
across the SCR is zero (SCR is assumed ideal).
In the period <t<2; the SCR is Reversed biased and the SCR cannot conduct. The
voltage drop across the load is zero and the total supply voltage appears the SCR.
Again during the third positive Half cycle supply is positive again SCR is forward
biased and if we give triggering SCR starts conducting and this cycle repeats.

17

Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Give the firing pulses accordingly at a suitable firing angle from the firing circuit.
3. Observe the load voltage on the CRO and note down the firing angle.
4. Draw the waveforms and calculate the Average and RMS value of output voltage.
Calculations:

18

WAVEFORMS:

19

Waveforms:

Result:

20

Experiment No 5
1-PHASE HALF WAVE CONTROLLED CONVERTER
WITH RL-LOAD
Aim: To study the performance of a single phase half wave controlled converter
with RL-load.

2. Firing Circuit
3. CRO
4. CRO probes

Circuit Diagram: Vs = 1-Phase 50Hz, 230V supply

Theory:
In the period 0 < ts /; the SCR is forward biased. Then current through the load
and voltage drop across the load are zero, and all the supply voltage appears
between the anode and cathode of the SCR. Let the SCR be triggered at an angle of
(0<</).Then the supply terminals are connected to the load through the SCR
and the current starts flowing through the load via SCR. Therefore the supply
appears across the load and the voltage drop across the SCR is zero (SCR is
assumed ideal).
In the period /<t<2/; the SCR is Reversed biased but due to the presence
21

of Inductor, energy is stored during the positive Half cycle and this stored energy is
supplied to the SCR to remain in conducting mode even if the supply is negative.
This amount of energy stored depends on the value of inductor. That is more the
value of inductor more is the energy stored and SCR will remain in conducting state
up to the angle . The load current continues to flow until the energy stored in the
Inductor becomes zero.
After the current becomes zero SCR is reverse biased and load voltage is Zero
hence, total supply voltage appears across the SCR up to 2.
Again during the third positive Half cycle supply is positive, SCR is forward biased
and if we give triggering SCR starts conducting and this cycle repeats.
Here is called Extinction Angle.

Procedure:
3. Observe the load voltage on the CRO and note down the firing angle and Extinction
angle.
Calculations:

22

WAVEFORMS:

23

Waveforms:

Result:

24

Experiment No 6
1-PHASE FULL CONTROLLED CONVERTER WITH R-
LOAD
Aim: To study the performance of a single phase Full wave controlled converter
with R-load.
2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; the SCRs T1 and T2 are forward
biased and the SCRs T3 and T4 are reverse biased. Then current through the load
and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at
25

an angle of (0<</).Then the supply terminals are connected to the load
through the SCRs and the current starts flowing through the load via SCRs T1 and
T2. Therefore the supply voltage appears across the load with a drop of R and the
voltage drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).
In the period (/<t<2/); the SCRs T1 and T2 are Reversed biased hence cannot
conduct and T3 and T4 are forward biased. When they are triggered at an angle of
(+)/
[0< (+)/ <2/ ]. Then the supply terminals are connected to the load through
the SCRs and the current starts flowing through the load via SCRs T3 and T4.
Therefore the supply voltage appears across the load with a drop R and the voltage
drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).These SCRs continue to conduct up to 2/ .
Again during the third positive Half cycle supply is positive and SCRs T1 and T2
are forward biased, if we give triggering SCRs start conducting and this cycle
repeats.

Procedure:
Calculations:

26

WAVEFORMS:

27

Waveforms:

Result:

28

Experiment No 7
1-PHASE FULL CONTROLLED CONVERTER WITH RL-
LOAD

Aim: To study the performance of a single phase Full wave controlled converter
with RL-load.

2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; the SCRs T1 and T2 are forward
biased and the SCRs T3 and T4 are reverse biased. Then current through the load
and voltage drop across the load are zero. Let the SCRs T1 and T2 be triggered at
an angle of (0<</).Then the supply terminals are connected to the load
through the SCRs and the current starts flowing through the load via SCRs T1 and
T2. Therefore the supply voltage appears across the load and the voltage drop
29

across the SCRs is zero when they are conducting (SCR is assumed ideal).
In the period ( /<t<2/); the SCRs T1 and T2 are Reversed biased ;the SCRs
are Reversed biased, but due to the presence of Inductor, energy is stored during the
positive Half cycle and this stored energy is supplied to the SCRs to remain in
conducting mode even if the supply is negative.
This amount of energy stored depends on the value of inductor. That is, more the
value of inductor more is the energy stored and SCRs will remain in conducting
state up to the angle for Discontinuous conduction mode (<+). T3 and T4 are
forward biased. When they are triggered at an angle of (+)/ [0< (+)/ <2/].
Then the supply terminals are connected to the load through the SCRs and the
current starts flowing through the load via SCRs T3 and T4. Therefore the supply
voltage appears across the load and the voltage drop across the SCRs is zero when
they are conducting (SCR is assumed ideal).These SCRs continue to conduct up to
(+)/ .

Again during the third positive Half cycle supply is positive and SCRs T1 and T2
are forward biased, if we give triggering SCRs start conducting and this cycle
repeats.
For continuous conduction a high value of Inductor is chosen and before the load
current reaches zero value the next pair of Thyristors are triggered and hence the
current flows continuously ( >+)
Procedure:
3. Observe the load voltage on the CRO and note down the firing angle and Extinction
angle.

30

Calculations:

31

WAVEFORMS:

32

Waveforms:

Result:

33

Experiment No 8
1-PHASE SEMI CONVERTER WITH RL-LOAD
Aim: To study the performance of a single phase Semi converter with RL-load.
2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; the SCRs T1 and Diode D1 are forward biased and the
SCR T2 and Diode D2 are reverse biased. Then current through the load and
voltage drop across the load are zero. Let the SCR T1 be triggered at an angle of
(0<</).As the Diode D1 is already conducting the supply terminals are
connected to the load through the SCR and Diode, the current starts flowing
through the load via SCR T1 and Diode D1. Therefore the supply voltage appears
across the load, the voltage drop across the SCR and the Diode is zero when they
are conducting (SCR, Diode are assumed ideal).
Soon after / load voltage tends to reverse, Free wheeling Diode gets forward
biased and starts conducting. The load, or output current is transferred from T1, D1
to FWD. As SCR T1 is reverse biased at t = /
+
current flows through FWD and
T1 is turned off. The load terminals are short circuited through FWD therefore load
voltage is zero during [/<t< (+) /]. During the period (/<t<2/); T2 and
Diode D2 are forward biased. When T2 is triggered at an angle of (+) /, [0<
34

(+)/ <2/], then the FWD is reverse biased and is turned off. During this
period supply terminals are connected to the load through the SCR and the Diode
D2, the load current shifts from FWD to T2 and D2. Therefore the supply voltage
appears across the load. The voltage drop across the SCR and Diode is zero when
they are conducting (SCR, Diode are assumed ideal). SCR T2 and Diode D2
continue to conduct up to 2/ . For the next half cycle the load current is
transferred from T2 and D2 to the FWD and SCR T1 and Diode D1 are forward
biased, if we give triggering SCR starts conducting and this cycle repeats.

Procedure:
Calculations:

35

WAVEFORMS:

36

Waveforms:

Result:

37

Experiment No 9
1-PHASE AC VOLTAGE CONTROLLER WITH R-LOAD

Aim: To study the performance of a single phase AC Voltage controller with R-
load.

2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; The SCR T1 is forward biased and SCR T2 is reverse
biased. Let the T1 be triggered at an angle of (0<</ ).Then the supply
terminals are connected to the load through T1 and the current starts flowing
through the load via SCR. Therefore the supply appears across the load. During the
period (/<t<2/) T1 is reverse biased and T2 is forward biased and when we
give trigger pulse at an angle of (+) /, [0< (+)/ <2/] T2 starts conducting
and the load terminals are connected to supply through T2 hence the output voltage
is the supply voltage from the instant of triggering. This repeats for the every half
cycle.

38

Procedure:
4. Draw the waveforms and calculate the RMS value of output voltage.
Calculations:

39

WAVEFORMS:

40

Waveforms:

Result:

41

Experiment No 10
1-PHASE AC VOLTAGE CONTROLLER WITH RL-
LOAD

Aim: To study the performance of a single phase AC Voltage controller with
RL-load.

2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
In the period 0 < ts /; the SCRs T1 is forward biased and the SCR T2 is reverse
biased. Then current through the load and voltage drop across the load are zero. Let
the SCR T1 be triggered at an angle of (0<</).Then the supply terminals are
connected to the load through the SCR T1 and the current starts flowing through the
load via SCR T1. Therefore the supply voltage appears across the load and the
voltage drop across the SCRs is zero when they are conducting (SCR is assumed
ideal).
In the period ( /<t<2/); the SCR T1 is Reversed biased and T2 is forward
biased, but due to the presence of Inductor, energy is stored during the positive Half
cycle and this stored energy is supplied to the SCR to remain in conducting mode
even if the supply is negative.This amount of energy stored depends on the value of
inductor. That is, more the value of inductor more is the energy stored and SCR will
42

remain in conducting state up to the angle for Discontinuous conduction mode
(<+). T2 is forward biased. When it is triggered at an angle of (+)/ [0<
(+)/ <2/]. Then the supply terminals are connected to the load through the
SCR T2 and the current starts flowing through the load via SCR T2. Therefore the
supply voltage appears across the load and the voltage drop across the SCRs is zero
when they are conducting (SCR is assumed ideal).This SCR will continue to
conduct up to (+)/ .

Again during the third positive Half cycle supply is positive and SCR T1 is forward
biased and T2 is reverse biased, if we give triggering the forward biased SCR, it
starts conducting and this cycle repeats.
For continuous conduction a high value of Inductor is chosen and before the load
current reaches zero value the next Thyristor is triggered and hence the current
flows continuously ( >+)
Procedure:
4. Draw the waveforms and calculate the RMS value of output voltage.
Calculations:

43

WAVEFORMS:

44

Waveforms:

Result:

45

Experiment No 11
1-PHASE STEP DOWN CYCLO CONVERTER WITH R-
LOAD

Aim: To study the performance of a single phase Cyclo converter with R-load.
2. Firing Circuit
3. CRO

Circuit Diagram:

Theory:
Cyclo converter is a circuit which converts the input voltage at one frequency to the
output vtage at different frequecy.
During the positive half cycle Thyristors P1, N2 are forward biased and Thyristors
P2 and N1 are reverse biased. The circuit is designed for step down cyclo converter
for a output frequency of = .To get the desired frequency the Thyristors are
triggered accordingly.
During the first positive half cycle P1 and N2 are forward biased and to get the
positive output voltage, P1 is triggered at an angle of (+). During the next
positive half cycle P2 and N1 are forward biased, to get required output voltage
thyristor P2 is triggered. In the next half cycle P1 is triggered next N1,N2 and again
46

N1 are triggered accordingly. This process repeats.
Procedure:

47

WAVEFORMS:

48

Waveforms:

Result:

49

Experiment No 12
555- TIMER TRIGGERING CIRCUIT
Aim: To generate pulses using 555 Timer Circuit
2. Firing Circuit
3. CRO

Circuit Diagram:

Output

50

Theory:

The 555 has three main operating modes, Monostable, Astable, and Bistable. Each mode represents a
different type of circuit that has a particular output.

Astable mode :

An Astable Circuit has no stable state - hence the name "astable". The output continually switches
state between high and low without without any intervention from the user, called a 'square' wave.
This type of circuit could be used to give a mechanism intermittent motion by switching a motor on
and off at regular intervals. It can also be used to flash lamps and LEDs, and is useful as a 'clock'
pulse for other digital ICs and circuits.

Output Waveforms in Astable Mode:

Monostable mode

A Monostable Circuit produces one pulse of a set length in response to a trigger input such as a push
button. The output of the circuit stays in the low state until there is a trigger input, hence the name
"monostable" meaning "one stable state". his type of circuit is ideal for use in a "push to operate"
system for a model displayed at exhibitions. A visitor can push a button to start a model's mechanism
moving, and the mechanism will automatically switch off after a set time.
Output Waveforms in Monostable Mode:

51

Procedure:
1. Connect the firing circuit as shown in the circuit diagram
2. Simulate it using Multisim
3. Observe the pulses at the output
4. Vary the circuit parameters to observe the changes.

52

Waveforms:

Results:

53

HARDWARE CIRCUIT DESIGNS

54

Experiment No 13
AC VOLTAGE CONTROLLER USING UJT TRIGGERING
CIRCUIT

Aim:

Circuit Diagram:

55

56

57

Experiment No 14
SEMI CONVERTER USING UJT TRIGGERING
CIRCUIT
Aim:

Circuit Diagram:

58

59

60

Experiment No 15
FULL CONTROLLED CONVERTER USING UJT
TRIGGERING CIRCUIT
Aim:

Circuit Diagram:

61

62

63

Experiment No 16
BASIC STEP DOWN CHOPPER USING 555 TIMER
Aim:

Circuit Diagram:

64

65

66

Experiment No 17
BASIC STEP UP CHOPPER USING 555-TIMER
Aim:

Circuit Diagram:

67

68

69

Experiment No 18
SEMI CONVERTER USING INVERSE COSINE
CONTROL SCHEME
Aim:

Circuit Diagram:

70

71

72

Experiment No 19
HALF WAVE CONTROLLED CONVERTER USING
INVERSE COSINE CONTROL SCHEME
Aim:

Circuit Diagram:

73

74

75

Experiment No 20
FULL CONTROLLED CONVERTER USING INVERSE
COSINE CONTROL SCHEME
Aim:

Circuit Diagram:

76

77

78

DATA SHEETS

2N2222
MUR 110
1N4148
IRFZ44
LM 7815
TL 494C
LM339
LM555
TYN612
TL3843

PIN DESCRIPTION
1 emitter
2 base
3 collector, connected to case

NPN switching transistors 2N2222; 2N2222A

FEATURES

High current (max. 800 mA)
Low voltage (max. 40 V).

APPLICATIONS

Linear amplification and switching.
PINNING

DESCRIPTION
1
3

PNP complement: 2N2907A.
2

3
MAM264

1

Fig.1 Simplified outline (TO-18) and symbol.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CBO
collector-base voltage
2N2222
2N2222A
open emitter

60
75

V
V
V
CEO
collector-emitter voltage
2N2222
2N2222A
open base

30
40

V
V
I
C
collector current (DC) 800 mA
P
tot
total power dissipation T
amb
25 C 500 mW
h
FE
DC current gain I
C
= 10 mA; V
CE
= 10 V 75
f
T
transition frequency
2N2222
2N2222A
I
C
= 20 mA; V
CE
= 20 V; f = 100 MHz

250
300

MHz
MHz
t
off
turn-off time I
Con
= 150 mA; I
Bon
= 15 mA; I
Boff
= 15 mA 250 ns


LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
V
CBO
collector-base voltage
2N2222
2N2222A
open emitter

60
75

V
V
V
CEO
collector-emitter voltage
2N2222
2N2222A
open base

30
40

V
V
V
EBO
emitter-base voltage
2N2222
2N2222A
open collector

5
6

V
V
I
C
collector current (DC) 800 mA
I
CM
peak collector current 800 mA
I
BM
peak base current 200 mA
P
tot
amb
25 C 500 mW
T
case
25 C 1.2 W
T
stg
storage temperature 65 +150 C
T
j
junction temperature 200 C
T
amb
operating ambient temperature 65 +150 C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 350 K/W
R
th j-c
thermal resistance from junction to case 146 K/W


CHARACTERISTICS
T
j
= 25 C unless otherwise specified.
I
CBO
collector cut-off current
2N2222

I
E
= 0; V
CB
= 50 V

10

nA
I
E
= 0; V
CB
= 50 V; T
amb
= 150 C 10 A
I
CBO
collector cut-off current
2N2222A

I
E
= 0; V
CB
= 60 V

10

nA
I
E
= 0; V
CB
= 60 V; T
amb
= 150 C 10 A
I
EBO
emitter cut-off current I
C
= 0; V
EB
= 3 V 10 nA
h
FE
DC current gain I
C
= 0.1 mA; V
CE
= 10 V 35
I
C
= 1 mA; V
CE
= 10 V 50
I
C
= 10 mA; V
CE
= 10 V 75
I
C
= 150 mA; V
CE
= 1 V; note 1 50
I
C
= 150 mA; V
CE
= 10 V; note 1 100 300
h
FE
DC current gain
2N2222A
I
C
= 10 mA; V
CE
= 10 V; T
amb
= 55 C

35

h
FE
DC current gain
2N2222
2N2222A
I
C
= 500 mA; V
CE
= 10 V; note 1

30
40

V
CEsat
collector-emitter saturation voltage
2N2222

I
C
= 150 mA; I
B
= 15 mA; note 1

400

mV
I
C
= 500 mA; I
B
= 50 mA; note 1 1.6 V
V
CEsat
collector-emitter saturation voltage
2N2222A

I
C
= 150 mA; I
B
= 15 mA; note 1

300

mV
I
C
= 500 mA; I
B
= 50 mA; note 1 1 V
V
BEsat
base-emitter saturation voltage
2N2222

I
C
= 150 mA; I
B
= 15 mA; note 1

1.3

V
I
C
= 500 mA; I
B
= 50 mA; note 1 2.6 V
V
BEsat
base-emitter saturation voltage
2N2222A

I
C
= 150 mA; I
B
= 15 mA; note 1

0.6

1.2

V
I
C
= 500 mA; I
B
= 50 mA; note 1 2 V
C
c
collector capacitance I
E
= i
e
= 0; V
CB
= 10 V; f = 1 MHz 8 pF
C
e
emitter capacitance
2N2222A
I
C
= i
c
= 0; V
EB
= 500 mV; f = 1 MHz

25

pF
f
T
transition frequency
2N2222
2N2222A
I
C
= 20 mA; V
CE
= 20 V; f = 100 MHz

250
300

MHz
MHz
F noise figure
2N2222A
I
C
= 200 A; V
CE
= 5 V; R
S
= 2 k ;
f = 1 kHz; B = 200 Hz

4

dB


Switching times (between 10% and 90% levels); see Fig.2
t
on
turn-on time I
Con
= 150 mA; I
Bon
= 15 mA; I
Boff
= 15 mA 35 ns
T
d
delay time 10 ns
T
r
rise time 25 ns
t
off
turn-off time 250 ns
T
s
storage time 200 ns
T
f
fall time 60 ns
Note
1. Pulse test: t
p
300 s; 0.02.

V
BB
V
CC

(probe)

R
B
R
C

V
o (probe)

oscilloscope oscilloscope
450

R2
V
i

DUT
450

R1

MLB826

V
i
= 9.5 V; T = 500 s; t
p
= 10 s; t
r
= t
f
3 ns.
R1 = 68 ; R2 = 325 ; R
B
= 325
; R
C
= 160 . V
BB
= 3.5 V; V
CC
= 29.5 V.
Oscilloscope input impedance Z
i
= 50 .

Fig.2 Test circuit for switching times.

w M A M B M


PACKAGE OUTLINE

Metal-can cylindrical single-ended package; 3 leads SOT18/13

j
seating plane

B

1
b

k
2
D
1

3

a

A D A L

0 5 10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT

A

a

b

D

D
1

j

k

L

w

mm
5.31
4.74

2.54
0.47
0.41
5.45
5.30
4.70
4.55
1.03
0.94
1.1
0.9
15.0
12.7

0.40

45

OUTLINE
VERSION
REFERENCES

IEC JEDEC EIAJ
EUROPEAN
PROJECTION
ISSUE DATE

SOT18/13

B11/C7 type 3

TO-18

97-04-18

MCC
Part Number
Maximum
Recurrent
Peak Reverse
Voltage

Maximum
RMS Voltage
Maximum DC
Blocking
Voltage
MUR105 50V 35V 50V
MUR110 100V 70V 100V
MUR115 150V 105V 150V
MUR120 200V 140V 200V
MUR140 400V 280V 400V
MUR160 600V 420V 600V
MUR180 800V 560V 800V
MUR1100 1000V 700V 1000V

Average Forward
Current
I
F(AV)
1 A T
A
= 55 C
Peak Forward Surge
Current
I
FSM
35A 8.3ms, half sine
Maximum
Instantaneous
Forward Voltage
MUR105-115
MUR120-160
MUR180-1100

V
F

.975V
1.35V
1.75V

I
FM
= 1.0A;
T
A
= 25 C
Max imum DC
Reverse Current At
Rated DC Blocking
Voltage

I
R

5 A
50 A

T
A
= 25 C
TA = 150 C
Maximum Reverse
Recovery Time
MUR105-120
MUR140-160
MUR180-1100

Trr

45ns
60ns
75ns

IF=0.5A, IR=1.0A,
I
rr
=0.25A
Typical Junction
Capacitance

C
J

20pF
Measured at
1.0MHz, VR=4.0V

M C C

MUR105
THRU
MUR1100

Features
High Surge Capability
Low Forward Voltage Drop
High Current Capability
Super Fast Switching Speed For High Efficiency

Maximum Ratings
Operating Temperature: -50 C to +150 C
Storage Temperature: -50 C to +150 C

1 Amp Super Fast
Recovery Rectifier
50 to 1000 Volts

DO-41

D

Electrical Characteristics @ 25 C Unless Otherwise Specified

A
Cathode
Mark

B

D

C

DIMENSIONS

DIM

INCHES

MM

NOTE MIN MAX MIN MAX
A .166 .205 4.10 5.20

B .080 .107 2.00 2.70

C .028 .034 .70 .90

D 1.000 --- 25.40 ---

*Pulse Test: Pulse Width 300 sec, Duty Cycle 1%

T
J
= 25

C

MUR105 thru MUR1100
M C C

Figure 1
Typical Forward Characteristics
20

10

6

1.5

Figure 2
Forward Derating Curve

Amps

4

2

1

.6

.4

.2

.06

25 C

MUR105-115

MUR180-1100

MUR120-160

Amps

1.25

1.0

.75

.5

Single Phase, Half Wave
60Hz Resistive or Inductive Load

.04
0
25 50 75 100 125

150

175

.02

.01

.5 .7 .9 1.1 1.3 1.5
Volts

C

Average Forward Rectified Current - Amperes versus
Ambient Temperature - C
Instantaneous Forward Current - Amperes versus
Instantaneous Forward Voltage - Volts

Figure 3
Junction Capacitance

100

60

40

20
pF
10

6
4

2

1
.1 .2 .4

1 2 4
Volts

10 20 40

100 200

400 1000

Junction Capacitance - pF versus
Reverse Voltage - Volts

www.mccsemi.com

www.mccsemi.com

T
A
= 15 0 C

T
A
= 100 C

25

C

MUR105 thru MUR110
M C C

100

60
40
Figure 4
Typical Reverse Characteristics

Figure 5
Peak Forward Surge Current
60

50

20

10

6

4

2

Amps 1

.6
40

30

Amps
20

10

0
1 2

4 6 8 10 20

Cycles

40 60 80 100

.4

.2

.1

.06

.04

T
A
=

Peak Forward Surge Current - Amperes versus
Number Of Cycles At 60Hz - Cycles

.02

.01
20

40 60 80 100

120

140

Volts

Instantaneous Reverse Leakage Current - MicroAmperes
versus

Figure 6
Reverse Recovery Time Characteristic And Test Circuit Diagram

50 10

+0.5A
trr

25Vdc

Pulse
Generator
Note 2
0
-0.25

1

Notes:
1. Rise Time = 7ns max.
Oscilloscope
Note 1
-1.0

1cm
Set Time Base for 20/100ns/cm
Input impedance = 1 megohm, 22pF
2. Rise Time = 10ns max.
Source impedance = 50 ohms
3. Resistors are non-inductive

TYPE NUMBER MARKING CODE
1N4148 1N4148PH or 4148PH
1N4448 1N4448

High-speed diodes 1N4148; 1N4448

FEATURES
Hermetically sealed leaded glass SOD27 (DO-35)

package
Hi gh switching speed: max. 4 ns

General application

Cont i nuous reverse voltage: max. 100 V

Repet i t i ve peak reverse voltage: max. 100 V

Repet i t i ve peak forward current: max. 450 mA.

APPLICATIONS
High-speed switching.

DESCRIPTION

The 1N4148 and 1N4448 are high-speed switching diodes
fabricated in planar technology, and encapsulated in
hermetically sealed leaded glass SOD27 (DO-35)
packages.

k a

The diodes are type branded.

Fig.1 Simplified outline (SOD27; DO-35) and
symbol.

MARKING

MAM246

ORDERING INFORMATION

TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
1N4148

hermetically sealed glass package; axial leaded; 2 leads SOD27
1N4448


LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
V
RRM
repetitive peak reverse voltage
100 V
V
R
continuous reverse voltage
100 V
I
F
continuous forward current see Fig.2; note 1
200 mA
I
FRM
repetitive peak forward current
450 mA
I
FSM
non-repetitive peak forward current square wave; T
j
= 25 C prior to

surge; see Fig.4
t = 1 s

t = 1 ms
t = 1 s

4
1
0.5

A
A
A
P
tot
amb
= 25 C; note 1
500 mW
T
stg
storage temperature 65
+200 C
T
j
junction temperature
200 C

Note
1. Device mounted on an FR4 printed-circuit board; lead length 10 mm.

ELECTRICAL CHARACTERISTICS
T
j
= 25 C unless otherwise specified.
V
F
forward voltage
1N4148
1N4448
see Fig.3
I
F
= 10 mA
I
F
= 5 mA
I
F
= 100 mA

0.62

1
0.72
1

V
V
V
I
R
reverse current V
R
= 20 V; see Fig.5 25 nA
V
R
= 20 V; T
j
= 150 C; see Fig.5
50 A
I
R
reverse current; 1N4448 V
R
= 20 V; T
j
= 100 C; see Fig.5
3 A
C
d
diode capacitance f = 1 MHz; V
R
= 0 V; see Fig.6
4 pF
T
rr
reverse recovery time when switched from I
F
= 10 mA to
I
R
= 60 mA; R
L
= 100 ;

measured at I
R
= 1 mA; see Fig.7

4 ns
V
fr
forward recovery voltage when switched from I
F
= 50 mA;
t
r
= 20 ns; see Fig.8

2.5 V

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-tp)
thermal resistance from junction to tie-point lead length 10 mm 240 K/W
R
th(j-a)
thermal resistance from junction to ambient lead length 10 mm; note 1 350 K/W

Note
1. Device mounted on a printed-circuit board without metallization pad.

(1) (2) (3)


GRAPHICAL DATA

300
mbg451
600
MBG464

I
F

(mA)
I
F
(mA)

200
400

100
200

0
0 100 200
T
amb
(C)

0
0 1
V
F
(V)
2

Device mounted on an FR4 printed-circuit board; lead length 10 mm.

Fig.2 Maximum permissible continuous forward
current as a function of ambient
temperature.
(1) T
j
= 175 C; typical values.
(2) T
j
= 25 C; typical values.
(3) T
j
= 25 C; maximum values.

Fig.3 Forward current as a function of forward
voltage.

10
2

MBG704

I
FSM
(A)

10

1

10
1
1

10 10
2

10
3

t
p
(s)

10
4

Based on square wave currents.
T
j
= 25 C prior to surge.

Fig.4 Maximum permissible non-repetitive peak forward current as a function of pulse duration.


10
3

I
R

mgd290

1.2
C
d

MGD004
(A)
10
2

(pF)

1.0

(1)
10
(2)

0.8

1

10
1

0.6

10
2

0 100

T
j
(C)

200
0.4

0 10
V
R
(V)
20

(1) V
R
= 75 V; typical values.
(2) V
R
= 20 V; typical values.
f = 1 MHz; T
j
= 25 C.

Fig.5 Reverse current as a function of junction
temperature.
Fig.6 Diode capacitance as a function of reverse
voltage; typical values.


D.U.T.
R
S
= 50
I
F

SAMPLING
OSCILLOSCOPE
t
r
t p

10%

t

I
F
t
rr
t
V = V
R
I
F
x R
S
R
i
= 50

V
R
MGA881

90%

input signal

output signal

(1)

(1) I
R
= 1 mA.

Fig.7 Reverse recovery voltage test circuit and waveforms.

I

R
S
= 50
1 k

D.U.T.
450

OSCILLOSCOPE
R
i
= 50

I
90%

V

V
fr

MGA882

10%

t
r

t
t p

input
signal

t

output
signal

Fig.8 Forward recovery voltage test circuit and waveforms.

UNIT
b
max.
D
max.
G
1
max.
L
min.

mm

0.56

1.85

4.25

25.4


PACKAGE OUTLINE

Hermetically sealed glass package; axial leaded; 2 leads SOD27

(1)

b

D L G
1
L

DIMENSIONS (mm are the original dimensions)
0 1 2 mm
scale

Note
1. The marking band indicates the cathode.

OUTLINE
VERSION
REFERENCES
EUROPEAN
PROJECTION

ISSUE DATE
IEC JEDEC JEITA

SOD27

A24

DO-35

SC-40

97-06-09
05-12-22

SYMBOL PARAMETER MAX. UNIT

V
DS
I
D
P
tot
T
j

R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance V
GS
= 10 V
55
49
110
175
22

V
A
W
C
m

PIN DESCRIPTION
1

2

3
tab
gate
drain
source
drain

N-channel enhancement mode IRFZ44N
TrenchMOS
TM
transistor

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
trench technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in switched mode
power supplies and general purpose
switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

d
tab

g

1 2 3
s

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
-
-
-
-
-
-
-
- 55
55
55
20
49
35
160
110
175
V
V
V
A
A
A
W
C

ESD LIMITING VALUE
V
C
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 k )
- 2 kV

THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb

R
th j-a
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-

in free air
-

60
1.4

-
K/W
K/W

TrenchMOS
TM
transistor

STATIC CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS

V
GS(TO)

I
DSS
I
GSS
V
(BR)GSS
R
DS(ON)
Drain-source breakdown
voltage
Gate threshold voltage

Zero gate voltage drain current

Gate source leakage current

Gate source breakdown voltage
Drain-source on-state
resistance
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175C
T
j
= -55C
V
DS
= 55 V; V
GS
= 0 V;
T
j
= 175C
V
GS
= 10 V; V
DS
= 0 V
T
j
= 175C
I
G
= 1 mA;
V
GS
= 10 V; I
D
= 25 A
T
j
= 175C
55
50
2.0
1.0
-
-
-
-
-
16
-
-
-
-
3.0
-
-
0.05
-
0.04
-
-
15
-
-
-
4.0
-
4.4
10
500
1
20
-
22
42
V
V
V
V

A
A
A
A
V
m
m

DYNAMIC CHARACTERISTICS
T
mb
g
fs
Forward transconductance V
DS
= 25 V; I
D
= 25 A 6 - - S
C
iss
C
oss
C
rss
Input capacitance
Output capacitance
Feedback capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz -
-
-
1350
330
155
1800
400
215
pF
pF
pF
Q
g
Q
gs
Q
gd
Total gate charge
Gate-cource charge
Gate-drain (miller) charge
V
DD
= 44 V; I
D
= 50 A; V
GS
= 10 V -
-
-
-
-
-
62
15
26
nC
nC
nC
t
d on

t
r
t
d off
t
f
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 10 V; R
G
= 10
Resistive load
-
-
-
-
18
50
40
30
26
75
50
40
ns
ns
ns
ns
L
d
L
d
L
s

Internal drain inductance
Internal drain inductance
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-

-

-
3.5

4.5

7.5
-

-

-
nH
nH
nH

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
I
DR

I
DRM

V
SD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage

I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
-

-
-
-
-

-
0.95
1.0
49

160
1.2
-
A

A
V
t
rr

Q
rr
Reverse recovery time
Reverse recovery charge
I
F
= 40 A; -dI
F
/dt = 100 A/ s;
V
GS
= -10 V; V
R
= 30 V
-
-
47
0.15
-
-
ns
C

TrenchMOS
TM
transistor

AVALANCHE LIMITING VALUE
W
DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
I
D
= 45 A; V
DD
25 V;
V
GS
= 10 V; R
GS
= 50 ; T
mb
= 25 C
- - 110 mJ

120
110
100
90
80
70
60
50
40
30
20
10
0
PD% Normalised Power Derating

0 20 40 60 80 100 120 140 160 180
Tmb / C
1000

ID/A

100

10

1

RDS(ON) =VDS/ID

DC

1 10

VDS/V

tp =
1 us
10us

100 us

1 ms

10ms
100ms

100
Fig.1. Normalised power dissipation.
PD% = 100 P
D
/P
D 25 C
= f(T
mb
)
Fig.3. Safe operating area. T
mb
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p

120
110
100
90
80
70
60
50
40
30
20
10
0

ID% Normalised Current Derating

10

1

0.1

0.01
Zth/(K/W)

0.5

0.2
0.1
0.05
0.02

0

PD
tp

T

D =
tp
T

t
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100 I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
10 V
0.001
1E-06 0.0001 0.01 1 100
t/s
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T

BUK959-60
BUK759-60
16

10
9

8.5

VGS/V =

VGS/V =

6

6.5

7

8
9

10

Tj/C = 175 25

max.

typ.

min.

TrenchMOS
TM
transistor

100

ID/A

80

60

40

20

0

0 2 4

VDS/V

6 8 10

8.0

7.5

7.0

6.5

6.0

5.5

5.0
4.5
4.0
30
gfs/S
25

20

15

10

5

0
0 20 40 60 80 100
ID/A
Fig.5. Typical output characteristics, T
j
= 25 C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V

RDS(ON)/mOhm
40

2.5
a

Rds(on) normlised to 25degC

35
2
30

25 1.5

20
1

15

10
0 10 20 30 40 50 60 70 80 90
ID/A
0.5
-100 -50 0 50 100 150 200
Tmb / degC
Fig.6. Typical on-state resistance, T
j
= 25 C.
R
DS(ON)
= f(I
D
); parameter V
GS

Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 C
= f(T
j
); I
D
= 25 A; V
GS
= 10 V

100

ID/A

80
VGS(TO) / V
5

4

60
3

40
2

20 1

0
0 2 4 6 8 10 12
VGS/V
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
0
-100 -50 0 50 100 150 200
Tj / C
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS

Tj/C =

175

25

VDS = 14V

VDS = 4 4V

T
h
o
u
s
a
n
d
s

p
F

+

TrenchMOS
TM
transistor

1E-01
Sub-Threshold Conduction
100

IF/A

80
1E-02

1E-03
2% typ 98%
60

40
1E-04

20
1E-05

1E-06

0 1 2 3 4 5
Fig.11. Sub-threshold drain current.
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSDS/V
Fig.14. Typical reverse diode current.
I
D
= f(V
GS)
; conditions: T
j
= 25 C; V
DS
= V
GS
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j

2.5

2

1.5

1

.5

0
0.01 0.1 1

VDS/V

Ciss

Coss
Crss
10 100

120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%

20 40 60 80 100 120 140 160 180
Tmb / C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 49 A

12
VGS/V

10

8

6

4

VGS

0

L

VDS

T.U.T.

VDD

-
-ID/100

2
RGS

R 01
shunt

0
0 10 20

QG/nC

30 40 50
Fig.13. Typical turn-on gate-charge characteristics.

Fig.16. Avalanche energy test circuit.
2
BV BV V

V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS

W
DSS
0.5 LI
D DSS DSS DD

TrenchMOS
TM
transistor

+
VDD
RD

VGS

0
VDS
-

RG
T.U.T.

Fig.17. Switching test circuit.

TrenchMOS
TM
transistor

MECHANICAL DATA

Dimensions in mm

Net Mass: 2 g

10,3
max

3,7

1,3

4,5
max

2,8

5,9
min

15,8
max

3,0 max
not tinned

1,3
max

1 2 3

3,0

13,5
min
(2x)

2,54 2,54
0,9 max (3x)

0,6
2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".

L
M
7
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May 2000

LM78XX
Series Voltage Regulators

General Description
The LM78XX series of three terminal regulators is available
with several fixed output voltages making them useful in a
wide range of applications. One of these is local on card
regulation, eliminating the distribution problems associated
with single point regulation. The voltages available allow
these regulators to be used in logic systems, instrumenta-
tion, HiFi, and other solid state electronic equipment. Al-
though designed primarily as fixed voltage regulators these
devices can be used with external components to obtain ad-
justable voltages and currents.
The LM78XX series is available in an aluminum TO-3 pack-
age which will allow over 1.0A load current if adequate heat
sinking is provided. Current limiting is included to limit the
peak output current to a safe value. Safe area protection for
the output transistor is provided to limit internal power dissi-
pation. If internal power dissipation becomes too high for the
heat sinking provided, the thermal shutdown circuit takes
over preventing the IC from overheating.
Considerable effort was expanded to make the LM78XX se-
ries of regulators easy to use and minimize the number of
external components. It is not necessary to bypass the out-

put, although this does improve transient response. Input by-
passing is needed only if the regulator is located far from the
filter capacitor of the power supply.
For output voltage other than 5V, 12V and 15V the LM117
series provides an output voltage range from 1.2V to 57V.

Features
n Output current in excess of 1A
n Internal thermal overload protection
n No external components required
n Output transistor safe area protection
n Internal short circuit current limit
n Available in the aluminum TO-3 package

Voltage Range
LM7805C 5V
LM7812C 12V
LM7815C 15V

Connection Diagrams

Metal Can Package
TO-3 (K) Aluminum
Plastic Package
TO-220 (T)

DS007746-2

Top View
DS007746-3
Bottom View
Order Number LM7805CK,
LM7812CK or LM7815CK
See NS Package Number KC02A
Order Number LM7805CT,
LM7812CT or LM7815CT
See NS Package Number T03B

2000 National Semiconductor Corporation DS007746 www.national.com

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Schematic

DS007746-1

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Absolute Maximum Ratings (Note 3) Maximum Junction Temperature
If Military/Aerospace specified devices are required,
(K Package) 150C
please contact the National Semiconductor Sales Office/ (T Package) 150C
Distributors for availability and specifications.
Storage Temperature Range 65C to +150C

Input Voltage
Lead Temperature (Soldering, 10 sec.)
(V
O
= 5V, 12V and 15V) 35V
TO-3 Package K 300C
Internal Power Dissipation (Note 1) Internally Limited
TO-220 Package T 230C
Operating Temperature Range (T
A
) 0C to +70C

Electrical Characteristics LM78XXC (Note 2)
0C T
J
125C unless otherwise noted.
Output Voltage 5V 12V 15V

Units Input Voltage (unless otherwise noted) 10V 19V 23V
Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ Max
V
O
Output Voltage Tj = 25C, 5 mA I
O
1A 4.8 5 5.2 11.5 12 12.5 14.4 15 15.6 V
P
D
15W, 5 mA I
O
1A
V
MIN
V
IN
V
MAX
4.75 5.25
(7.5 V
IN
20)
11.4 12.6 1
(14.5 V
IN

27)
4.25 15.75
(17.5 V
IN

30)
V
V
V
O
Line Regulation I
O
= 500
mA
Tj = 25C

V
IN
3 50

(7 V
IN
25)
4 120

14.5 V
IN
30)
4 150

(17.5 V
IN

30)
mV

V
0C Tj +125C
V
IN
50
(8 V
IN
20)
120
(15 V
IN
27)
150
(18.5 V
IN

30)
mV
V
I
O
1A Tj = 25C
V
IN
50
(7.5 V
IN
20)
120
(14.6 V
IN

27)
150
(17.7 V
IN

30)
mV
V
0C Tj +125C
V
IN
25
(8 V
IN
12)
60
(16 V
IN
22)
75
(20 V
IN
26)
mV
V
V
O
Load Regulation Tj = 25C 5 mA I
O
1.5A
250 mA I
O

750 mA
10 50
25
12 120
60
12 150
75
mV
mV
5 mA I
O
1A, 0C Tj
+125C
50 120 150 mV
I
Q
Quiescent Current I
O
1A Tj = 25C
0C Tj +125C
8
8.5
8
8.5
8
8.5
mA
mA
I
Q
Quiescent Current
Change
5 mA I
O
1A 0.5 0.5 0.5 mA
Tj = 25C, I
O
1A
V
MIN
V
IN
V
MAX
1.0
(7.5 V
IN
20)
1.0
(14.8 V
IN
27)
1.0
(17.9 V
IN

30)
mA
V
I
O
500 mA, 0C Tj +125C
V
MIN
V
IN
V
MAX
1.0
(7 V
IN
25)
1.0
(14.5 V
IN
30)
1.0
(17.5 V
IN

30)
mA
V
V
N
Output Noise
Voltage
T
A
=25C, 10 Hz f 100 kHz 40 75 90 V

Ripple Rejection

f = 120 Hz
I
O
1A, Tj = 25C
or
I
O
500 mA
0C Tj +125C
62 80

62

(8 V
IN
18)
55 72

55

(15 V
IN
25)
54 70

54

(18.5 V
IN

28.5)
dB
dB
V V
MIN
V
IN
V
MAX
R
O
Dropout Voltage
Output Resistance
Tj = 25C, I
OUT
= 1A
f = 1 kHz
2.0
8
2.0
18
2.0
19
V
m

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Electrical Characteristics LM78XXC (Note 2) (Continued)

0C T
J
125C unless otherwise noted.
Output Voltage 5V 12V 15V

Units Input Voltage (unless otherwise noted) 10V 19V 23V
Symbol Parameter Conditions Min Typ Max Min Typ Max Min Typ Max

Short-Circuit
Current
Peak Output
Current
Average TC of
V
OUT
Tj = 25C
Tj = 25C
0C Tj +125C, I
O
= 5 mA
2.1

2.4

0.6
1.5

2.4

1.5
1.2

2.4

1.8
A
A
mV/C
V
IN
Input Voltage
Required to
Maintain
Line Regulation

Tj = 25C, I
O
1A

7.5

14.6

17.7

V
Note 1: Thermal resistance of the TO-3 package (K, KC) is typically 4C/W junction to case and 35C/W case to ambient. Thermal resistance of the TO-220 package
(T) is typically 4C/W junction to case and 50C/W case to ambient.
Note 2: All characteristics are measured with capacitor across the input of 0.22 F, and a capacitor across the output of 0.1F. All characteristics except noise voltage
and ripple rejection ratio are measured using pulse techniques (t
w
10 ms, duty cycle 5%). Output voltage changes due to changes in internal temperature must
be taken into account separately.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and the test conditions, see Elec-
trical Characteristics.

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Typical Performance Characteristics

Maximum Average Power Dissipation

DS007746-5
Maximum Average Power Dissipation

DS007746-6

Peak Output Current

DS007746-7
Output Voltage (Normalized to 1V at T
J
= 25C)

DS007746-8

Ripple Rejection

DS007746-9
Ripple Rejection

DS007746-10

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Typical Performance Characteristics (Continued)

Output Impedance

DS007746-11
Dropout Voltage

DS007746-12

Dropout Characteristics

DS007746-13
Quiescent Current

DS007746-14

Quiescent Current

DS007746-15

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Physical Dimensions inches (millimeters) unless otherwise noted

Aluminum Metal Can Package (KC)
Order Number LM7805CK, LM7812CK or LM7815CK
NS Package Number KC02A
Nati onal does not assume any responsi bility for use of any circuitry described, no circuit patent licenses are implied and Nati onal reserves the ri ght at any time without noti ce to change said circuitry and specifications.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

TO-220 Package (T)
Order Number LM7805CT, LM7812CT or LM7815CT
NS Package Number T03B

LIFE SUPPORT POLICY

NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Franais Tel: +33 (0) 1 41 91 8790
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
TL494
PULSE-WIDTH-
MODULATIONCONTROLCIRCUITS

SLVS074D JANUARY 1983 REVISED MAY 2002

testingof all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

1 16
2 15
3 14
4 13
5 12
6 11
7 10
8 9

Complete PWM Power-Control Circuitry
Uncommitted Outputs for 200-mA Sink or

D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Source Current
Output Control Selects Single-Ended or
Push-Pull Operation
Internal Circuitry Prohibits Double Pulse at
Either Output
Variable Dead Time Provides Control Over
Total Range
Internal Regulator Provides a Stable 5-V
Reference Supply With 5% Tolerance
Circuit Architecture Allows Easy
Synchronization

1IN+
1IN
FEEDBACK
DTC
CT
RT
GND
C1

2IN+
2IN
REF
OUTPUT CTRL
V
CC
C2
E2
E1

description

The TL494 incorporates all the functions required in the construction of a pulse-width-modulation (PWM) control
circuit on a single chip. Designed primarily for power-supply control, this device offers the flexibility to tailor the
power-supply control circuitry to a specific application.

The TL494 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC)
comparator, a pulse-steering control flip-flop, a 5-V, 5%-precision regulator, and output-control circuits.

The error amplifiers exhibit a common-mode voltage range from 0.3 V to V
CC
2 V. The dead-time control
comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed
by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common
circuits in synchronous multiple-rail power supplies.

The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which can be selected through the
output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice
during push-pull operation.

The TL494C is characterized for operation from 0C to 70C. The TL494I is characterized for operation from
40C to 85C.

AVAILABLE OPTIONS

T
A

PACKAGED DEVICES

SMALL
OUTLINE
(D)

PLASTIC
DIP
(N)

SMALL
OUTLINE
(NS)
SHRINK
SMALL
OUTLINE
(DB)
THIN SHRINK
SMALL
OUTLINE
(PW)
0C to 70C TL494CD TL494CN TL494CNS TL494CDB TL494CPW
40C to 85C TL494ID TL494IN
The D, DB, NS, and PW packages are available taped and reeled. Add the suffix R to device type (e.g.,
TL494CDR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conformto specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
Copyright 2002, Texas Instruments Incorporated
TL494
PULSE-WIDTH-


testingof all parameters.

FUNCTION TABLE
INPUT TO
OUTPUT CTRL

OUTPUT FUNCTION
V
I
= GND

Single-ended or parallel output
V
I
= V
ref
Normal push-pull operation

functional block diagram

RT
6

CT
5

DTC
4

~ 0.1 V

Oscillator

Dead-Time Control
Comparator

OUTPUT CTRL
(see Function Table)
13

1D

C1

Q1
8

C1
9
E1

1IN+
1

1IN
2

2IN+
16

2IN
15

FEEDBACK
3

Error Amplifier 1

+

Error Amplifier 2

+

PWM
Comparator

0.7 mA

Pulse-Steering
Flip-Flop

Reference
Regulator
Q2
11

10

12

14

7

C2

E2

V
CC
REF

GND
TL494
PULSE-WIDTH-



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
CC
(see Note 1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Amplifier input voltage, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
+ 0.3 V

Collector output voltage, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 V
Collector output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Package thermal impedance, u
JA
(see Note 2 and 3): D package

DB package
N package
NS package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
73C/W
82C/W
67C/W
64C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of T
J
(max), u
JA
, and T
A
. The maximum allowable power dissipation at any allowable
ambient temperature is P
D
= (T
J
(max) T
A
)/u
JA
. Operating at the absolute maximum T
J
of 150C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN MAX UNIT
V
CC
Supply voltage

7 40 V
V
I
Amplifier input voltage

0.3 V
CC
2

V
V
O
Collector output voltage

40 V
Collector output current (each transistor) 200 mA
Current into feedback terminal 0.3 mA
f
osc
Oscillator frequency

1 300 kHz
C
T
Timing capacitor

0.47 10000 nF
R
T
Timing resistor

1.8 500 k&

T
A
Operating free-air temperature
TL494C 0 70

C
TL494I 40 85
TL494
PULSE-WIDTH-



PARAMETER

TEST CONDITIONS

TL494, TL494I

UNIT
MIN TYP

MAX
Frequency

10 kHz
Standard deviation of frequency
All values of V
CC
, CT, RT, and T
A
constant 100 Hz/kHz
Frequency change with voltage V
CC
= 7 V to 40 V, T
A
= 25C
1 Hz/kHz
Frequency change with temperature
#
T
A
= MIN to MAX 10 Hz/kHz

electrical characteristics over recommended operating free-air temperature range, V
CC
= 15 V,
f = 10 kHz (unless otherwise noted)

reference section

PARAMETER

TEST CONDITIONS

TL494C, TL494I

UNIT
MIN TYP

MAX
Output voltage (REF) I
O
= 1 mA

4.75 5 5.25 V
Input regulation V
CC
= 7 V to 40 V

2 25 mV
Output regulation I
O
= 1 mA to 10 mA

1 15 mV
Output voltage change with temperature T
A
= MIN to MAX
2 10 mV/V
Short-circuit output current
REF = 0 V 25 mA

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values, except for parameter changes with temperature, are at T
A
= 25C.

Duration of the short circuit should not exceed one second.

oscillator section, C
T
= 0.01 F, R
T
= 12 kO (see Figure 1)

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

A
= 25C.

Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:

N

n 1
(x
n
X)
2

N 1

#
Temperature coefficient of timing capacitor and timing resistor are not taken into account.

error-amplifier section (see Figure 2)

PARAMETER

TEST CONDITIONS
TL494, TL494I

UNIT
MIN TYP

MAX
Input offset voltage V
O
(FEEDBACK) = 2.5 V

2 10 mV
Input offset current V
O
(FEEDBACK) = 2.5 V

25 250 nA
Input bias current V
O
(FEEDBACK) = 2.5 V

0.2 1 A

Common-mode input voltage range

V
CC
= 7 V to 40 V
0.3 to
V
CC
2

V
Open-loop voltage amplification V
O
= 3 V, R
L
= 2 k&, V
O
= 0.5 V to 3.5 V
70 95 dB
Unity-gain bandwidth V
O
= 0.5 V to 3.5 V, R
L
= 2 k&
800 kHz
Common-mode rejection ratio V
O
= 40 V, T
A
= 25C
65 80 dB
Output sink current (FEEDBACK) V
ID
= 15 mV to 5 V, V (FEEDBACK) = 0.7 V

0.3 0.7 mA
Output source current (FEEDBACK) V
ID
= 15 mV to 5 V, V (FEEDBACK) = 3.5 V 2 mA

A
= 25C.

TL494
PULSE-WIDTH-


electrical characteristics over recommended operating free-air temperature range, V
CC
= 15 V,
f = 10 kHz (unless otherwise noted)

output section
PARAMETER TEST CONDITIONS MIN TYP

MAX UNIT
Collector off-state current V
CE
= 40 V, V
CC
= 40 V

2 100 A
Emitter off-state current V
CC
= V
C
= 40 V, V
E
= 0

100 A

Collector-emitter saturation voltage
Common emitter V
E
= 0, I
C
= 200 mA

1.1 1.3

V
Emitter follower V
O(C1 or C2)
= 15 V, I
E
= 200 mA

1.5 2.5
Output control input current V
I
= V
ref
3.5 mA

All typical values except for temperature coefficient are at T
A
= 25C.

dead-time control section (see Figure 1)

MAX UNIT
Input bias current (DEAD-TIME CTRL) V
I
= 0 to 5.25 V

2 10 A
Maximum duty cycle, each output V
I
(DEAD-TIME CTRL) = 0, C
T
= 0.01 F, R
T
= 12 k&
45%

Input threshold voltage (DEAD-TIME CTRL)
Zero duty cycle 3 3.3

V
Maximum duty cycle 0

A
= 25C.

PWM comparator section (see Figure 1)

MAX UNIT
Input threshold voltage (FEEDBACK) Zero duty cycle 4 4.5 V
Input sink current (FEEDBACK) V (FEEDBACK) = 0.7 V 0.3 0.7 mA

A
= 25C.

total device

MAX UNIT

Standby supply current

RT = V
ref
, All other inputs and outputs open
V
CC
= 15 V

6 10

mA
V
CC
= 40 V

9 15
Average supply current V
I
(DEAD-TIME CTRL) = 2 V, See Figure 1 7.5 mA

A
= 25C.

switching characteristics, T
A
= 25C

MAX UNIT
Rise time

Common-emitter configuration, See Figure 3
100 200 ns
Fall time 25 100 ns
Rise time

Emitter-follower configuration, See Figure 4
100 200 ns
Fall time 40 100 ns

A
= 25C.

TL494
PULSE-WIDTH-


PARAMETER MEASUREMENT INFORMATION

V
CC
= 15 V

12
V
CC
4

150 O
2 W
8

150 O
2 W
Test
DTC C1 Output 1
Inputs 3

12 kO
6

5

FEEDBACK

RT
CT
E1
9

11
C2
E2
10

Output 2

0.01 F
1
2
16
15

1IN+
1IN
2IN+
2IN

Error
Amplifiers

50 kO

13
OUTPUT
CTRL

GND
7

REF
14

TEST CIRCUIT

Voltage
at C1

Voltage
at C2

Voltage
at CT

DTC

Threshold Voltage
V
CC

0 V
V
CC
0 V

0 V

FEEDBACK
Threshold Voltage
0.7 V
Duty Cycle

0%
MAX
0%

VOLTAGE WAVEFORMS

Figure 1. Operational Test Circuit and Waveforms

TL494
PULSE-WIDTH-


PARAMETER MEASUREMENT INFORMATION

Amplifier Under Test
+
V
I FEEDBACK

+

V
ref
Other Amplifier

Figure 2. Amplifier Characteristics

15 V

Each Output
Circuit
68 O
2 W

Output

90%

t
f t
r

90%
C
L
= 15 pF
(See Note A)

10%

10%

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM
NOTE A: C
L
includes probe and jig capacitance.

Figure 3. Common-Emitter Configuration

15 V

Each Output
Circuit

C
L
= 15 pF
(See Note A)

68 O
2 W
Output

10%

90%

t
r

90%

10%

t
f

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

NOTE A: C
L
includes probe and jig capacitance.

Figure 4. Emitter-Follower Configuration

TL494
PULSE-WIDTH-


f

O
s
c
i
l
l
a
t
o
r

F
r
e
q
u
e
n
c
y

a
n
d

F
r
e
q
u
e
n
c
y

V
a
r
i
a
t
i
o
n

H
z

A

A
m
p
l
i
f
i
e
r

V
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e

A
m
p
l
i
f
i
c
a
t
i
o
n

d
B

TYPICAL CHARACTERISTICS

100 k

40 k
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATION

vs
TIMING RESISTANCE

V
CC
= 15 V
T
A
= 25C

2%

10 k

4 k
1%

0%
0.01 F

0.001 F

1 k 0.1 F

400

100

40

C
T
= 1 F

Df = 1%

10
1 k 4 k 10 k 40 k 100 k 400 k 1 M

R
T
Timing Resistance O

Frequency variation (Af) is the change in oscillator frequency that occurs over the full temperature range.

Figure 5

100
AMPLIFIER VOLTAGE AMPLIFICATION
vs
FREQUENCY
V
CC
= 15 V
90
AV
O
= 3 V

T
A
= 25C
80

70

60

50

40

30

20

10

0
1 10 100

1 k 10 k

100 k 1 M
f Frequency Hz

Figure 6
POWER ELECTRONICS LAB MANUAL 2011-2012

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