Clock Gating and Power Gating for Low Power Circuits

1
Abstract Clock Gating and Power Gating are the two most
widely used techniques for reducing the power losses in
Application Specific Integrated Circuits and other Digital
Networks. This paper discusses the various techniques of Clock
and Power Gating that exist or are being developed. Further it
addresses the challenges faced in integrating Clock Gating and
Power Gating Circuitry and recommends techniques to minimize
the Dissipated (Dynamic and Leakage) Power so as to design a
Low Power Circuit.

I ndex Terms Clock Gating, Power Gating, Dynamic Power,
Leakage Power, Pipeline.

I. INTRODUCTION
odays consumer demands include enhanced functionality
and energy efficiency of devices, which has given rise to
the need to optimize the power of devices at the lowest level
possible. The use of low power techniques is highly
appreciated in VLSI designs. As a result, many methods are
being applied to control and reduce the power wasted in
digital circuits.
Power consumption can broadly be divided into:
(i) Dynamic Power:
It is consumed during the operation of a circuit,
when the circuit has input toggles.
(ii) Leakage Power:
It is dissipated during sleep mode, that is when the
circuit does not have any input toggles. It can be
further categorized into Standby leakage and Active
Leakage.
The most commonly used and widely accepted method to
reduce dynamic power is Clock Gating. On the other hand,
Power Gating is the currently dominating technique being
used to reduce standby leakage power.
II. CLOCK GATING
Currently, clock power consumes 50-70% of total chip
power and this value is expected to rise with the new
generation of designs. [7] Thus, reducing clock power is
extremely important and clock gating is one of the most
efficient ways to implement it.
In practice, a circuit includes a large number of unnecessary
signal transitions that do not affect the output value in. The
basic idea of clock gating involves shutting down the clock of
components that are not being used so as to avoid these
unnecessary transitions. Combinational logic is inserted into
clock paths where switching of sequential elements is not
required (for some particular period of time).
A. CONVENTI ONAL TECHNI QUES
1) Gate Based Clock Gating Cell
Logic Gates such as and, nor, xor, or etc. can be used
having one of the inputs as the clock, the output as the gated
clock and another input as a signal to control the output.
The logic gate and signal can be chosen according to the
requirement .
[15]
Fig.1 OR based Clock Gating Cell
For example, in the gating cell shown above; when enable is
0 the ouput remains stable at 1 and as a result no
flipping/transition occurs at the clock pin of the sequential
element. Thus, no dynamic power is consumed. If enable is
1, g_clk will be the same as Clock.

2) Latch Based Clock Gating Cell
A latch is used as the control element. In the figure shown
below, the positive clock cycle corresponds to the output of
the latch being fixed; while any change in Enable is
reflected only in the negative clock cycle.
[15]
Fig.2 Latch based Clock Gating Cell
Only the high value of latch output allows the clock to reach
the sequential logic. The period when a change in Enable is
detected is called the Active Period, while the period when
we cannot detect it is called the Sleep Period. It should be
ensured that no important change in the state of Enable
occurs during the Sleep period, else it may lead to a faulty
design.


Clock Gating and Power Gating Techniques to
control Dissipated Power
Sachit Tandon
1
, 2012EE10473

1 Department of Electrical Engineering
Indian Institute of Technology, I.I.T. Delhi
sachit.tandon@gmail.com
T
Clock Gating and Power Gating for Low Power Circuits

2
3) Flip-flop based Clock Gating Cell
A flip-flop is used as the control element.
[15]
Fig.3 FF based Clock Gating Cell
Change in Enable is reflected in the flip-flop output on the
arrival of a negative edge. Clock gets transferred to the
sequential circuit only when the flip-flop output is high.
Here the Sleep period is longer as compared to the latch
counterpart.

Each of the above implementations can also be done by
inserting an extra reset signal.
The Gate level implementation has an advantage that it does
not have a sleep period and can respond to the enable signal
irrespective of clock. But, it is prone to glitches. The Latch
and FF based designs on the other hand are free of glitches as
the sleep period ensures that there is no mismatch of delay
between clock and Enable.

B. BEYOND CONVENTI ONAL CLOCK GATI NG
1) Register Level Clock Gating
This type of gating technique is particularly helpful in the
cases involving pipelines with more than one paths. Data has
multiple pathways to flow through. If fewer instructions are
passed, then the registers without a valid input can be clock
gated. It takes advantage of the fact that instructions have a
tendency to follow a specific path that might be very different
from one another, for example: multiplication of values
follows a different path than comparison would require. As a
result, registers that are not being used for a certain class of
instructions can be gated off when the pipeline stage has
instructions of only that class.

2) Transparent Clock Gated Pipelines
Traditional methods of gating in pipelines involves holding
latches opaque in order to avoid race conditions between
adjacent latch stages. This is termed as data propagation.
Thus, it takes M clock cycles to propagate through an M-stage
pipeline. Transparent Clock Gating works on the concept of
data separation that involves keeping successive latch stages
transparent. A data race between 2 signals say A and B is
avoided by making B follow A by m clock cycles, using an
opaque latch stage. [M/m] clock cycles are hence needed to
move A through the pipeline without any data loss.


Fig.4 A 3 Stage TCG Pipeline [2]

Fig.5 Sample Waveforms for A and B [2]
The value of A is stored at the opaque latch till the time B arrives
(2 cycles late) at latch 1 to overwrite A. At this time, A has
reached transparent latch 3 and is captured at that point by
enabling the local clk 3 to transition low. This also ensures that
there is no data race between the two. When B reaches latch 3, A
has already reached the output stage and is captured. Thus, it can
be seen from the waveforms that the TCG approach requires only
one equivalent clock pulse, while the traditional method required
6 pulses.

3) Pipeline Balancing
Pipeline Balancing (PLB) incorporates predicting a
programs Instruction Level Parallelism (ILP) using certain
algorithms, at the granularity of 256-cycle window. [14] The
degree of the ILP for the next window is predicted and
compared with the pipeline width. If the degree is found to be
lesser than the width, then this technique allows clock gating
of a cluster of the components present in the pipeline.

4) Deterministic Clock Gating
The basic concept applied in Deterministic Clock Gating
(DCG) is that a circuit blocks usage in a coming cycle can be
deterministically found out and analyzed a few cycles ahead of
time. Hence the blocks that are not going to be used in the
coming cycle(s) can be clock gated. For instance, there is
usually a register-read stage for a particular application, which
gives us a one cycle window to deterministically analyze the
next cycle. DCG has been found to be more accurate than
PLB, has finer granularity and uses no extra prediction
heuristics. [14]

C. BENEFI TS OF CLOCK GATI NG
A major part of the power is dissipated close to the leaf
nodes of the clock tree driving latch banks. A clock gated
latch can store a value and keep it stable, thus it can prevent
unnecessary and redundant signal transitions from traversing
the pipeline. Hence the switching (active) power in the
combinational logic between latch stages is greatly reduced.
It can also effectively reduce the static (leakage) power as
leakage through CMOS devices is an exponential function of
temperature and clock gating brings the temperature under
control by reducing the dynamic power.
D. LI MI TATI ONS AND CONSTRAI NTS
(i) Some latch groups may be too small to be considered for
Gating due to design limitations.
(ii) Logic required to compute when a latch should be gated
off could become very complex with an increasing number of
latches in the circuit.
Clock Gating and Power Gating for Low Power Circuits

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(iii) Clock gating might lead to inductive noise in the voltage
rails.

III. POWER GATING
A major part of power lost in digital circuits is in the form
of leakage power. At the 32nm and 22nm technology nodes,
leakage power ranges from 16.9% to 52.7% of total core
power depending on circuit type, latency constraints, and
temperature. [3]
Power Gating is the most widely accepted and used
technique to reduce leakage power. The basic idea behind
power gating is to insert a type of switch between the supply
voltage and the combinational/sequential block so that current
through the block can be stopped when the block is not needed
by switching off the switch, hence ensuring that the functional
block does not contribute to the leakage power loss.
Depending on the power gating approach, the technique can
be categorized into:
(i) Fine-Grained Power Gating:
If each power gated cell is used separately in an isolated
fashion i.e.: they do not share a common switch for the
gating operation.
(ii) Coarse-Grained or Cluster-Based Power Gating:
The switch is shared by a cluster of logic cells, possibly
located in close proximity or having similar
functionalities.

A. TRANSI STOR-BASED POWER GATI NG
Transistors are used as sleep switches between the power
(or voltage) supply and the functional block. The power
network is called the header, while the ground network is
called the footer.
[1]
Fig.6 A general power gating scheme
Virtual VDD and Virtual GND are the effective supply
voltage and ground voltage respectively being applied on the
logic block. Their values depend on the states of the switches
used. Although both header and footer switches may be used
simultaneously, using only one is recommended keeping in
mind the restrictions in area and time.

Fig.7 Power Gating with only header switch
Now consider only a header switch. Say the switch is
controlled by a signal sleep (base of the transistor). When
sleep is 0, the transistor is in active state and VDD appears as
Virtual VDD, with a minor voltage drop across the transistor.
This enables the functional block. When sleep is 1, the
transistor is switched off and hence current to the functional
block is stopped. There is thus no leakage power loss in the
logic block. It should however be noted that the header
switches, being transistors; themselves leak. This implies that
leakage is reduced and not eliminated.

B. EMERGI NG POWER GATI NG TECHNI QUES
1) NEMS Switches
Many devices today require long idle periods such as
wireless security systems, environmental sensors, biomedical
implants etc. Hence it is not only important to reduce active
leakage, but also the residual off-state leakage, because over
long periods of time these may accumulate to incur huge
energy losses. Some changes in the transistor design may help
but have their drawbacks. Changing the thickness or length of
the transistor increases the effective resistance and slows
down the logic unit, while increasing threshold and supply
voltages is not recommended due to energy considerations.
Hence the deciding factor is the tradeoff between delay and
power loss.
The CMOS-Nano Electro Mechanical Systems (NEMS)
switch is a type of nano-scale relay having a mechanical
switching delay of the order ~10
-9
s.

Fig.8 A double cantilever NEMS Switch [5]
The switch comprises of a cantilever beam as the source.
Once the gate voltage reaches the activation voltage of the
switch, the cantilever beam bends and forms contact with the
drain under the electrostatic force generated from the gate.
This is how the switch works. It should be noted that the off-
resistance is nearly infinite due to the air gap between drain
and source, hence NEMS switches completely eliminate off-
state leakage. [5]
Clock Gating and Power Gating for Low Power Circuits

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Research is being done to form entire power gating circuits
using NEMS switches only, keeping in mind its relative
advantages. [5]

2) Using Clocked Adiabatic Logic
Conventional CMOS logic uses a constant voltage source to
charge the load capacitance, whereas adiabatic logic uses a
constant current source. The voltage across a resistance is used
as the on-switch condition and the setup applies the concept of
recycling the energy of a circuit rather than dissipating it.
Multiphase or single-phase power-clocks are required for
adiabatic logic. CAL is one Adiabatic Logic family which
uses single phase power-clock and can be used just like
transistors to switch off a functional cell when it is not needed.
The use of adiabatic flip-flops for the purpose of power gating
is widely being researched. [10]

IV. INTEGRATING CLOCK AND POWER GATING
Integrating clock and power gating involves using the clock
gating signals essentially to control the power-gating
components. The convenience in integrating the two
techniques involves exploring the properties of the clusters
that exist in the digital network- which clusters are
independent or which ones can be clock-gated etc. Certain
trade-offs need to be taken care of. The combination and
selection of clusters may be sub-optimal when compared to
either Clock Gating or Power Gating. Moreover, sizes of the
clusters being power gated may result in the need for larger
sizes of the sleep transistors. Further, if Clock Gating signals
switch too frequently, this would mean that clusters will be
deactivated and activated at that frequency. Since reactivating
a cluster requires power, the net result might be that power
saving is reduced. Thus, while integrating; such factors should
be kept in mind.
Currently several researches are being done in this area and
many algorithms have also been suggested such as Placement
Aware Clustering, using Data Retention Logic etc. [9][11]
V. CONCLUSION
In this paper, we saw how clock gating and power gating
are the most widely used techniques to reduce dynamic and
leakage power respectively. Further, various types of clock
gating and power gating techniques were discussed along with
their benefits and shortcomings. Certain upcoming
technologies were mentioned and explained in brief. Finally,
the problems and challenges faced in integrating the two were
discussed.
Therefore, we observed that Clock Gating and Power
Gating are extremely useful methodologies in the design of
Low Power Circuits.
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