IMPROVED ASIC IMPLEMENTATION

Carol Bachelu
Senior H/W Design Verification Engineer
CDNLive!/13 Sep 05
THROUGH SDC CONSTRAINT VALIDATION
Overview
> Introduction
> SDC Constraints Specification for Nortel ASICs
> Moving Towards Automatic Constraints Generation
> Summary
Why Are SDC Constraints Needed?
> Timing closure for large, complex ASICs is a major
challenge
> Timing requirements must be considered throughout
implementation
RTL synthesis
Virtual prototyping (VP) and floorplanning/placement
Static timing verification (STV)
> Synopsys design constraints (SDC) convey timing
requirements to implementation tools
SDC Constraint Specification Challenges
> Implementation tools use the constraints differently
> Incorrect or missing constraints can cause
unnecessarily long tool run times
undetected timing problems
unnecessary design/analysis effort
Different Tools: Different Constraints
> For RTL synthesis tools,
SDC constraints influence the technology cells used in and the
structure of the generated netlist
> For VP/floorplanning/placement tools,
SDC constraints influence the physical location of the cells in the
netlist
> For STV tools,
SDC constraints enable timing measurement and violation
detection
Incorrect or Missing Constraints
> Unnecessarily long tool run times
e.g.
synthesis and VP/floorplanning/placement tools expend effort to
meet overly-tight timing requirements
STV tools measure and report timing for paths which are
asynchronous
> Undetected timing problems
e.g.
VP/floorplanning/placement tools specify improper locations for
elements of critical timing paths
STV and VP/floorplanning/placement tools do not report actual
timing violations
Incorrect or Missing Constraints cont
> Unnecessary design/analysis effort
e.g.
changes are made to RTL code to unnecessarily avoid false
timing violations
analysis time is spent determining the cause of false timing
violations
How Conformal Constraint Designer Helps
> Constraints Checking
detects proper usage/syntax, conflicts/inconsistencies,
redundancies,
> Constraints Completeness
reports missing external delay constraints, unconstrained clock
pins, missing clock latencies,
> Exceptions Validation
reports correctness of specified false path constraints
determines falseness of specified timing paths
Overview
> Introduction
> SDC Constraints Specification for Nortel ASICs
> Moving Towards Automatic Constraints Generation
> Summary
Where Are SDC Constraints Used at Nortel?
> Block-level RTL Synthesis
Design Compiler
> VP/Floorplanning
First Encounter (FE)
> STV
PrimeTime (PT)
Constraints Specification
> No top-level synthesis constraints
Nortels complex designs are too large to do top-level RTL
synthesis (link only)
> Single set of constraints for VP
merged set of most-restrictive core and boundary constraints from
all modes of operation
> Multiple sets of constraints for STV
separate constraints sets for core and boundary timing paths
separate core constraints sets for each mode of operation
separate constraints sets for output data and enable timing paths
Constraints Specification Flow
> Develop preliminary constraints sets for STV
> Assemble initial merged constraints set for VP
> (Iteratively) refine merged constraints set as required
throughout VP process
> Finalize constraints sets for STV
Develop Preliminary STV Constraints Sets
> Identify operation modes
> For each operation mode,
apply mode configuration constants (if any)
define clocks
define clock relations
define boundary constraints
validate constraints with Conformal Constraint Designer
(Conformal CD)
Define Clocks
> Find clock tree roots
> Apply clock tree configuration constants as required
> Define clock network constraints
dont touch
latency
uncertainty (skew, jitter, on-chip variation)
Define Clock Relations
> Identify clock groups and define asynchronous clock
relations
define false path constraints
> Override default clock relations, if necessary
define multi-cycle path constraints
Define Boundary Constraints
> Define transition and external drive constraints for
inputs (except clocks)
> Define load constraints for outputs
> Identify constraining clocks for synchronous inputs
and outputs
> Define external delay constraints for synchronous
inputs and outputs
decide how to constrain the output direction of inout pins (enable
vs data path)
Validate with Conformal CD
> Set design stage to G-pre
> Read SDC constraints
> Validate constraints
> Modify constraints to eliminate SDC rule check Error
messages
> Review all SDC rule check Warning messages
modify constraints if warning message indicates a real issue
keep a log of waived warning messages to compare against in
subsequent validation passes
> Repeat from validate step as necessary
Constraints Specification Flow
> Develop preliminary constraints sets for STV
> Assemble initial merged constraints set for VP
> (Iteratively) refine merged constraints set as required
throughout VP process
> Finalize constraints sets for STV
Assemble Merged Constraints Set for VP
> Select the constraints set with the most restrictive
constraints for the largest number of timing paths
> Identify unconstrained timing paths
> Modify selected constraints set to cover all
unconstrained paths
> Correct constraints for timing paths which are over-
or under-constrained
> Validate constraints with Conformal CD
Identify Unconstrained Timing Paths
> No commercial CAD tools provide complete
capability
PTs report_coverage capability is incomplete
FE has no coverage reporting
> Nortels in-house timing path audit tool reports timing
path coverage for single constraints sets
scripts provide semi-automatic process for determining
cumulative coverage of multiple constraints sets
Add Coverage for Unconstrained Paths
> Specify undefined clocks
> Remove or move constants
attempt to restrict usage of constants to clock tree configuration
> Specify min/max delay constraints for timing paths
which are missing either or both startpoint and
endpoint clocks
Correct Over/Under-Constrained Paths
> No formal process
> Things to look for:
paths which in a constraints set other than the original selected
set are associated with a higher/lower frequency clock
paths which are multi-cycle in a constraints set other than the
original selected set
> Use min/max delay constraints to override
Constraints Specification Flow
> Develop preliminary constraints sets for STV
> Assemble initial merged constraints set for VP
> (Iteratively) refine merged constraints set as required
throughout VP process
> Finalize constraints sets for STV
Refine Merged Constraints During VP
modify constraints
start FE
validate constraints
analyze violations
load design apply constraints
congestion?
Y
N
analyze problems
floorplan
Y
N
A
place, route,
optimize
violations?
timing
Analyze Timing Violations
> Translate FE timing path reports for violations into
Conformal CDs STD format
translation scripts come with CD
> Use Conformal CD to generate false path constraints
for any of the violating paths which are functionally
false
it may be necessary to use the preliminary STV constraints sets,
in which case, a timing path can only be considered false if it is
false for each of the constraints sets
> Determine if any of the remaining violating paths are
actually multi-cycle paths
Modify and Re-validate Constraints
> Add any false path constraints generated by
Conformal CD
> Add constraints for paths identified as multi-cycle
> Validate with Conformal CD as before
Refine Merged Constraints cont
analyze problems
synthesize
clock trees
modify constraints
N
Y
floorplan
A
output netlist,
placement
exit FE
route, optimize
violations?
timing
validate constraints
Modify Constraints for Post-CTS
> Remove dont touch network clock constraints
> Remove (non-source) clock latency constraints
> Remove skew from clock uncertainty constraints
> Add propagated clock constraints
Validate with Conformal CD
> Set design state to G-post
> Read SDC constraints
> Validate constraints
> Modify constraints to eliminate SDC rule check errors
> Review SDC rule check warning messages
> Repeat from validate step as necessary
Constraints Specification Flow
> Develop preliminary constraints sets for STV
> Assemble initial merged constraints set for VP
> (Iteratively) refine merged constraints set as required
throughout VP process
> Finalize constraints sets for STV
Finalize STV Constraints
> Update preliminary STV constraints set(s)
change to reflect final post-CTS constraints set used for VP
separate core and boundary constraints
update boundary constraints
(optional) separate core synchronous reset timing paths, if any
> Identify unconstrained timing paths and add
coverage, if necessary
> Refine constraints during STV, if necessary
> Validate all constraints sets with Conformal CD as for
post-CTS VP constraints
Incorporate Post-CTS Constraints from VP
> Adjust the clock constraints for post-CTS
> Add exception constraints
when there are multiple STV constraint sets, ensure that
constraints are added to all appropriate sets
note that some multi-cycle path constraints may need to be
converted to false path constraints
Update Boundary Constraints
> Remove transition, external drive, and load
constraints if delay calculation isnt to be used
> Isolate output enable paths for inouts
create a separate constraints set with input and data output paths
disabled
disable output enable paths in original constraints sets
> (Optional) Create separate characterization
constraints
used to measure actual boundary timing instead of to verify
specified external delay constraints
Identify Unconstrained Timing Paths
> Run audit tool on constraints set(s) to determine
timing path coverage
> If there are multiple sets of core constraints,
determine cumulative core timing path coverage
> Determine cumulative boundary timing path coverage
Add Coverage for Unconstrained Paths
> Create new constraints sets as required
run audit tool to determine updated cumulative coverage
> Document timing paths which cannot be verified
statically
verification of these paths will need to be done with gate-level
simulations
Refine Constraints During STV
> Run PT to analyze timing for each constraints set
> Analyze timing violations
> Modify constraints to eliminate false violations
> Validate constraints with Conformal CD
> Repeat from PT analysis step as necessary
Analyze Timing Violations
> Translate PT timing path reports for violations into
Conformal CDs STD format
translation scripts come with Conformal CD
> Use Conformal CD to generate false path constraints
for any of the violating paths which are functionally
false
> Determine if any of the remaining violating paths are
actually multi-cycle paths
Eliminate False Violations
> Add any false path constraints generated by
Conformal CD
use audit tool to determine updated cumulative coverage, and if
necessary, create new constraints sets to verify these false paths
> Add constraints for paths identified as multi-cycle
Too Big to Handle Flat
> Specification of constraints for sub-blocks follows
same process as for top-level design except:
sub-block boundary constraints can be determined directly from
results of top-level placement
for STV, interface logic models (ILMs) allow boundary timing
paths of sub-blocks to be verified in the top-level netlist, so
external delay constraints for the sub-blocks are not required
> Additional help from Conformal CD
checks for inconsistencies between block-level and top-level
constraints
Overview
> Introduction
> SDC Constraints Specification for Nortel ASICs
> Moving Towards Automatic Constraints Generation
> Summary
More Help from Conformal CD
> Automated integration of top-level and block-level
SDC constraints
> Simultaneous analysis of constraints sets for multiple
modes
Hierarchical Constraints Integration
> Conformal CD will integrate block-level and partial
top-level SDC constraints into a single, complete top-
level SDC constraints set (4Q05)
read block-level and partial top-level constraints
integrate the relevant constraints and exceptions, resolving
conflicts when necessary
> Designers can compare integrated constraints with
original block-level constraints using Conformal CDs
hierarchical constraint checks
Support for Multiple Modes
> Conformal CD will analyze multiple constraints sets
and report:
overlaps and conflicts
over-constrained and under-constrained paths
> Designers can use reported information to help
assemble the merged constraints set required by
most VP/floorplanning/placement tools
Summary
> To achieve timing closure for Nortels large, complex
designs, good quality SDC constraints are required
> Nortel uses Conformal Constraint Designer to
improve the quality of the SDC constraints sets used
for VP/floorplanning and STV