+
}
+
K x K x
dx
Wheree is the error signal between output and input of transfer characteristic
If we assume the best case input signal to be a full-scale sine wave, code transition level T[k] of N bit ADC is
1
[ ] .
k
C
T k C A cos
M
| |
=
|
\ .
, K=1, 2 2
N-1
(3.1)
IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
A Publisher for Research Motivation........ Email: editoriijec@ipasj.org
Volume 2, Issue 8, August 2014 ISSN 2321-5984
Volume 2, Issue 8, August 2014 Page 71
Also rms value as function of Vref for sinusoidal stimuli is
[ rms] = (3.2)
The range of the error voltage is the quantum voltage level (the least significant bit)
[] = =1 LSB (3.3)
Assuming this quantization error voltage is uniformly distributed over the code width from -1/2 LSB to +1/2 LSB, the
expectation value of the error voltage is
= = (3.4)
So the signal to noise ratio is
=20 log =6.02N+1.76 db (3.5)
SINAD is frequently expressed as function of ENOB as
=( - 1.76) / 6.02. (3.6)
Figure 2.2 Sine wave for Histogram representation
4. EXPERIMENTAL ANALYSIS & SIMULATION RESULT
Noise appear due to quantization error may leads to the result of signal to quantization ratio for different effective
number of bit.
4.1 Overdrive Effect on ENOB
Table 4.1 Overdrive Effect on ENOB for 5 bit ADC
S.
No
Over
drive
Voltage
(LSB)
ENOB
without
correction
ENOB
with
correction
ENOB
with
correction
ENOB
with
correction
ENOB with
Correction
1
0 4.6411 3.591714 3.832237 4.185664 4.49258
2
0.3 4.585717 3.7395 3.80722 4.112153 4.371658
IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
A Publisher for Research Motivation........ Email: editoriijec@ipasj.org
Volume 2, Issue 8, August 2014 ISSN 2321-5984
Volume 2, Issue 8, August 2014 Page 72
3
0.6 3.526631 3.944277 3.955724 4.154126 4.293105
4
0.9 3.052208 4.106052 4.102543 4.278497 4.388625
5
1.2 2.773103 4.262992 4.245827 4.413243 4.509603
6
1.5 2.580804 4.41501 4.391954 4.555625 4.64326
7
1.8 2.418624 4.571049 4.593446 4.702765 4.784715
8
2.1 2.282153 4.730507 4.84872 4.852046 4.92587
9
2.4 2.16101 4.886028 4.997289 4.996745 5.062183
Fig.4.1 Comparision of ENOB for overdrive effect for 5 bit ADC
4.2 SINAD estimation & comparision (propsed & earlier)
Table 4.2 Estimation of signal-to-noise & distortion ratio (SINAD) for 5 bit ADC
No. of
Samples
Resolution
ENOB SINAD ENOB
SINAD
(proposed)
(earlier) (earlier) (proposed)
512 5 Bits 4.7178 30.16 db 4.832 30.84 db
1024 5 Bits 4.7094 30.11 db 4.7963 30.63 db
2048 5 Bits 4.607 29.49 db 4.7687 30.46 db
4096 5 Bits 4.6491 29.74 db 4.7786 30.52db
8192 5 Bits 4.642 29.70 db 4.7824 30.55 db
11200 5 Bits 4.6543 29.77 db 4.7801 30.53 db
16384 5 Bits 4.7437 30.31 db 4.7872 30.57 db
20000 5 Bits 4.7469 30.33 db 4.7811 30.54 db
Fig.4.2 Comparision of SINAD for 5 bit ADC with previous results
IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm
A Publisher for Research Motivation........ Email: editoriijec@ipasj.org
Volume 2, Issue 8, August 2014 ISSN 2321-5984
Volume 2, Issue 8, August 2014 Page 73
5. CONCLUSION
In proposed work dynamic testing of an ADC is done by simulating ideal 5 bit ADC transfer characteristics. Large
number of samples of full scale sine wave is taken at selected sampling frequency and code transition levels are
computed using histogram method. Overdrive effects on Effective No. of bit (ENOB) have been analyzed.
Quantization error & different error voltage are determined. Signal-to-noise ratio & signal-to-noise & distortion ratio is
estimated with different samples of input frequency of sine wave. Expected proposed output has been compared with
previous results, which shows improvement in the outcomes of estimated parameter of proposed work.
REFERENCES
[1] IEEE Standard for Terminology and Test Methods for Analog-to- Digital Converters, IEEE Std. 1241, 2000.
[2] Jingbo Duan, Degang Chen, SNR Measurement Based on Linearity Test for ADC BIST IEEE Std. 2011.
[3] Bhawana Garg, Dr. D.K.Mishra, Dynamic Testing of ADC: A Review International Journal of Advancements in
Research & Technology, Vol. 1, Issue 4, September-2012.
[4] Jerome J. Blair, Thomas E. Linnenbrink, Corrected rms error and effective number of bits for sine wave ADC ests
ELSEVIER International J ournal on Computer Standards & Interfaces, vol. 26, pp. 4349, 2003.
[5] H. W. Ting, Bin-Da Liu and S. J. Chang, A histogram based testing method for estimating/D converter
performance, IEEE transaction on instrumentation and measurement. Vol. 57,no. 2, PP 420 427, Feb. 2008.
[6] F.azais, S.Bernard, Y.Bertrand, M.Comte, M.Renovell, A-to-D Converter static error detection from dynamic
Parameter measurement, Microelectronics journal34945-953, 2003.
[7] Mahmoud Fawzy Wagdy and Selim S. Awad, Determining ADC Effective Number of Bits Via Histogram testing,
IEEE transaction on instrumentation and measurement. Vol.40, no.4, PP 770-772, Aug.1991.
[8] H. W. Ting, Bin-Da Liu and S. J. Chang, A histogram based testing method for estimating A/D converter
performance, IEEE transaction on instrumentation and measurement. Vol. 57, no. 2, PP 420 427, Feb. 2008.
[9] F. Correa Alegria and A. Cruz Serra, Error in the estimation of transition voltages with the standard
Histogram test ADCs ELSEVIER international Journal on Measurement, 35, pp 389-397, 2004.
[10] H. W. Ting, B. Da Liu and S. Jyh Chang, A Histogram - Based Testing Method for Estimating A/D
Converter Performance IEEE Transactions on Instrumentation and Measurement, vol 57, No 2,2008.
AUTHORS
Manish Jain received the B.E.in Electronics & Telecommunication from MIT with RGPV Bhopal in
2001, and M.Tech. in Microelectronics & VLSI from SGSITS Indore in 2008.He has having 11 years of
Experience in field of teaching & research. His field of interest is in NOC, ADC design & testing, RF
communication, digital design & fabrication. He is currently working as a Associate Professor in Elex. &
Communication Department in Engg. College.
Dr. R.S. Gamad received B.E. in Electronics & Communication, M.Tech. in EC & Ph.D. He has having
17 years of Experience in field of teaching. His area of interest is Design and performance analysis of
ADC, Analog & mixed signal circuit design. He is member of IETE & IE India. He is currently working
as a Associate Professor in Elex. & Instrument Department in reputed Engg. College.