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Chapter N

Table of Operands
Drawing Number: 04 68 283000/A
Issued: 19.06.02
Stored: 03.04.03
Version: 1.0.0
File name:
04-68283 Manual digsy
Chapter N Table of Operands.doc
Prepared by: Ralf Neuber
This manual was prepared with great care. The details and data in this document are regularly checked and updated and
are at any time subject to change without notice. Nevertheless, INTER CONTROL does not assume liability for the
correctness of the details/data in this document, since, despite great effort, mistakes cannot always be completely ruled out.
In addition, INTER CONTROL reserves the right to make at any time technical changes to the product, which can also result
in deviations from the contents of this document.
The document includes information that enjoys protection of copyright. No part of this publication may be reproduced and/or
translated into other languages without the prior written permission of INTER CONTROL.
Of course, any ideas and suggestions regarding amendments, or notes concerning mistakes in this document are welcome.
Please refer to INTER CONTROL.
INTER CONTROL
Hermann Khler Elektrik GmbH & Co. KG
Schafhofstrae 30
D-90411 Nrnberg
Germany
Tel.: ++49 911 9522-5
Fax: ++49 911 9522-857
E-mail: info@intercontrol.de
Internet: http://www.intercontrol.de
N Table of Operands
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Table of Contents:
N Table of Operands ...................................................................................................................N-3
N.1 Introduction .......................................................................................................................N-3
N.2 Overview of the Operand Areas .......................................................................................N-3
N.3 Input Operands of the digsy

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N.4 Output Operands of the digsy

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N.5 System Input Operands of the digsy

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N.6 System Output Operands of the digsy

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N.7 Configuration Operands of the digsy

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N.8 Notes...............................................................................................................................N-25
N Table of Operands
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N TABLE OF OPERANDS
N.1 Introduction
The tables below are listing the inputs or outputs that are assigned to the respective operands
required for programming (please refer to the Documentation and Programming system
PROSYD1131 Type 4395.20.100).
NOTE:
PROSYD1131 V2.1 SP11 (or versions of a higher level) is to be used at any
rate, if the complete flag area is to be addressed, too !
N.2 Overview of the Operand Areas
The interface between firmware, application program PROSYD1131 and external processes is a
data interface consisting of 1024 input bytes (I-area), 1024 output bytes (Q-area) and 2048 flag
bytes (M-area).
Since both the firmware and external processes (e.g., CANopen) are accessing these operands,
the user should use the predefined operands in the variable control configuration for programming.
Inputs (IX, IB, IW) Outputs (QX, QB, QW) Flags (MX, MB, MW)
Bytes Area (read only) Bytes Area (read write) Bytes Area (read write)
0 0 0
191
Input
variables
191
Output
variables
192 192
255
SYSIN
255
256
511
Configuration
files
256
511
SYSOUT
512 512
1023
freely usable
for user variables;
e.g.,
CANopen
input variables
1023
freely usable
for user variables;
e.g.,
CANopen-output
variables
1023
1024
2047
freely usable
for CANopen
input / output
variables and
fixly addressed
user data
Figure N.1: Overview of the operand areas
N Table of Operands
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N.3 Input Operands of the digsy

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Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
Digital Inputs (TDIGININ)
0 0
In.DigIn.Value[1]
(WORD)
ID1 All digital inputs of DcS CPU (ID1.1..ID1.12) X
0.0 ID1_1 Digital input 1 of DcS CPU (ID1.1) X
0.1 ID1_2 Digital input 2 of DcS CPU (ID1.2) X
0.2 ID1_3 Digital input 3 of DcS CPU (ID1.3) X
0.3 ID1_4 Digital input 4 of DcS CPU (ID1.4) X
0.4 ID1_5 Digital input 5 of DcS CPU (ID1.5) X
0.5 ID1_6 Digital input 6 of DcS CPU (ID1.6) X
0.6 ID1_7 Digital input 7 of DcS CPU (ID1.7) X
0.7 ID1_8 Digital input 8 of DcS CPU (ID1.8) X
1 0.8 ID1_9 Digital input 9 of DcS CPU (ID1.9) X
0.9 ID1_10 Digital input 10 of DcS CPU (ID1.10) X
0.10 ID1_11 Digital input 11 of DcS CPU (ID1.11) X
0.11 ID1_12 Digital input 12 of DcS CPU (ID1.12) X
0.12 not used
: :
0.15 not used
1 2
In.DigIn.Value[2]
(WORD)
ID2 All digital inputs of DcS I/O (ID2.1..ID2.12) X
1.0 ID2_1 Digital input 1 of DcS I/O (ID2.1) X
1.1 ID2_2 Digital input 2 of DcS I/O (ID2.2) X
1.2 ID2_3 Digital input 3 of DcS I/O (ID2.3) X
1.3 ID2_4 Digital input 4 of DcS I/O (ID2.4) X
1.4 ID2_5 Digital input 5 of DcS I/O (ID2.5) X
1.5 ID2_6 Digital input 6 of DcS I/O (ID2.6) X
1.6 ID2_7 Digital input 7 of DcS I/O (ID2.7) X
1.7 ID2_8 Digital input 8 of DcS I/O (ID2.8) X
3 1.8 ID2_9 Digital input 9 of DcS I/O (ID2.9) X
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Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
1.9 ID2_10 Digital input 10 of DcS I/O (ID2.10) X
1.10 ID2_11 Digital input 11 of DcS I/O (ID2.11) X
1.11 ID2_12 Digital input 12 of DcS I/O (ID2.12) X
1.12 ID2_13 Digital input 13 of DcS I/O (ID2.13) X
1.13 ID2_14 Digital input 14 of DcS I/O (ID2.14) X
1.14 not used
1.15 not used
2 4
In.DigIn.Value[3]
(WORD)
QD2_AS_ID3
Readback Digital outputs of DcS I/O,
configured as Digital inputs (QD2.1..QD2.8)
X
2.0
QD2_1_AS_
ID3_1
Readback Digital output 1 of DcS I/O, when
configured as Digital input (QD2.1)
X
2.1
QD2_2_AS_
ID3_2
Readback Digital output 2 of DcS I/O, when
configured as Digital input (QD2.2)
X
2.2
QD2_3_AS_
ID3_3
Readback Digital output 3 of DcS I/O, when
configured as Digital input (QD2.3)
X
2.3
QD2_4_AS_
ID3_4
Readback Digital output 4 of DcS I/O, when
configured as Digital input (QD2.4)
X
2.4
QD2_5_AS_
ID3_5
Readback Digital output 5 of DcS I/O, when
configured as Digital input (QD2.5)
X
2.5
QD2_6_AS_
ID3_6
Readback Digital output 6 of DcS I/O, when
configured as Digital input (QD2.6)
X
2.6
QD2_7_AS_
ID3_7
Readback Digital output 7 of DcS I/O, when
configured as Digital input (QD2.7)
X
2.7
QD2_8_AS_
ID3_8
Readback Digital output 8 of DcS I/O when
configured as Digital input (QD2.8)
X
5 not used
Analog Inputs (TANININ)
3 6
In.AnIn.Value[1]
(WORD)
IA1_1
Analog input 1 of DcS CPU
(IU1.1 or II1.1)
X
4 8
In.AnIn.Value[2]
(WORD)
IA1_2
Analog input 2 of DcS CPU
(IU1.2 or II1.2)
X
5 10
In.AnIn.Value[3]
(WORD)
IA1_3
Analog input 3 of DcS CPU
(IU1.3 or II1.3)
X
6 12
In.AnIn.Value[4]
(WORD)
IA1_4
Analog input 4 of DcS CPU
(IU1.4 or II1.1)
X
7 14
In.AnIn.Value[5]
(WORD)
IA2_1
Analog input 1 of DcS I/O
(IU2.1 or II2.1)
X
8 16
In.AnIn.Value[6]
(WORD)
IA2_2
Analog input 2 of DcS I/O
(IU2.2 or II2.2)
X
9 18
In.AnIn.Value[7]
(WORD)
IA2_3
Analog input 3 of DcS I/O
(IU2.3 or II2.3)
X
10 20
In.AnIn.Value[8]
(WORD)
IA2_4
Analog input 4 of DcS I/O
(IU2.4 or II2.4)
X
11 22
In.AnIn.VQS_
VCP (WORD)
VQS_VCP
Readback of offset voltage VCP of the inputs
ID1.9..ID1.12 on the DcS CPU [mV] (VQS for
the time being without meaning)
X
12 24
In.AnIn.VIMP
(WORD)
VIMP_CPU
Readback of operating voltage VIM on the
DcS CPU [100mV]
X
13 26
In.AnIn.TEMP
(WORD)
TEMP_CPU
Internal temperature (close to the processor)
in the DcS CPU [K]
X
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Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
14 28
In.AnIn.RAMPE
(WORD)
RAMPE_CPU
Test ramp for the Analog inputs of DcS CPU
(presently not supported)
X
Counting Inputs (TCOUNTERIN)
15 30
In.Cnt.Value[1]
(DINT)
IC1_1
Counting input 1 of DcS CPU
(ID1.11 as IC1.1)
X
17 34
In.Cnt.Value[2]
(DINT)
IC1_2
Counting input 2 of DcS CPU
(ID1.12 as IC1.2)
X
19 38
In.Cnt.Value[3]
(DINT)
IC2_1
Counting input 1 of DcS I/O
(ID2.11 as IC2.1)
X
21 42
In.Cnt.Value[4]
(DINT)
IC2_2
Counting input 2 of DcS I/O
(ID2.12 as IC2.2)
X
23 46
In.Cnt.Value[5]
(DINT)
IC3_1
Counting input 3 of DcS I/O
(ID2.9 as IC3.1)
X
25 50
In.Cnt.Value[6]
(DINT)
IC3_2 Counting input 4 of DcS I/O (ID2.10 as IC3.2) X
27 54
In.Cnt.Value[7]
(DINT)
IC4_1 Counting input 5 of DcS I/O(ID2.13 as IC4.1) X
29 58
In.Cnt.Value[8]
(DINT)
IC4_2 Counting input 6 of DcS I/O(ID2.14 as IC4.2) X
31 62
In.Cnt.Velocity[1]
(WORD)
IC1_1_Velo
Velocity on counting input No. 1 of DcS CPU
(IC1.1) [Pulses/time window]
X
32 64
In.Cnt.Velocity[2]
(WORD)
IC1_2_Velo
Velocity on counting input No. 2 of DcS CPU
(IC1.2) [Pulses/time window]
X
33 66
In.Cnt.Velocity[3]
(WORD)
IC2_1_Velo
Velocity on counting input 1 of DcS I/O
(IC2.1) [Pulses/time window]
X
34 68
In.Cnt.Velocity[4]
(WORD)
IC2_2_Velo
Velocity on counting input 2 of DcS I/O
(IC2.2) [Pulses/time window] (In the case of a
configuration as an AB-counter: 0 = forward
or unchanged (A before B), 1 = backward
(B before A))
X
35 70
In.Cnt.Velocity[5]
(WORD)
IC3_1_Velo
Velocity on counting input 3of DcS I/O (IC3.1)
[Pulses/time window]
36 72
In.Cnt.Velocity[6]
(WORD)
IC3_2_Velo
Velocity on counting input 4 of DcS I/O
(IC3.2) [Pulses/time window] (In the case of a
configuration as an AB-counter: 0 = forward
or unchanged (A before B), 1 = backward
(B before A))
X
37 74
In.Cnt.Velocity[7]
(WORD)
IC4_1_Velo
Velocity on counting input 5 of DcS I/O
(IC4.1) [Pulses/time window]
X
38 76
In.Cnt.Velocity[8]
(WORD)
IC4_2_Velo
Velocity on counting input 6 of DcS I/O
(IC4.2) [Pulses/time window] (In the case of a
configuration as an AB-counter: 0 = forward
or unchanged (A before B), 1 = backward
(B before A))
X
PWM Current Measurement (TPWMIN)
39 78
In.PWM.Current
[1] (WORD)
IPI1_1
Readback of current on PWM-output 1
of DcS CPU (QD1.1) [2mA/Digit]
X
40 80
In.PWM.Current
[2] (WORD)
IPI1_2
Readback of current on PWM-output 2
of DcS CPU (QD1.2) [2mA/Digit]
X
41 82
In.PWM.Current
[3] (WORD)
IPI1_3
Readback of current on PWM-output 3
of DcS CPU (QD1.3) [2mA/Digit]
X
42 84
In.PWM.Current
[4] (WORD)
IPI1_4
Readback of current on PWM-output 4
of DcS CPU (QD1.4) [2mA/Digit]
X
43 86
In.PWM.Current
[5] (WORD)
IPI1_5
Readback of current on PWM-output 5
of DcS CPU (QD1.5) [2mA/Digit]
X
44 88
In.PWM.Current
[6] (WORD)
IPI1_6
Readback of current on PWM-output 6
of DcS CPU (QD1.6) [2mA/Digit]
X
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Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
45 90
In.PWM.Current
[7] (WORD)
IPI1_7
Readback of current on PWM-output 7
of DcS CPU (QD1.7) [2mA/Digit]
X
46 92
In.PWM.Current
[8] (WORD)
IPI1_8
Readback of current on PWM-output 8
of DcS CPU (QD1.8) [2mA/Digit]
X
General Input Variables of the Control Unit (TCOMMONIN)
47 94
In.Common.Awp
Cycle (BYTE)
I_AWPCycle Duration of the last AWP-cycle [ms] X
95
In.Common.Wdg
Reset (BYTE)
I_WdgReset
Detection of a Watch-Dog-Reset on the DcS
CPU (TRUE -> Watch-Dog-Reset occurred)
X
48 96
In.Common.Pwr
Fail (BYTE)
I_PwrFail
Detection of an undervoltage VIM on the DcS
CPU (TRUE = VIM smaller than 8V in the
12V-system or smaller than 16V in the 24V-
system)
X
97
In.Common.PWR
_VIQ1 (BYTE)
I_PWR_VIQ1
Readback of the load supply voltage VIQ1 of
DcS CPU
X
49 98 not used
99
In.Common.PWR
_VIQ2 (BYTE)
I_PWR_VIQ2
Digital input for the load supply voltage VIQ2
of DcS I/O
X
50 100
In.Common.
SRAMchecked
(INT)
I_SRAMchecked
Number of test runs in the SRAM of DcS CPU
(-1 stands for error)
X
51 102
In.Common.
FWchecked (INT)
I_Fwchecked
Number of test runs of the firmware in the
flash of DcS CPU (-1 stands for error)
X
52 104
In.Common.
Nodestate
(BYTE)
I_Nodestate
Indicates the NMS-state of the CAN-node
(0=Initializing, 1=Disconnected, 2=Connec-
ting, 3= Preparing, 4=PREPARED,
5=OPERATIONAL, 127=PREOPERA-
TIONAL; s. ENUM EnodeState)
X
105
In.Common.
AWPchecked
(INT)
I_AWPchecked
Number of test runs of the AWP(appl. progr.)
in the flash of DcS CPU (-1 stands for error)
X
Input Variables of the CAN-Bus on the DcS I/O (TCANIOIN)
53 106
In.CAN.Active
(BYTE)
CANActive_In
Indication as to whether the communication
partner is transmitting in the DcS I/O (1 ->
cyclic transmission 2 -> WRN(Activation of
the SHDN) 4 -> BOFF(Activation of SHDN))
X
54 108
In.CAN.Data
(BYTE)
Input data from the CAN-Bus of DcS I/O;
Permissible data types: TCanIOMobaRx,
TCanIOJ1939Rx, TCanIODeutzRx, ,
TCanIOMuxRx
X
TCanIO
MuxRx
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Input operand as Symbol address acc. to Description on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
Output Variables for the Digital Outputs (TDIGOUTOUT)
0 0
Out.DigOut.Value
(WORD)
QD
Digital outputs of DcS CPU and I/O
(QD1.1..QD1.8 und QD2.1..QD2.8)
X X 2#0
0.0 QD1_1 Digital output 1 of DcS CPU (QD1.1) X 2#0
0.1 QD1_2 Digital output 2 of DcS CPU (QD1.2) X 2#0
0.2 QD1_3 Digital output 3 of DcS CPU (QD1.3) X 2#0
0.3 QD1_4 Digital output 4 of DcS CPU (QD1.4) X 2#0
0.4 QD1_5 Digital output 5 of DcS CPU (QD1.5) X 2#0
0.5 QD1_6 Digital output 6 of DcS CPU (QD1.6) X 2#0
0.6 QD1_7 Digital output 7 of DcS CPU (QD1.7) X 2#0
0.7 QD1_8 Digital output 8 of DcS CPU (QD1.8) X 2#0
1 0.8 QD2_1 Digital output 1 of DcS I/O (QD2.1) X 2#0
0.9 QD2_2 Digital output 2 of DcS I/O (QD2.2) X 2#0
0.10 QD2_3 Digital output 3 of DcS I/O (QD2.3) X 2#0
0.11 QD2_4 Digital output 4 of DcS I/O (QD2.4) X 2#0
0.12 QD2_5 Digital output 5 of DcS I/O (QD2.5) X 2#0
0.13 QD2_6 Digital output 6 of DcS I/O (QD2.6) X 2#0
0.14 QD2_7 Digital output 7 of DcS I/O (QD2.7) X 2#0
0.15 QD2_8 Digital output 8 of DcS I/O (QD2.8) X 2#0
Output Variables for the Counting Inputs (TCOUNTEROUT)
1 2
Out.Cnt.Time
Wnd[1] (WORD)
IC1_1_TimeWnd
Time window of counting input 1
of DcS CPU in [ms]
X 2#0
2 4
Out.Cnt.Time
Wnd[2] (WORD)
IC1_2_TimeWnd
Time window of counting input 2
of DcS CPU in [ms]
X 2#0
3 6
Out.Cnt.Time
Wnd[3] (WORD)
IC2_1_TimeWnd
Time window of counting input 1
of DcS I/O in [ms]
X 2#0
4 8
Out.Cnt.Time
Wnd[4] (WORD)
IC2_2_TimeWnd
Time window of counting input 2
of DcS I/O in [ms]
X 2#0
5 10
Out.Cnt.Time
Wnd[5] (WORD)
IC3_1_TimeWnd
Time window of counting input 3
of DcS I/O in [ms]
X 2#0
6 12
Out.Cnt.Time
Wnd[6] (WORD)
IC3_2_TimeWnd
Time window of counting input 4
of DcS I/O in [ms]
X 2#0
7 14
Out.Cnt.Time
Wnd[7] (WORD)
IC4_1_TimeWnd
Time window of counting input 5
of DcS I/O in [ms]
X 2#0
8 16
Out.Cnt.Time
Wnd[8] (WORD)
IC4_2_TimeWnd
Time window of counting input 6
of DcS I/O in [ms]
X 2#0
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Input operand as Symbol address acc. to Description on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
9 18
Out.Cnt.Start
(BYTE)
IC_Start
Starting/Stopping the counting on the
counting inputs of DcSs CPU and I/O
(IC1.1..IC1.2 and IC2.1..IC4.2 on
ID1.11..ID1.12 and ID2.9..2.14)
X X 2#0
9.0 IC_1_1_Start
Starting the counting on counting input 1
of DcS CPU (IC1.1 or ID1.11)
X 2#0
9.1 IC_1_2_Start
Starting the counting on counting input 2
of DcS CPU (IC1.2 or ID1.12)
X 2#0
9.2 IC_2_1_Start
Starting the counting on counting input 1
of DcS I/O (IC2.1 or ID2.11)
X 2#0
9.3 IC_2_2_Start
Starting the counting on counting input 2
of DcS I/O (IC2.2 or ID2.12)
X 2#0
9.4 IC_3_1_Start
Starting the counting on counting input 3
of DcS I/O (IC3.1 or ID2.9)
X 2#0
9.5 IC_3_2_Start
Starting the counting on counting input 4
of DcS I/O (IC3.2 or ID2.10)
X 2#0
9.6 IC_4_1_Start
Starting the counting on counting input 5
of DcS I/O (IC4.1 or ID2.13)
X 2#0
9.7 IC_4_2_Start
Starting the counting on counting input 6
of DcS I/O (IC4.2 or ID2.14)
X 2#0
19
Out.Cnt.Reset
(BYTE)
IC_Reset
Resetting the counter values (with concurrent
stopping) on the counting inputs of DcSs CPU
and I/O (IC1.1..IC1.2 and IC2.1..IC4.2 on
ID1.11..ID1.12 and ID2.9..2.14)
X X 2#0
9.8 IC_1_1_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 1of DcS CPU
(IC1.1 or ID1.11)
X 2#0
9.9 IC_1_2_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 2 of DcS CPU
(IC1.2 or ID1.12)
X 2#0
9.10 IC_2_1_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 1 of DcS I/O
(IC2.1 or ID2.11)
X 2#0
9.11 IC_2_2_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 2 of DcS I/O
(IC2.2 or ID2.12)
X 2#0
9.12 IC_3_1_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 3 of DcS I/O
(IC3.1 or ID2.9)
X 2#0
9.13 IC_3_2_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 4 of DcS I/O
(IC3.2 or ID2.10)
X 2#0
9.14 IC_4_1_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 5 of DcS I/O
(IC4.1 or ID2.13)
X 2#0
9.15 IC_4_2_Reset
Resetting the counter values (with concurrent
stopping) on the counting input 6 of DcS I/O
(IC4.2 or ID2.14)
X 2#0
Analog Outputs (TANOUTOUT)
10 20
Out.AnOut.Value
[1] (WORD)
QAI1
Output value of Analog output 1 of DcS I/O
(QAI1) [Digits] (0 to 500 Digits = 0 to +20mA)
X 2#0
11 22
Out.AnOut.Value
[2] (WORD)
QAI2
Output value of Analog output 2 of DcS I/O
(QAI2) [Digits] (0 to 500 Digits = 0 to +20mA)
X 2#0
12 24
Out.AnOut.Value
[3] (WORD)
QAI3
Output value of Analog output 3 of DcS I/O
(QAI3) [Digits] (0 to 500 Digits = 0 to +20mA)
X 2#0
13 26
Out.AnOut.Value
[4] (WORD)
QAI4
Output value of Analog output 4 of DcS I/O
(QAI4) [Digits] (0 to 500 Digits = 0 to +20mA)
X 2#0
PWM-Outputs (TPWMOUT)
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-10
Input operand as Symbol address acc. to Description on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
14 28
Out.PWM.Freq[1]
(WORD)
QP1_Freq
Frequency of the PWM-output 1 of DcS CPU
(QD1.1) [Hz] Range: 50 to 1200Hz
X 10#400
15 30
Out.PWM.Freq[2]
(WORD)
QP2_Freq
Frequency of the PWM-output 2 of DcS CPU
(QD1.2) [Hz] Range: 50 to 1200Hz
X 10#400
16 32
Out.PWM.Freq[3]
(WORD)
QP3_Freq
Frequency of the PWM-output 3 of DcS CPU
(QD1.3) [Hz] Range: 50 to 1200Hz
X 10#400
17 34
Out.PWM.Freq[4]
(WORD)
QP4_Freq
Frequency of the PWM-output 4 of DcS CPU
(QD1.4) [Hz] Range: 50 to 1200Hz
X 10#400
18 36
Out.PWM.Freq[5]
(WORD)
QP5_8_Freq
Frequency of the PWM-outputs 5..8 of DcS
CPU (QD1.5..QD1.8) [Hz] Range: 50 to
1200Hz
X 10#400
19 38
Out.PWM.Pwidth
[1] (WORD)
QP1_PWidth
Pulse width of the PWM-output 1of DcS CPU
(QD1.1) [Digits] Range: 0 to 1023 Digits
X 2#0
20 40
Out.PWM.Pwidth
[2] (WORD)
QP2_PWidth
Pulse width of the PWM-output 2 of DcS CPU
(QD1.2) [Digits] Range: 0 to 1023 Digits
X 2#0
21 42
Out.PWM.Pwidth
[3] (WORD)
QP3_PWidth
Pulse width of the PWM-output 3 of DcS CPU
(QD1.3) [Digits] Range: 0 to 1023 Digits
X 2#0
22 44
Out.PWM.Pwidth
[4] (WORD)
QP4_PWidth
Pulse width of the PWM-output 4 of DcS CPU
(QD1.4) [Digits] Range: 0 to 1023 Digits
X 2#0
23 46
Out.PWM.Pwidth
[5] (WORD)
QP5_PWidth
Pulse width of the PWM-output 5 of DcS CPU
(QD1.5) [Digits] Range: 0 to 1023 Digits
X 2#0
24 48
Out.PWM.Pwidth
[6] (WORD)
QP6_PWidth
Pulse width of the PWM-output 6 of DcS CPU
(QD1.6) [Digits] Range: 0 to 1023 Digits
X 2#0
25 50
Out.PWM.Pwidth
[7] (WORD)
QP7_PWidth
Pulse width of the PWM-output 7 of DcS CPU
(QD1.7) [Digits] Range: 0 to 1023 Digits
X 2#0
26 52
Out.PWM.Pwidth
[8] (WORD)
QP8_PWidth
Pulse width of the PWM-output 8 of DcS CPU
(QD1.8) [Digits] Range: 0 to 1023 Digits
X 2#0
27 54
Out.PWM.Pstart
(BYTE)
QP_Start
Enabling the PWM-outputs 1 to 8 of DcS CPU
(QD1.1 to QD1.8)
X 2#0
27.0 QP1_Start
Enabling the PWM-output 1 of DcS CPU
(QD1.1)
X 2#0
27.1 QP2_Start
Enabling the PWM-output 2 of DcS CPU
(QD1.2)
X 2#0
27.2 QP3_Start
Enabling the PWM-output 3 of DcS CPU
(QD1.3)
X 2#0
27.3 QP4_Start
Enabling the PWM-output 4 of DcS CPU
(QD1.4)
X 2#0
27.4 QP5_Start
Enabling the PWM-output 5 of DcS CPU
(QD1.5)
X 2#0
27.5 QP6_Start
Enabling the PWM-output 6 of DcS CPU
(QD1.6)
X 2#0
27.6 QP7_Start
Enabling the PWM-output 7 of DcS CPU
(QD1.7)
X 2#0
27.7 QP8_Start
Enabling the PWM-output 8 of DcS CPU
(QD1.8)
X 2#0
55 not used
General Output Variables of the Control Unit (TCOMMONOUT)
28 56
Out.Common.Pwr
_Hold (BYTE)
Q_Pwr_Hold
Flag for defined switch-off of the control unit
from the AWP (appl. prog.); shall be set after
switch-on; in the case of FALSE and switched
off IPON, the control unit will be switched off
(Vcc=0)
X X 2#0
57
Out.Common.
VQSW1_OFF
(BYTE)
Q_VQSW1_OFF
Flag for switching the load supply voltage
VIQ1 from the outputs QD1.1..QD1.8
(true=outputs supplied; is currently not
supported)
X 2#0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-11
Input operand as Symbol address acc. to Description on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
29 not used
30 60
Out.Common.
SET_12_24V
(BOOL)
Change of the voltage level for the Digital
inputs on the I/O
TRUE -> 24V
FALSE -> 12V
X
61 not used
Output variables of the CAN-Bus of the DcS I/O (TCANIOOUT)
31 62
Out.CAN.Mode
(BYTE)
Q_CAN_Mode
Possible modes: 0=no mode, 1=MOBA,
2=J1939, 3=Deutz Motor connection J1939
X 10#0
63
Out.CAN.Timeout
(BYTE)
Q_CAN_Timeout
Timeout of the CAN of DcS I/O in steps of
[10ms] (0=no Timeout)
X 10#200
32 64
Out.CAN.Speed
(ECanSpeed)
Q_CAN_Speed
Transmission speed of the CAN of DcS I/O
(Data type from enumeration structure
EcanSpeed in the library Prosyd.lib)
X
KBD_
125
33 66 Out.CAN.Data
From here all output-PDOs of the CAN-bus
(Permissible data types: TCanIOMobaTx,
TCanIOJ1939Tx, TCanIODeutzTx,
TCanIOMuxTx)
X
TcanIO
MuxTx
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-12
N.5 System Input Operands of the digsy

compact
E
Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
96 192
SysIn.initialized
(BYTE)
SYSIN_WasInit
Flag for the first AWP-processing (true=first
AWP-run (is/was) effected, false=AWP not
yet started)
X
193
SysIn.SW_Major
(BYTE)
SYSIN_CPU_SW
_Major
Majority-version of the software of DcS CPU X
97 194
SysIn.SW_Minor
(BYTE)
SYSIN_CPU_SW
_Minor
Minority-version of the software of DcS CPU X
195
SysIn.SW_Bugfix
(BYTE)
SYSIN_CPU_SW
_Bugfix
Bugfix-version of the software of DcS CPU X
98 196
SysIn.HW_Major
(BYTE)
SYSIN_CPU_Har
dware_Major
Majority-version of the hardware of DcS CPU X
197
SysIn.HW_Minor
(BYTE)
SYSIN_CPU_Har
dware_Minor
Minority-version of the hardware of DcS CPU X
99 198 not used
199
SysIn.RetainIdx
(BYTE)
SYSIN_RetainIdx Current Retain data block X X
100 200
SysIn.Retain
Length (WORD)
SYSIN_Retain
Length
Provides the current Retain data length X X
101 202
SysIn.Retain
Pcycles (WORD)
SYSIN_Retain
PCycles
Number of the Retain programming cycles so
far
X X
102 204
SysIn.CanType
(BYTE)
SYSIN_CANType
Type of the implemented CAN-protocol
(0=CANopen-Slave)
X X
205
SysIn.CanNode
State (BYTE)
SYSIN_CAN
NodeState
NMS-state of the CAN-node X X
103 206
SysIn.ErrorCnt
(WORD)
SYSIN_ErrorCnt Provides the current error counter status X X
104 208
SysIn.IO_SW_
Major (BYTE)
SYSIN_IO_SW_
Major
Majority-version of the software of DcS I/O X
209
SysIn.IO_SW_
Minor (BYTE)
SYSIN_IO_SW_
Minor
Minority-version of the software of DcS I/O X
105 210
SysIn.IO_SW_
Bugfix (BYTE)
SYSIN_IO_SW_
Bugfix
Bugfix-version of the software of DcS I/O X
211
SysIn.IO_HW_
Major (BYTE)
SYSIN_IO_HW_
Major
Majority-version of the hardware of DcS I/O X
106 212
SysIn.IO_HW_Mi
nor (BYTE)
SYSIN_IO_HW_
Minor
Minority-version of the hardware of DcS I/O X
213
SysIn.FlManu
Code (BYTE)
SYSIN_FlManu
Code
Manufacturing Code of the Flash-EPROM
being on the DcS CPU
X
107 214
SysIn.FlIdent
(BYTE)
SYSIN_FlIdent
Identity Code of the Flash-EPROM being on
the DcS CPU
X
215
SysIn.PWR_VIQ1
(BYTE)
SYSIN_PWR_
VIQ1
Readback of the load supply voltage VIQ1 of
DcS CPU
X
108
SysIn.cnt_PWR_
IPON-Changes
(WORD)
SYSIN_PWR_
IPON_Changes
Number of the IPON switching operations
(only change from high to low)
X
109 218
SysIn.PWR_
IPON (BYTE)
SYSIN_PWR_
IPON
State of the switching input IPON X
219
SysIn.PWR_FAIL
_Voltage(BYTE)
SYSIN_PWR_
FAIL
Detection of an undervoltage VIM on DcS
CPU (TRUE = VIM smaller than 8V in 12V-
system or smaller than 16V in 24V-system)
X
110 220
SysIn.cnt_PWR_
FAIL (WORD)
SYSIN_CNT_
PWR_FAIL
Number of the detected undervoltages (VIM
smaller than 8V in 12V-system or VIM smaller
than 16V in 24V-system)
X
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-13
Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
111 222
SysIn.readCfg
10msTask[1]
(WORD)
SYSIN_CFG
10MS_1
Configuring the 1st millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
112 224
SysIn.readCfg
10msTask[2]
(WORD)
SYSIN_CFG
10MS_2
Configuring the 2nd millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
113 226
SysIn.readCfg
10msTask[3]
(WORD)
SYSIN_CFG
10MS_3
Configuring the 3rd millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
114 228
SysIn.readCfg
10msTask[4]
(WORD)
SYSIN_CFG
10MS_4
Configuring the 4th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
115 230
SysIn.readCfg
10msTask[5]
(WORD)
SYSIN_CFG
10MS_5
Configuring the 5th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
116 232
SysIn.readCfg
10msTask[6]
(WORD)
SYSIN_CFG
10MS_6
Configuring the 6th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
117 234
SysIn.readCfg
10msTask[7]
(WORD)
SYSIN_CFG
10MS_7
Configuring the 7th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
118 236
SysIn.readCfg
10msTask[8]
(WORD)
SYSIN_CFG
10MS_8
Configuring the 8th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
119 238
SysIn.readCfg
10msTask[9]
(WORD)
SYSIN_CFG
10MS_9
Configuring the 9th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
120 240
SysIn.readCfg
10msTask[10]
(WORD)
SYSIN_CFG
10MS_10
Configuring the 10th millisecond of the 10ms
task (low Byte indicates active channel,
Assignment: Bit 0 -> QP1, Bit 1 -> QP2, etc.,
Bit 8..14 irrelevant, Bit 15 = call-up active)
X
121 242
SysIn.maxCur
rentToMeasure[1]
(WORD)
SYSIN_MAX_
IPI1_1
Maximum current to be measured on current
measuring channel 1 (QD1.1) [2mA/Digit]
X
122 244
SysIn.maxCur
rentToMeasure[2]
(WORD)
SYSIN_MAX_
IPI1_2
Maximum current to be measured on current
measuring channel 2 (QD1.1) [2mA/Digit]
X
123 246
SysIn.maxCur
rentToMeasure[3]
(WORD)
SYSIN_MAX_
IPI1_3
Maximum current to be measured on current
measuring channel 3 (QD1.1) [2mA/Digit]
X
124 248
SysIn.maxCur
rentToMeasure[4]
(WORD)
SYSIN_MAX_
IPI1_4
Maximum current to be measured on current
measuring channel 4 (QD1.1) [2mA/Digit]
X
125 250
SysIn.maxCur
rentToMeasure[5]
(WORD)
SYSIN_MAX_
IPI1_5
Maximum current to be measured on current
measuring channel 5 (QD1.1) [2mA/Digit]
X
126 252
SysIn.maxCur
rentToMeasure[6]
(WORD)
SYSIN_MAX_
IPI1_6
Maximum current to be measured on current
measuring channel 6 (QD1.1) [2mA/Digit]
X
127 254
SysIn.maxCur
rentToMeasure[7]
(WORD)
SYSIN_MAX_
IPI1_7
Maximum current to be measured on current
measuring channel 7 (QD1.1) [2mA/Digit]
X
128 256
SysIn.maxCur
rentToMeasure[8]
(WORD)
SYSIN_MAX_
IPI1_8
Maximum current to be measured on current
measuring channel 8 (QD1.1) [2mA/Digit]
X
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-14
Input operand as Symbol address acc. to Description on Default
%IW
(Word)
%IB
(Byte)
%IX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
129 258
SysIn.statePWM
OffsetCalibration
(BYTE)
State of the Offset-calibration of the PWM
current measurement (true=calibrated)
X
259
SysIn.statePWM
GradientCalibra
tion (BYTE)
Status of the Gradient calibration of the PWM
current measurement (true=calibrated)
X
130 not used
131 262
SysIn.DayOf
Week (BYTE)
SYSIN_DAYOF
WEEK
Reading out the weekday of the real-time
clock (0=Sunday, 1=Monday, .., 6=Saturday)
(Only valid with RTC_Date-flag set in
SystemCfg)
X
263
SysIn.Week
(BYTE)
SYSIN_WEEK
Reading out the calendar week of the real-
time clock (only valid with RTC_Date-flag set
in SystemCfg)
X
132 264
SysIn.RTC_Date
(DATE)
SYSIN_RTC_
DATE
Reading out the date of the real-time clock
(Notation: YYYY-MM-DD) (Only valid with
RTC_Date-flag set in SystemCfg)
X
134 268
SysIn.RTC_Date
AndTime (DATE_
AND_TIME)
SYSIN_RTC_
DATEANDTIME
Reading out the date and time of the real-time
clock (Notation: YYYY-MM-DD-hh:mm:ss)
(Only valid with RTC_Date-flag set in
SystemCfg)
X
136 not used
: :
159 not used
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-15
N.6 System Output Operands of the digsy

compact
E
Input operand as Symbol address acc. to Description on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
96 192
SysOut.initialized
(BYTE)
SYSOUT_Was
Init
Flag for one-time processing of the
AWP(appl. progr.)-cycle
X
193
SysOut.set_Can
Type (BYTE)
SYSOUT_set
CANType
Sets the type of the CAN-protocol
(0=CANopen-Slave)
X
97 194
SysOut.set_Can
NodeState
(BYTE)
SYSOUT_set
CANNodeState
Sets the NMS-state of the CAN-node X
195
SysOut.en_
emergency
(BYTE)
SYSOUT_
ENABLE_
EMERGENCY
Mask for Emergency-readouts on the CAN-
bus (0=no message, 1=normal message,
2=warning, 4=user error, 8=application error,
16=system error, 31=all)
X 2#0
98 196
SysOut.wSet_
VCP (WORD)
SYSOUT_SET_
VCP
Setting the Offset voltage VCP for the inputs
ID1.9..ID1.12 on the DcS CPU [mV]
(0..34500mV in steps of 138mV)
X 10#0
99 198
SysOut.wSet_
VTS (WORD)
SYSOUT_SET_
VTS
Setting the Test ramp VTS for testing the
function of the AD-converter on the DcS CPU
[mV] (0..34500mV in steps of 138mV)
(presently not supported)
X 2#0
100 200
SysOut.bReset
WdgFlag (BYTE)
SYSOUT_
RESET_WDG
Resetting the Watchdog counter WdgReset in
TCommonIn with rising edge
X 2#0
201
SysOut.bActivate
_setting_VCP
(BYTE)
SYSOUT_
ACTIVATE_VCP
Activating the Offset voltage wSet_VCP X 2#0
101 not used
: :
127 not used
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-16
N.7 Configuration Operands of the digsy

compact
E
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
Configuration Variables for the Digital Inputs (TDIGINCFG)
128 256
Cfg.DigIn.Used[1]
(WORD)
CFG_ID_CPU
Using the Digital inputs of DcS CPU (ID1.1 to
ID1.12) - dyncfg
X 0
128.0 CFG_ID1_1
Using the Digital input 1
of DcS CPU (ID1.1) - dyncfg
X 0
128.1 CFG_ID1_2
Using the Digital input 2
of DcS CPU (ID1.2) - dyncfg
X 0
128.2 CFG_ID1_3
Using the Digital input 3
of DcS CPU (ID1.3) - dyncfg
X 0
128.3 CFG_ID1_4
Using the Digital input 4
of DcS CPU (ID1.4) - dyncfg
X 0
128.4 CFG_ID1_5
Using the Digital input 5
of DcS CPU (ID1.5) - dyncfg
X 0
128.5 CFG_ID1_6
Using the Digital input 6
of DcS CPU (ID1.6) - dyncfg
X 0
128.6 CFG_ID1_7
Using the Digital input 7
of DcS CPU (ID1.7) - dyncfg
X 0
128.7 CFG_ID1_8
Using the Digital input 8
of DcS CPU (ID1.8) - dyncfg
X 0
257 128.8 CFG_ID1_9
Using the Digital input 9
of DcS CPU (ID1.9) - dyncfg
X 0
128.9 CFG_ID1_10
Using the Digital input 10
of DcS CPU (ID1.10) - dyncfg
X 0
128.10 CFG_ID1_11
Using the Digital input 11
of DcS CPU (ID1.11) (Has to be set to 0
when used as counter IC1.1) - dyncfg
X 0
128.11 CFG_ID1_12
Using the Digital input 12
of DcS CPU (ID1.12) (Has to be set to 0
when used as counter IC1.2) - dyncfg
X 0
128.12 not used
: :
128.15 not used
129 258
Cfg.DigIn.Used[2]
(WORD)
CFG_ID_IO
Using the Digital inputs of DcS I/O (ID2.1 to
ID2.14) dyncfg
X 0
129.0 CFG_ID2_1
Using the Digital input 1
of DcS I/O (ID2.1) dyncfg
X 0
129.1 CFG_ID2_2
Using the Digital input 2
of DcS I/O (ID2.2) dyncfg
X 0
129.2 CFG_ID2_3
Using the Digital input 3
of DcS I/O (ID2.3) dyncfg
X 0
129.3 CFG_ID2_4
Using the Digital input 4
of DcS I/O (ID2.4) dyncfg
X 0
129.4 CFG_ID2_5
Using the Digital input 5
of DcS I/O (ID2.5) dyncfg
X 0
129.5 CFG_ID2_6
Using the Digital input 6
of DcS I/O (ID2.6) dyncfg
X 0
129.6 CFG_ID2_7
Using the Digital input 7
of DcS I/O (ID2.7) dyncfg
X 0
129.7 CFG_ID2_8
Using the Digital input 8
of DcS I/O (ID2.8) dyncfg
X 0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-17
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
259 129.8 CFG_ID2_9
Using the Digital input 9
of DcS I/O (ID2.9) (Has to be set to 0 when
used as counter IC3.1) - dyncfg
X 2#0
129.9 CFG_ID2_10
Using the Digital input 10
of DcS I/O (ID2.10) (Has to be set to 0 when
used as counter IC3.2) - dyncfg
X 2#0
129.10 CFG_ID2_11
Using the Digital input 11
of DcS I/O (ID2.11) (Has to be set to 0 when
used as counter IC2.1) - dyncfg
X 2#0
129.11 CFG_ID2_12
Using the Digital input 12
of DcS I/O (ID2.12) (Has to be set to 0 when
used as counter IC2.2) - dyncfg
X 2#0
129.12 CFG_ID2_13
Using the Digital input 13
of DcS I/O (ID2.13) (Has to be set to 0 when
used as counter IC4.1) - dyncfg
X 2#0
129.13 CFG_ID2_14
Using the Digital input 14
of DcS I/O (ID2.14) (Has to be set to 0 when
used as counter IC4.2) - dyncfg
X 2#0
129.14 not used
129.15 not used
130 260
Cfg.DigIn.Used[3]
(WORD)
CFG_QD_AS_ID
Using the Digital outputs of DcS I/O as Digital
inputs (QD2.1 to QD2.8) - dyncfg
X 0
130.0
CFG_QD2_1_AS
_ID3_1
Using the Digital output 1
of DcS I/O as Digital input (QD2.1) - dyncfg
X 0
130.1
CFG_QD2_2_AS
_ID3_2
Using the Digital output 2
of DcS I/O as Digital input (QD2.2) - dyncfg
X 0
130.2
CFG_QD2_3_AS
_ID3_3
Using the Digital output 3
of DcS I/O as Digital input (QD2.3) - dyncfg
X 0
130.3
CFG_QD2_4_AS
_ID3_4
Using the Digital output 4
of DcS I/O as Digital input (QD2.4) - dyncfg
X 0
130.4
CFG_QD2_5_AS
_ID3_5
Using the Digital output 5
of DcS I/O as Digital input (QD2.5) - dyncfg
X 0
130.5
CFG_QD2_6_AS
_ID3_6
Using the Digital output 6
of DcS I/O as Digital input (QD2.6) - dyncfg
X 0
130.6
CFG_QD2_7_AS
_ID3_7
Using the Digital output 7
of DcS I/O as Digital input (QD2.7) - dyncfg
X 0
130.7
CFG_QD2_8_AS
_ID3_8
Using the Digital output 8
of DcS I/O as Digital input (QD2.8) - dyncfg
X 0
261 not used
131 262
Cfg.DigIn.Group
(BYTE)
CFG_ID_GROUP
Configuring the active switching levels of the
Digital inputs of DcSs CPU and I/O
(1=plusswitching, 0=groundswitching) -
dyncfg
X X 0
131.0
CFG_ID_
GROUP_1
Configuring the active switching levels of the
Digital inputs 1 to 5 of DcS CPU (ID1.1 to
ID1.4) (1=plusswitching, 0=groundswitching) -
dyncfg
X 0
131.1
CFG_ID_
GROUP_2
Configuring the active switching levels of the
Digital inputs 6 to 10 of DcS CPU
(ID1.4 to ID1.8) (1=plusswitching,
0=groundswitching) - dyncfg
X 0
131.2
CFG_ID_
GROUP_3
Configuring the active switching levels of the
Digital inputs 1 to 4 of DcS I/O
(ID2.1 to ID2.4) (1=plusswitching,
0=groundswitching) - dyncfg
X 0
131.3
CFG_ID_
GROUP_4
Configuring the active switching levels of the
Digital inputs 5 to 8 of DcS I/O
(ID2.5 to ID2.8) (1=plusswitching,
0=groundswitching) - dyncfg
X 0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-18
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
131.4 not used
: :
131.7 not used
263 not used
132 264
Cfg.DigOut.Used
(WORD)
CFG_QD
Using the Digital outputs of DcS CPU and I/O
(QD1.1..QD1.8 and QD2.1..QD2.8) - dyncfg
X X
132.0 CFG_QD1_1
Using the Digital output 1
of DcS CPU (QD1.1) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.1 CFG_QD1_2
Using the Digital output 2
of DcS CPU (QD1.2) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.2 CFG_QD1_3
Using the Digital output 3
of DcS CPU (QD1.3) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.3 CFG_QD1_4
Using the Digital output 4
of DcS CPU (QD1.4) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.4 CFG_QD1_5
Using the Digital output 5
of DcS CPU (QD1.5) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.5 CFG_QD1_6
Using the Digital output 6
of DcS CPU (QD1.6) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.6 CFG_QD1_7
Using the Digital output 7
of DcS CPU (QD1.7) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
132.7 CFG_QD1_8
Using the Digital output 8
of DcS CPU (QD1.8) (Has to be set to 0
when used as a PWM-output) - dyncfg
X
265 132.8 CFG_QD2_1
Using the Digital output 1
of DcS I/O (QD2.1) - dyncfg
X
132.9 CFG_QD2_2
Using the Digital output 2
of DcS I/O (QD2.2) - dyncfg
X
132.10 CFG_QD2_3
Using the Digital output 3
of DcS I/O (QD2.3) - dyncfg
X
132.11 CFG_QD2_4
Using the Digital output 4
of DcS I/O (QD2.4) - dyncfg
X
132.12 CFG_QD2_5
Using the Digital output 5
of DcS I/O (QD2.5) - dyncfg
X 0
132.13 CFG_QD2_6
Using the Digital output 6
of DcS I/O (QD2.6) - dyncfg
X 0
132.14 CFG_QD2_7
Using the Digital output 7
of DcS I/O (QD2.7) - dyncfg
X 0
132.15 CFG_QD2_8
Using the Digital output 8
of DcS I/O (QD2.8) - dyncfg
X 0
Configuration Variables for the Analog Inputs (TANINCFG)
133 266
Cfg.AnIn.Used
(BYTE)
CFG_IA_Used
Using the Analog inputs of DcS CPU and I/O
(IAV1.1..IAV1.4, IAV2.1..IAV2.4 or
IAI1.1..IAI1.4, IAI2.1..IAI2.4) - dyncfg
X X 0
133.0
CFG_IA1_1_
Used
Using the Analog input 1
of DcS CPU (IAV1.1 or IAI1.1) - dyncfg
X 0
133.1
CFG_IA1_2_
Used
Using the Analog input 2
of DcS CPU (IAV1.2 or IAI1.2) - dyncfg
X 0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-19
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
133.2
CFG_IA1_3_
Used
Using the Analog input 3
of DcS CPU (IAV1.3 or IAI1.3) - dyncfg
X 0
133.3
CFG_IA1_4_
Used
Using the Analog input 4
of DcS CPU (IAV1.4 or IAI1.4) - dyncfg
X 0
133.4
CFG_IA2_1_
Used
Using the Analog input 1
of DcS I/O (IAV2.1 or IAI2.1) - dyncfg
X 0
133.5
CFG_IA2_2_
Used
Using the Analog input 2
of DcS I/O (IAV2.2 or IAI2.2) - dyncfg
X 0
133.6
CFG_IA2_3_
Used
Using the Analog input 3
of DcS I/O (IAV2.3 or IAI2.3) - dyncfg
X 0
133.7
CFG_IA2_4_
Used
Using the Analog input 4
of DcS I/O (IAV2.4 or IAI2.4) - dyncfg
X 0
267 not used
134 268
Cfg.AnIn.Upper
Limit [1] (WORD)
CFG_IA1_1_
LimitUp
Upper limiting value of the Analog input 1
of DcS CPU (IAV1.1 or IAI1.1) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
135 270
Cfg.AnIn.Upper
Limit [2] (WORD)
CFG_IA1_2_
LimitUp
Upper limiting value of the Analog input 2
of DcS CPU (IAV1.2 or IAI1.2) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
136 272
Cfg.AnIn.Upper
Limit [3] (WORD)
CFG_IA1_3_
LimitUp
Upper limiting value of the Analog input 3
of DcS CPU (IAV1.3 or IAI1.3) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
137 274
Cfg.AnIn.Upper
Limit [4] (WORD)
CFG_IA1_4_
LimitUp
Upper limiting value of the Analog input 4
of DcS CPU (IAV1.4 or IAI1.4) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
138 276
Cfg.AnIn.Upper
Limit [5] (WORD)
CFG_IA2_1_
LimitUp
Upper limiting value of the Analog input 1
of DcS I/O (IAV2.1 or IAI2.1) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
139 278
Cfg.AnIn.Upper
Limit [6] (WORD)
CFG_IA2_2_
LimitUp
Upper limiting value of the Analog input 2
of DcS I/O (IAV2.2 or IAI2.2) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
140 280
Cfg.AnIn.Upper
Limit [7] (WORD)
CFG_IA2_3_
LimitUp
Upper limiting value of the Analog input 3
of DcS I/O (IAV2.3 or IAI2.3) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
141 282
Cfg.AnIn.Upper
Limit [8] (WORD)
CFG_IA2_4_
LimitUp
Upper limiting value of the Analog input 4
of DcS I/O (IAV2.4 or IAI2.4) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0FFF
142 284
Cfg.AnIn.Lower
Limit [1] (WORD)
CFG_IA1_1_
LimitLow
Lower limiting value of the Analog input 1
of DcS CPU (IAV1.1 or IAI1.1) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
143 286
Cfg.AnIn.Lower
Limit [2] (WORD)
CFG_IA1_2_
LimitLow
Lower limiting value of the Analog input 2
of DcS CPU (IAV1.2 or IAI1.2) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
144 288
Cfg.AnIn.Lower
Limit [3] (WORD)
CFG_IA1_3_
LimitLow
Lower limiting value of the Analog input 3
of DcS CPU (IAV1.3 or IAI1.3) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
145 290
Cfg.AnIn.Lower
Limit [4] (WORD)
CFG_IA1_4_
LimitLow
Lower limiting value of the Analog input 4
of DcS CPU (IAV1.4 or IAI1.4) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
146 292
Cfg.AnIn.Lower
Limit [5] (WORD)
CFG_IA2_1_
LimitLow
Lower limiting value of the Analog input 1
of DcS I/O (IAV2.1 or IAI2.1) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
147 294
Cfg.AnIn.Lower
Limit [6] (WORD)
CFG_IA2_2_
LimitLow
Lower limiting value of the Analog input 2
of DcS I/O (IAV2.2 or IAI2.2) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
148 296
Cfg.AnIn.Lower
Limit [7] (WORD)
CFG_IA2_3_
LimitLow
Lower limiting value of the Analog input 3
of DcS I/O (IAV2.3 or IAI2.3) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
149 298
Cfg.AnIn.Lower
Limit [8] (WORD)
CFG_IA2_4_
LimitLow
Lower limiting value of the Analog input 4
of DcS I/O (IAV2.4 or IAI2.4) [Digit]
(Range: 0 to 1023 Digits) - dyncfg
X
16#
0000
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-20
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
150 300
Cfg.AnIn.VQS_
VCP_UpperLimit
(WORD)
CFG_VQS_VCP_
LimitUp
Upper limiting value of the offset voltage VCP
for the inputs ID1.9..ID1.12 on the DcS CPU
in [mV] (Range: 0 to 32000mV)
X
16#
7D00
151 302
Cfg.AnIn.VIMP_
UpperLimit
(WORD)
CFG_VIMP_
LimitUp
Upper limiting value of the operating voltage
VIMP of DcS CPU in [100mV] (Range: 90 to
320 corresponds with 9 to 32V )
X 10#350
152 304
Cfg.AnIn.TEMP_
UpperLimit
(WORD)
CFG_TEMP_
LimitUp
Upper limiting value of temperature of DcS
CPU in [K] (Range: 243 to 393K)
X 10#393
153 306
Cfg.AnIn.RAMPE
_UpperLimit
(WORD)
CFG_RAMPE_
LimitUp
Upper limiting value of test ramp VTS of DcS
CPU in [Digit] (Range: 0 to 1023 Digits)
(presently without function)
X
16#
03FF
154 308
Cfg.AnIn.VQS_
VCP_LowerLimit
(WORD)
CFG_VQS_VCP_
LimitLow
Lower limiting value of offset voltage VCP for
the inputs ID1.9..ID1.12 on the DcS CPU in
[mV] (Range: 0 to 32000mV)
X
16#
0000
155 310
Cfg.AnIn.VIMP_
LowerLimit
(WORD)
CFG_VIMP_
LimitLow
Lower limiting value of operating voltage
Vimp of DcS CPU in [Digit] (0 to 1023 ->
1Digit corresponds to 10mV)
X 10#90
156 312
Cfg.AnIn.TEMP_
LowerLimit
(WORD)
CFG_TEMP_
LimitLow
Lower limiting value of temperature
of DcS CPU in [K] (Range: 243 to 393K)
X 10#243
157 314
Cfg.AnIn.RAMPE
_LowerLimit
(WORD)
CFG_RAMPE_
LimitLow
Lower limiting value of test ramp VTS of DcS
CPU in [Digit] (Range: 0 to 1023 Digits)
(presently without function)
X
16#
0000
Configuration Variables for the Analog Outputs (TANOUTCFG)
158 316
Cfg.AnOut.Used
(BYTE)
CFG_QAI
Using the Analog Outputs 1-4
of DcS I/O (QAI1..QAI4) - dyncfg
X 0
158.0 CFG_QAI1
Using the Analog output 1
of DcS I/O (QAI1) - dyncfg
X 0
158.1 CFG_QAI2
Using the Analog output 2
of DcS I/O (QAI2) - dyncfg
X 0
158.2 CFG_QAI3
Using the Analog output 3
of DcS I/O (QAI3) - dyncfg
X 0
158.3 CFG_QAI4
Using the Analog output 4
of DcS I/O (QAI4) - dyncfg
X 0
158.4 not used
: :
158.7 not used
317 not used
Configuration Variables for the Counting Inputs (TCOUNTERCFG)
159 318
Cfg.Cnt.Used
(BYTE)
CFG_IC
Using the counting inputs
of DcS CPU and I/O
(IC1.1..IC1.2; IC2.1..IC4.2) - dyncfg
X X 0
159.0 CFG_IC1_1
Using the counting input 1
of DcS CPU (IC1.1) - dyncfg
X 0
159.1 CFG_IC1_2
Using the counting input 2
of DcS CPU (IC1.2) - dyncfg
X 0
159.2 CFG_IC2_1
Using the counting input 1
of DcS I/O (IC2.1) - dyncfg
X 0
159.3 CFG_IC2_2
Using the counting input 2
of DcS I/O (IC2.2) - dyncfg
X 0
159.4 CFG_IC3_1
Using the counting input 3
of DcS I/O (IC3.1) - dyncfg
X 0
159.5 CFG_IC3_2
Using the counting input 4
of DcS I/O (IC3.2) - dyncfg
X 0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-21
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
159.6 CFG_IC4_1
Using the counting input 5
of DcS I/O (IC4.1) - dyncfg
X 0
159.7 CFG_IC4_2
Using the counting input 6
of DcS I/O (IC4.2) - dyncfg
X 0
319
Cfg.Cnt.AB
(BYTE)
CFG_AB
Using the counting inputs of DcS I/O as AB-
counters(IC2.1 to IC4.2)
(1=AB-counter, 0=single counter) - dyncfg
X 16#00
159.8 CFG_IC1_AB_1
Using the counting input IC1 of DcS CPU as
AB-counter (A-signal) (IC1.1)
(1=AB-counter, 0=single counter)
(presently not supported, must be 0)
dyncfg
X 2#0
159.9 CFG_IC1_AB_2
Using the counting input IC1 of DcS CPU as
AB-counter (B-signal) (IC2.2)
(1=AB-counter, 0=single counter)
(presently not supported, must be 0)
dyncfg
X 2#0
159.10 CFG_IC2_AB_1
Using the counting input IC2 of DcS I/O as
AB-counter (A-signal) (IC2.1)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
159.11 CFG_IC2_AB_2
Using the counting input IC2 of DcS I/O as
AB-counter (B-signal) (IC2.2)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
159.12 CFG_IC3_AB_1
Using the counting input IC3 of DcS I/O as
AB-counter (A-signal) (IC3.1)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
159.13 CFG_IC3_AB_2
Using the counting input IC3 of DcS I/O as
AB-counter (B-signal) (IC3.2)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
159.14 CFG_IC4_AB_1
Using the counting input IC4 of DcS I/O as
AB-counter (A-signal) (IC4.1)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
159.15 CFG_IC4_AB_2
Using the counting input IC4 of DcS I/O as
AB-counter (B-signal) (IC4.2)
(1=AB-counter, 0=single counter) - dyncfg
X 2#0
Configuration variables for the PWM-Outputs (TPWMCFG)
160 320
Cfg.PWM.Used
(BYTE)
CFG_QP
Using the PWM-outputs 1 to 8
of DcS CPU (QD1.1..QD1.8) - dyncfg
X 0
160.0 CFG_QP1_1
Using the PWM-output 1
of DcS CPU (QD1.1) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.1 CFG_QP1_2
Using the PWM-output 2
of DcS CPU (QD1.2) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.2 CFG_QP1_3
Using the PWM-output 3
of DcS CPU (QD1.3) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.3 CFG_QP1_4
Using the PWM-output 4
of DcS CPU (QD1.4) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.4 CFG_QP1_5
Using the PWM-output 5
of DcS CPU (QD1.5) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.5 CFG_QP1_6
Using the PWM-output 6
of DcS CPU (QD1.6) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.6 CFG_QP1_7
Using the PWM-output 7
of DcS CPU (QD1.7) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
160.7 CFG_QP1_8
Using the PWM-output 8
of DcS CPU (QD1.8) (Has to be set to 0 if
used as a digital output) - dyncfg
X 0
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-22
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
321 not used
Configuration Variables for the General Functions of the Control Unit (TCOMMONCFG)
161 322
Cfg.Common.
AwpCycle
(BYTE)
CFG_AWPCycle
Setting a fixed AWP(appl. prog.)-cycle time
[ms] (Range: 1 to 255ms) (If the actual cycle
time of the AWP is longer than the adjusted
one, the AWP will nevertheless be completely
processed and the cycle time not kept)
X 10#5
323
Cfg.Common.
U_12_24 (BYTE)
CFG_U_12_24
Configuring the system voltage level for the
switching thresholds of the digital inputs
(possible values: 12V or 24V)
X X 10#24
162 324
Cfg.Common.
CheckSRAM
Startup (BYTE)
CFG_Check
SRAMStartup
Configuring an SRAM test run in the startup
of the DcS CPU (Notation: 2#nnnnSSSS)
In the whole RAM, (n+1) Bytes each will be
checked in step widths of ((S+1)*16).
n: number Check bytes=n+1
0=1; 1=2; ..; 16#F=16Bytes
S: Step width=S+1*16Byte
0=16; 1=32; ..; 16#F=256
Special values: 16#00=Test 1 Byte every 256
steps; 16#F0=Check of the whole RAM
X 16#00
325
Cfg.Common.
CheckSRAMRun
(BYTE)
CFG_Check
SRAMRun
Configuring a continuous SRAM-check of the
DcS CPU (Notation: 2#nnnnSSSS)
In the whole RAM, (n+1) Bytes will be
checked in step widths of ((S+1)*16) steps.
n: Number Check bytes=n+1
0=1; 1=2; ..; 16#F=16Bytes
S: Step width=S+1*16Byte
0=16; 1=32; ..; 16#F=256
Special values: 16#00= Check 1 Byte every
256 steps; 16#F0=Check of the whole RAM
X 16#00
163 326
Cfg.Common.
CheckPRG
Startup (BYTE)
CFG_Check
PRGStartup
Configuring a flash-ROM test run in the
startup of the DcS CPU (Notation:
2#nnnnmmmm)
n = reserved; m = Mode:
2#0000=Check AWP-CRC
(approx.100ms/16kByte)
2#0001=Check AWP-CKS (approx.
25ms/16kByte)
2#0010=Check FW-CRC (approx.
100ms/16kByte)
2#0011=Check FW-CKS (approx.
25ms/16kByte)
2#11xx=reserved, Bit0: 1=CRC, 0=CKS
X 16#08
327
Cfg.Common.
CheckPRGRun
(BYTE)
CFG_Check
PRGRun
Configuring a continuous flash-ROM check of
the DcS CPU (in every cycle)
(Notation: 2#nnnnmmmm)
n = reserved; m = Mode:
2#0000=Check AWP-CRC (approx.
185s/16Byte)
2#0001=Check AWP-CKS (approx.
80s/16Byte)
2#0010=Check FW+AWP-CRC (approx.
370s/16Byte)
2#0011=Check FW+AWP-CKS (approx.
160s/16Byte)
2#0100=Check FW-CRC (approx.
185s/16Byte)
2#0101=Check FW-CKS (t approx.
8s/16Byte)
2#1xxx := reserved, Bit0: 1=CRC, 0=CKS
Special value: 16#00 = no continuous check
X 16#00
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-23
Input operand as Symbol address acc. to Desription on Default
%QW
(Word)
%QB
(Byte)
%QX
(Bit)
Data structure
Adjustable control
configuration
C
P
U
I
O
Preset
Configuration Variables for the CAN-Bus of the DcS I/O (TCANIOCFG)
164 328
Cfg.CAN.Mode
(BYTE)
CFG_CAN_
Mode
Adjustment of the CAN-protocol of the DcS
I/O (possible modes: 0=no mode, 1=MOBA,
2=Caterpillar J1939, 3=Deutz J1939)
X 2#0
329
Cfg.CAN.ModePa
r (BYTE)
CFG_CAN_
Timeout
Adjustment of the Timeout of the CAN-bus of
the DcS I/O in steps of [10ms] (0=no Timeout)
X 10#200
165 330
Cfg.CAN.Speed
(EcanSpeed)
CFG_CAN_
Speed
Adjustment of the transmission speed of the
CAN-bus of the DcS I/O in [EcanSpeed (see
Prosyd.lib)]
X
KBD_
125
331 not used
166 not used
: :
195 not used
Configuration Variables for the Control System (TSYSTEMCFG)
196 392
Cfg.Sys.maxWD
reset (WORD)
CFG_MaxWdg
Reset
Max. number of Watchdog-resets. When this
number of watchdog-resets is reached one
after the other, the AWP will be deactivated
X 10#5
197 394
Cfg.Sys.cycles
WDclear (WORD)
CFG_Cycles
ToClearWdg
Number of faultless AWP-cycles after which
the internal Watchdog-reset-counter will be
reset
X 10#500
198 396
Cfg.Sys.en_
emergency
(BYTE)
CFG_Enable
Emergency
Mask for EMERGENCY-readouts on the
CAN-bus:
16#00 = no message,
16#01 = NO_ERROR = normal message,
16#02 = WARNING = warnings,
16#04 = USER_ERROR = user error,
16#08 = APP_ERROR = application error,
16#10 = SYS_ERROR = system error,
16#1F = output of all
X 16#1F
397
Cfg.Sys.RTC_
Date_flag (BYTE)
CFG_RTC_DATE
_FLAG
Flag for updating the Date & Time variables in
SystemIn
X 2#1
199 398
Cfg.Sys.ASC0_
CharLen (BYTE)
CFG_ASC0_
CharLength
Configuring the character frame of the RS232
of the DcS CPU
(16#18 = 1 Stop bit & 8 Data bits)
X 16#18
399
Cfg.Sys.ASC0_
Parity (BYTE)
CFG_ASC0_
PARITY
Configuring the parity error detection of the
RS232 of DcS CPU
(16#00 = no parity, 16#10 = EVEN-parity,
16#20 = ODD-Parity)
X 16#00
200
Cfg.Sys.ASC0_
Baudrate
(DWORD)
CFG_ASC0_
BAUDRATE
Configuring the transmission rate of the
RS232 of DcS CPU
(possible values: 2400, 4800, 9600, 19200,
38400, 57600)
X
10#
19200
202 not used
: :
211 not used
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-24
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-25
N.8 Notes
N Table of Operands
Manual
digsy

compact
04 68 283000/A
Version 1.0.0
Page N-26

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