Centero VN220 HW Integration Application Note

VersaNode 220 Hardware Integration
Application Note
Version 1.2
Date: April 1, 2011
08-00023-01 Proprietary & Confidential – NIVIS LLC

Table of Contents
1. Introduction ................................................................................................................................... 3
1.1 Purpose and Audience................................................................................................................... 3
2. Pin-out and Interface Summary .................................................................................................... 4
3. VL10 Application .......................................................................................................................... 15
3.1 VL10 HART Modem Interface ...................................................................................................... 15
3.2 VL10 4-20 mA Input Connectivity ................................................................................................ 17
3.3 Additional VN220 Interfaces on the VL10 ................................................................................... 19
4. VS220 Application........................................................................................................................ 24
4.1 VS220 HART Modem Interface .................................................................................................... 24
4.2 VS220 4-20 mA Input Connectivity .............................................................................................. 26
4.3 VS220 Input Power Options ........................................................................................................ 28
4.4 UART1 Alternate Connectivity ..................................................................................................... 29
4.5 Additional Interfaces on the VS220 ............................................................................................. 30
5. VN220 Power Supply Considerations .......................................................................................... 37
5.1 Maximum Ratings ........................................................................................................................ 37
5.2 Normal Operating Conditions...................................................................................................... 37
6. VN220 Layout Information and Mechanical Drawings................................................................ 38
7. Appendix A. VL10 HART Loop Board Reference Schematic........................................................ 41
8. Appendix B. VS220 HART Development Board Reference Schematic ........................................ 43
9. Appendix C. Nivis HART Modem Daughter Board Reference Schematic .................................... 46
08-00023-01 VN220 Hardware Integration Application Note v.1.2 2/46

Proprietary & Confidential – NIVIS LLC
1. Introduction
1.1 Purpose and Audience
The purpose of this document is to define the VN220 radio modem’s connectivity on Nivis data
acquisition boards and to provide the necessary data to achieve hardware integration of the VN220 and
these data acquisition boards with customer application processors. The document also provides
reference design information for customers who wish to purchase the VN220 separately from the Nivis
development kit in order to develop a different application.
By definition the VN220 is a wireless modem that is pre-loaded with the Nivis WirelessHART stack.

2. Pin-out and Interface Summary
The following section presents the pin assignments of the VN220 as used on the VL10 and VS220 boards,
which are part of the Nivis HART development kit.
An external processing entity can communicate with the VN220 using a variety of methods depending
on the application. The UART1 port is used for serial firmware upload, and in some applications, it is
used to talk to the HART modem.
The VN220 is used in two applications in the Nivis HART development kit: the VL10 and the VS220. Nivis
VL10 is designed specifically for WirelessHART applications and enables customers to connect a variety
of 4-20mA devices in order to transmit temperature or other sensor data using the WirelessHART
standard to the customer’s Gateway. The VS220 is a development board designed specifically for
WirelessHART developers to enable fast product integration and development for industrial wireless
solutions.
Figure 1 shows the VN220 pin assignments. Table 1 shows the pin descriptions for the VL10 application,
and Table 2 shows the pin descriptions for the VS220 application.
Note: For minimum battery consumption, all unused GPIOs should be left unconnected.
Figure 1. VN220 Pin Assignments

Table 1. Pin Definitions for VN220
No. Name Description Type Dir Comments
Standard UART communication with flow

1 UART2-RTS UART2 Request to Send DIG I control. Connect this to UART RTS of application
processor.

2 UART2-CTS UART2 Clear to Send DIG O control. Connect this to UART CTS of application
processor.

3 UART2-RXD UART2 Receive Data DIG I control. Connect this to UART-TXD of application
processor.

4 UART2-TXD UART2 Transmit Data DIG O control. Connect this UART-RXD of application
processor.
Optional connection to firmware load interface

5 UART1-RTS UART1 Request to Send DIG I/O
or to HART Modem.
6 UART1-CTS UART1 Clear to Send DIG I/O Not used.
7 UART1-RXD UART1 Receive Data DIG I Standard UART communication.
8 UART1-TXD UART1 Transmit Data DIG O Standard UART communication.
9 I2C-SDA I2C bus DATA DIG I/O Not used.
10 I2C-SCL I2C bus CLOCK DIG I/O Not used.
Turns the HART Modem on (0) or off (1). Note

11 TMR1 Timer 1 I/O DIG O that the auxiliary HART Carrier detector is
always on.
12 TMR0 Timer 0 I/O DIG I/O Not used.
13 SPI-SCK SPI Clock DIG O Standard SPI Communication.
14 SPI-MOSI SPI Data Out DIG O Standard SPI Communication.
15 SPI-MISO SPI Data In DIG I Standard SPI Communication.
16 SPI-SS SPI Slave Select DIG O Standard SPI Communication.
17 GND Ground N/A N/A Connect to Ground pin.
18 KBI0 Keyboard interface pin 0 DIG O Controls the red STATUS LED (D1).
19 RTC-FOUT 32768Hz RTC clock out DIG O Not Used
Used for Display Status button. Holding this pin

20 KBI6 Keyboard interface pin 6 DIG I low for 1 second enables the STATUS LED for the
next 10 seconds.
21 KBI5 Keyboard interface pin 5 DIG I Power fail monitor input.

22 GND Ground N/A N/A
Wakeup input from the auxiliary HART Carrier

26 RTC-INT-B Keyboard interface pin 7 DIG I detector. Detects presence of a carrier on the
line using a very low power circuit (always on).
Boot switch input from SW5. If switch SW5 is

placed at position 1, the VN220 will see a logic
HIGH, and the ISA100 stack will be loaded. If
27 KBI1 Keyboard interface pin 1 DIG I switch SW5 is at position 2, the VN220 will see a
logic LOW, the Wireless HART stack will be
loaded, and the board will boot from Flash Area
4.
Controls output enable of USB level translator.

28 KBI2 Keyboard interface pin 2 DIG O The VN220 controls whether UART1 lines are
connected to the USB interface (Note2).
RDY_RADIO line. This signal is active low and is

used by the VN220 to indicate a ready-to-
29 KBI3 Keyboard interface pin 3 DIG O
receive state. It will be generated as a response
to the Application CPU WKU signal.
WKU_RADIO line. This signal is active high and is

used by the Application CPU to wake up the
VN220 CPU from hibernation and to signal the
30 KBI4 Keyboard interface pin 4 DIG I
intention to communicate with the modem.
Keeping this line active will block the modem
from entering the low power mode (sleep).
Modem carrier detect signal – this is a valid

32 ADC3 ADC pin 3 DIG I HART carrier detect signal from the HART
modem chip.
33 ADC2 ADC pin 2 DIG I/O Not used.
Set ADC2-VREFH to Low and ADC2-VREFL to

High and power the VN220 for a few seconds to
ADC2- erase the flash. After erasing the flash, set the
36 ADC2 reference, high pin Analog I
VREFH ADC2-VREFH to High and ADC2-VREFL to Low.
WARNING: this operation will erase the Nivis

Bootloader and all manufacturing and

non-volatile data!
ADC2-
37 ADC2 reference, low pin Analog I See the comments for ADC2-VREFH
VREFL
Connect this pin to regulated power supply VCC.

39 VCC Supply voltage N/A N/A
(+3V < Vcc <3.3V)
Reset pin of the VN220. LOW to reset and HIGH

41 RESET RESET pin DIG I
to run.
JTAG Return Clock /

42 JTAG-RTCK DIG O Standard JTAG interface
ADC pin 7
43 JTAG-TDO JTAG Test Data Output DIG O Standard JTAG interface
44 JTAG-TDI JTAG Test Data Input DIG I Standard JTAG interface
45 JTAG-TCK JTAG Test Data Input DIG I Standard JTAG interface
46 JTAG-TMS JTAG Test Mode Select DIG I Standard JTAG interface
To use the Nivis antenna connector, ensure C27

is mounted (default configuration) and pin 50 is
not used. To connect a different type of
50 RF RF pin Analog I/O antenna/antenna connector, move C27 to C29’s
position, and pin 50 is the signal for the
antenna. Note: C27 and C29 are located on the
VN220.

Table 2. Pin Definitions for VL10 Application
Digital output from the VN220 used for HART

1 UART2-RTS UART2 Request to Send DIG O Modem UART communication. 1-Modem
receive, 0-Modem transmit (Note1).
2 UART2-CTS UART2 Clear to Send DIG I/O Not Used (Note1).
Digital data output of the HART modem’s

3 UART2-RXD UART2 Receive Data DIG I demodulator and an input to the VN220’s
UART2 RX line (Note1).
Digital data input to the HART modem’s

4 UART2-TXD UART2 Transmit Data DIG O modulator and an output from the VN220’s
UART2 TX line (Note1).

5 UART1-RTS UART1 Request to Send DIG I
control.

6 UART1-CTS UART1 Clear to Send DIG O
control.
Standard UART communication. Used for

upgrading the firmware of the VN220. TTL<->
7 UART1-RXD UART1 Receive Data DIG I
RS232 level shifters should be employed when
connecting to RS232 port.
Standard UART communication. Used for

upgrading the firmware of the VN220. TTL<->
8 UART1-TXD UART1 Transmit Data DIG O
RS232 level shifters should be employed when
connecting to RS232 port.
9 I2C-SDA I2C bus DATA DIG I/O Communicates with A-D Converter.
10 I2C-SCL I2C bus CLOCK DIG I/O Communicates with A-D Converter.
11 TMR1 Timer 1 I/O DIG I/O Not used.
12 TMR0 Timer 0 I/O DIG I/O Not Used
13 SPI-SCK SPI Clock DIG I/O Not Used.
14 SPI-MOSI SPI Data Out DIG I/O Not Used
15 SPI-MISO SPI Data In DIG I/O Not Used
16 SPI-SS SPI Slave Select DIG I/O Not Used

18 KBI0 Keyboard interface pin 0 DIG O that the auxiliary HART Carrier detector is
always on.


next 10 seconds.
RTC wake-up interrupt /

26 RTC-INT-B DIG I Not Used
Keyboard interface pin 7
27 KBI1 Keyboard interface pin 1 DIG O Not Used

30 KBI4 Keyboard interface pin 4 DIG I detector. Detects presence of a carrier on the
32 ADC3 ADC pin 3 DIG I Not Used
Used for power conservation – when in logical 0

33 ADC2 ADC pin 2 DIG O turns off the 2.5V reference and the amplifier
for the A-D converter.
34 ADC1 ADC pin 1 DIG O Controls STATUS LED.

modem chip.

erase the flash. After erasing the flash, set the
ADC2- ADC2-VREFH to High and ADC2-VREFL to Low.
VREFH
non-volatile data!
ADC2-
37 ADC2 reference, low pin Analog I See the comments for ADC2-VREFH.
VREFL
39 VCC Supply voltage N/A N/A Connect this pin to regulated power supply VCC.

(+3V < Vcc <3.3V)

to run.
JTAG Return Clock /

42 JTAG-RTCK DIG O Standard JTAG interface.
ADC pin 7

VN220.
Note 1: For the VL10 application, the VN220 UART2 control lines are not compatible with the Nivis
Standard API and are used as GPIO lines to communicate with the HART Modem interface board.

Table 3. Pin Definitions for VS220 Application

control. Supports communication using the Nivis
1 UART2-RTS UART2 Request to Send DIG I
Simple API. Connect this to UART RTS of the
application processor.

control. Supports communication using the Nivis
2 UART2-CTS UART2 Clear to Send DIG O
Simple API. Connect this to UART CTS of the
application processor.

control. Connect this to UART-TXD of application
3 UART2-RXD UART2 Receive Data DIG I
processor. Supports communication using the
Nivis Simple API.

control. Connect this UART-RXD of application
4 UART2-TXD UART2 Transmit Data DIG O
processor. Supports communication using the
Nivis Simple API.
Optional connection to firmware load interface

5 UART1-RTS UART1 Request to Send DIG I/O
(USB or J14), or to HART Modem (Note2).
6 UART1-CTS UART1 Clear to Send DIG O Temp/Humidity Sensor interface (CLK out).
7 UART1-RXD UART1 Receive Data DIG I Standard UART communication (Note 2).
8 UART1-TXD UART1 Transmit Data DIG O Standard UART communication (Note 2).
Communicates with external A-D Converter

9 I2C-SDA I2C bus DATA DIG I/O
(Data I/O).
Communicates with external A-D Converter

10 I2C-SCL I2C bus CLOCK DIG O
(Clk out).

11 TMR1 Timer 1 I/O DIG O that the auxiliary HART Carrier detector is
always on.

12 TMR0 Timer 0 I/O DIG O turns off the 2.5V reference and the amplifier
for the A-D converter.
Connects to standard 10 pin header for SPI

13 SPI-SCK SPI Clock DIG O
communication using Nivis API.

14 SPI-MOSI SPI Data Out DIG O

15 SPI-MISO SPI Data In DIG I
16 SPI-SS SPI Slave Select DIG O Connects to standard 10 pin header for SPI

18 KBI0 Keyboard interface pin 0 DIG O Controls the red STATUS LED (D1).

next 10 seconds.

26 RTC-INT-B Keyboard interface pin 7 DIG I detector. Detects presence of a carrier on the
Boot switch input from SW5. If switch SW5 is

placed at position 1, the VN220 will see a logic
HIGH, and the ISA100 stack will be loaded. If
27 KBI1 Keyboard interface pin 1 DIG I switch SW5 is at position 2, the VN220 will see a
logic LOW, the Wireless HART stack will be
loaded, and the board will boot from Flash Area
4.
Controls output enable of USB level translator.

28 KBI2 Keyboard interface pin 2 DIG O The VN220 controls whether UART1 lines are
connected to the USB interface (Note2).
RDY_RADIO line. This signal is active low and is

used by the VN220 to indicate a ready-to-
29 KBI3 Keyboard interface pin 3 DIG O
receive state. It will be generated as a response
to the Application CPU WKU signal.
WKU_RADIO line. This signal is active high and is

used by the Application CPU to wake up the
VN220 CPU from hibernation and to signal the
30 KBI4 Keyboard interface pin 4 DIG I
intention to communicate with the modem.
Keeping this line active will block the modem
from entering the low power mode (sleep).

modem chip.


33 ADC2 ADC pin 2 DIG O
turns off the Temp/Humidity sensor.
34 ADC1 ADC pin 1 DIG O Controls the green D3 LED.
35 ADC0 ADC pin 0 DIG I/O Temp/Humidity Sensor interface (Data I/O).

erase the flash. After erasing the flash, set the
ADC2- ADC2-VREFH to High and ADC2-VREFL to Low.
VREFH
non-volatile data!
ADC2-
37 ADC2 reference, low pin Analog I See the comments for ADC2-VREFH
VREFL
Connect this pin to regulated power supply VCC.

39 VCC Supply voltage N/A N/A
(+3V < Vcc <3.3V)

to run.
JTAG Return Clock /

42 JTAG-RTCK DIG O Standard JTAG interface
ADC pin 7

VN220.

Note 2: On the VS220 board, the WirelessHART stack normally uses UART1 to communicate with the
HART Modem (KBI2 is automatically set to 0, and J12, J16, J17, J18, J19 and J20 jumpers must be
populated (the RTS signal communicates the direction of dataflow to the HART Modem). Occasionally
the user can decide to make a serial firmware loading through USB or J14 connector, using the dedicated
Nivis PC application. For serial firmware loading through the USB interface or through J14, first populate
only the following jumpers: J10, J12 and J21 before powering on the board. During boot and firmware
loading, KBI2 is automatically set to 1, while RTS is not used. If connector J14 is used instead of USB port
for firmware loading, TTL <-> RS232 level shifters must be employed when connecting to the PC’s RS232
port.

3. VL10 Application
The Nivis VL10 is designed specifically for WirelessHART applications and enables customers to connect
a variety of 4-20mA devices in order to read and transmit temperature or other sensor data using the
WirelessHART standard to the user’s Gateway. The Nivis VL10 has several interfaces that are useful to
the user.
The Nivis VL10 uses the VN220 radio, which contains an MC13224 processor running a Nivis certifiable
WirelessHART stack. It also includes a HART Maintenance Port (FSK interface) on the HART Modem
daughter card.
3.1 VL10 HART Modem Interface
The WirelessHART stack residing on the VN220 radio only supports the FSK interface (HART Modem) as a
Maintenance Port as described by the WirelessHART specification from the HART foundation.
The Maintenance Port impedance is 500 Ohm and normally it is not coupled with the VL10 4-20 mA
analog input. It is designated only for device configuration, and it does not support Burst Mode.
The HART Configuration Tool (or Handheld device) is connected to the Maintenance Port at TR1 and TR2
pins. In the default configuration, they are isolated from the board’s ground, so their polarity does not
matter.
The HART Modem interface resides on connector J1 on the VL10. The VL10 comes pre-populated with a
Nivis HART Modem interface board connected at J1.
The VN220 radio communicates with the HART Modem using the UART2 interface (CTS line is not used),
and the GPIO lines described in this section. The VL10 was designed for a maximum compatibility with
the HART Modem daughter board, which contains a HART certifiable modem IC, part number
DS8500-JND+.
In order to save power, the HART Modem circuit is turned on by the VN220 only when a carrier signal is
first detected by an auxiliary low-power carrier detector circuit also located on the Modem daughter
board. The HART Modem is turned back off only after the master’s request (STX) packet is received and
the slave response (ACK) packet is transmitted.
The GPIO handshaking and data transfer between the VN220 and the HART modem daughter board
connector on the VL10 is shown in Figure 2.

Auxiliary Carrier Detect
30 9
Modem OCD
35 11
UART2 RX Data Out
3 15
UART2 TX Data In
4 17
UART2 RTS RTS
1 21
MODEM ON
18 23
VN220 HART MODEM CONNECTOR
Figure 2. Modem Interface GPIO for VL10
The Auxiliary Carrier Detect line is an external interrupt input to the VN220. This signal becomes HIGH
when the auxiliary low-power carrier detector located on the HART Modem daughter board detects a
carrier on the line. This circuit is always powered, even when the HART Modem is switched off, and it is
only used to wake-up the VN220 from the sleep mode and/or to request the modem’s power control to
be switched on by the VN220.
Modem On is an output from the VN220 that turns on the power supply for the HART modem chip.
A LOW on this line will turn on the modem, and a HIGH will turn off the modem. The modem will be
turned on, to stay on reception mode, when the Auxiliary Carrier Detect line first indicates that there is a
carrier on the line.
The Modem OCD line is an input to the VN220 and is connected to the CD digital output of the HART
modem IC. This signal is used by the software to monitor the carrier presence during the reception of a
packet. Logic HIGH indicates a valid carrier detection.
The Data Out / UART2 RX line is the digital data output of the HART modem’s demodulator and an input
to the VN220’s UART2 RX line.
The Data In / UART2 TX line is the digital data input to the HART modem’s modulator and an output
from the VN220’s UART2 TX line.
The RTS line is a digital input to the modem from the VN220. When set high, the modem is put into the
demodulator mode. A logic-low puts the modem into modulator mode.

3.2 VL10 4-20 mA Input Connectivity
The VL10 acts as a WirelessHART sensor (transmitter) field device. The analog 4-20 mA input on VL10 is
identified with its Primary Variable, which can be transmitted wirelessly, but it does not support the
standard HART current loop output (the VL10 accepts analog data from a non-HART 4-20 mA transmitter
device through its analog input, however it does not have an analog output configuration to transmit
the measured data value by analog signaling).
On the VL10, the HART Maintenance Port (FSK interface) is separate from the 4-20 mA analog input.
The field device can access the maintenance port on the VL10 on ports TR1 and TR2. Normally they are
isolated from the board’s ground, so their polarity does not matter.
To connect the 4-20 mA loop to the VL10 analog input, connect the positive side to TB1, and the
negative side to TB2. Also populate J11, and depopulate J5 and J6. Refer to Figures 3, 4, and to the HART
Loop board schematic in Appendix A for more information.
Note: To introduce minimal error rate in the loop current measurement, ensure that the ground from the
power source is isolated from the VL10 ground. Using a power source with non-isolated ground can
cause a significant measuring error at the differential amplifier input.
As an option, the Maintenance Port can be physically connected to the 4-20mA input circuit via
populating jumpers J5, J6 and depopulating J11. Be aware that this will introduce a 500 Ohm resistor in
series with the current loop. Figure 3 shows this connectivity on the VL10 board’s side, and Figure 4
shows the circuitry involved on the Modem Daughter Board side.

TB1
1
1
2
2
1727010
TR1
1249
1
1 J5
MODEM_OUT+ 1 2
90120-0122
2
J11
TR2
90120-0122
1249
1
1
J6
1
MODEM_OUT- 1 2
90120-0122
Current Sense Resistors R6 R7 To A-D Converter

10 10
TB2
1
1
2
2
1727010
Figure 3. HART Modem Connectivity on VL10
MODEM_OUT+ To VL10
R23 C24
From Op Amp U7 1 T2 4 R24
of modem daughter board
499
10 2.2uF JP2
3 6
TMM-102-01-T-S
TY -307P
MODEM_OUT- To VL10
Figure 4. HART Modem Connectivity on Modem Daughter Card

3.3 Additional VN220 Interfaces on the VL10
For more information on the interfaces described in this section, refer to the VL10 schematic in
Appendix A.
UART1
The VN220’s UART1 lines are connected to J3 on the VL10. This connector is used for firmware loading.
WARNING: Avoid connecting J3 Pin3 to GND or to another power source (e.g. 5V).
I2C
The VN220’s I2C interface communicates with the A/D converter on the VL10 board. The A/D converter
is used to read the current value from the 4-20mA input. Between the measurements it can be shut
down via the i2C interface to conserve power.
3V 3V
R4 R5 TP14 TP15
5
3
Current monitor input 2K 2K

2 4
A1
A0
AIN GND
7
SCL I2C_SCL sheet2
6
SDA I2C_SDA sheet2
1 8
VREF VDD 3V NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND
From 2.5 voltage reference
U3
ADS7823E
C7
1uF
Figure 5. A-D Converter Interface on VL10

Display Status Switch
The VN220 reads in pushbutton switch SW3 at KBI_6, pin 20. SW3 is the Display Status button. Holding
this pin low for 1 second enables the status LED for the next 10 seconds.
3V
R20
TP11 100K
to KBI_6
(Pin 20 of VN220)
1
C18 SW3
EVQ-PAC07K
0.1uF
2
Figure 6. Display Status Pushbutton on VL10
Power Fail Monitor

The VN220 reads in an active low power fail monitor input at KBI_5, pin 21. Also, the RESETn line asserts
(low) whenever VCC drops below the selected reset threshold voltage, which is 2.7V.
3V 3V
R8
590K
U4 R10
C8 4.7K
1 8 0.1uF
RESET_IN VCC
R13
499K 4 7
GND RESETn KBI_5 sheet2
6 To Pin 21 of VN220
WDI
3
2 SRT 5
SWT WDS
C15
MAX6749KAT
1500pF
Figure 7. Power Fail Monitoring on VL10

RED Status LED
The VN220 controls a red status LED at VN220 pin 34. The functionality of this LED is described in the
following table:
Table 1. VL10 Status LED
JOIN status LED (red) State Behavior

Device in discovery mode LED blinking with a low refresh
rate. At power-up until the
network is detected.
Device joining the network LED blinking rapidly.
Advertisement has been received
and join request will be or has
been sent. Device in the process
of joining.
Joined LED on continuously. The device
has joined the network
(Operational).
GPIO4
sheet2
From pin 22 of VN220
TP1
D1 LS M67K-H2L1-1-0-2-R18-Z
RED
R18
750
Figure 8. Status LED on VL10

Current Monitoring Control
The VN220 can turn on/off the 2.5 Voltage reference and the analog input amplifier on the VL10 by
asserting / de-asserting pin 33. De-asserting this line will turn off the board’s ability to measure the
4-20mA current loop. This switched voltage is used for power saving on the VL10.
5V
R25 C21
100K 0.1uF
2
S
G
1
D Q3
SI1305DL
3
3
D
5V_SW
G
sheet2 GPIO5 1
S Q2
From Pin 33 of VN220 SI1300BDL
2
R24
1M
Figure 9. Power Saving Circuit on VL10
FLASH Erase
The VN220 provides a way to erase the VN220 micro controller’s internal FLASH via pins 36 and 37
(ADC_VREFH and ADC_VREFL respectively). Set ADC2-VREFH to Low and ADC2-VREFL to High and power
the VN220 for a few seconds to erase the flash. After erasing the flash, set the ADC2-VREFH to High and
ADC2-VREFL to Low.
WARNING: This operation will erase the Nivis Bootloader and all manufacturing and non-volatile data!
The VN220 will no longer be operational, until a software re-manufacturing procedure is performed.

JTAG
The VL10 board provides a standard 20 pin JTAG interface to update the processor code residing on the
VN220. The connector designator is J2 and connects JTAG lines going to pins 42 – 46 of the VN220.
See the table below for the JTAG pin-out.
Table 2. VL10 JTAG Pin-out
JTAG Function VN220 Pin Number J2 Pin Number
RESET 41 15
RTCK 42 11
TDO 43 13
TDI 44 5
TCK 45 9
TMS 46 7
RESET Switch
The VL10 supports a reset switch at SW1. This switch is used to reset the VN220 stack modem.

4. VS220 Application
The VS220 sensor node fulfills the Wireless HART field device logical role in the WirelessHART network.
The Nivis VS220 offers a complete integration platform for users who intend to WirelessHART enable
their instruments. This is accomplished by exposing various hardware ports of the stack modem through
which the user can interface an application processor.
The Nivis VS220 uses the VN220 radio, which contains an MC13224 processor running a Nivis certifiable
Wireless HART stack. It also includes a HART Maintenance Port (FSK interface) on the HART Modem
daughter card.
4.1 VS220 HART Modem Interface
The VS220 board supports the FSK interface (HART Modem) as a Maintenance Port as described by
WirelessHART specification. The Maintenance Port impedance is 500 Ohms and normally it is not
coupled with the VS220 4-20 mA analog input. It is designated only for device configuration, and it does
not support Burst Mode.
The HART Modem interface board resides on connector J6 on the VS220. The VS220 comes
pre-populated with a Nivis HART Modem interface board connected at J6.
The VN220 radio communicates with the HART Modem using the UART1 interface (CTS line is not used),
and the other GPIO lines described below. Actually UART1 is used for multiple applications on the
VS220. Appropriate jumper settings described in this document and shown on the VS220 schematic in
Appendix B of this document, need to be implemented for the UART1 pins to connect to the HART
modem. The VS220 was designed for a maximum compatibility with the HART Modem daughter board,
which contains a HART certified modem IC, part number DS8500-JND+.
In order to save power, the HART Modem circuit is turned on by the VN220 only when a carrier signal is
first detected by an auxiliary low-power carrier detector circuit also located on the Modem daughter
board. The HART Modem will be turned back off only after the master’s request (STX) packet was
received and the slave response (ACK) packet was transmitted.
The GPIO handshaking and data transfer between the VN220 and the HART modem daughter board
connector on the VS220 is shown in Figure 10.

Auxiliary Carrier Detect
26 9
Modem OCD
32 11
UART1 RX Data Out
7 15
UART1 TX Data In
8 17
UART1 RTS RTS
5 21
MODEM ON
11 23
VN220 HART MODEM CONNECTOR
Figure 10. Modem Interface GPIO for VS220
The Auxiliary Carrier Detect line is an external interrupt input to the VN220. This signal becomes HIGH
when the auxiliary low-power carrier detector located on the HART Modem board detects the presence
of a carrier on the line. This circuit is always powered, even when the HART Modem is switched off, and
it is only used to wake-up the VN220 from the sleep mode and/or to request the modem’s power
control to be switched on by the VN220.
Modem On is an output from the VN220 that turns on the power supply for the HART modem chip.
A LOW on this line will turn on the modem, and a HIGH will turn off the modem. The modem will be
turned on, to stay on reception mode, when the Auxiliary Carrier Detect line first indicates that there is a
carrier on the line.
The Modem OCD line is an input to the VN220 and is connected to the CD digital output of the HART
modem chip. This signal is the one used by the software to monitoring the carrier presence during the
reception of a packet. A logic HIGH indicates a valid carrier detection.
The Data Out / UART1 RX line is the digital data output of the HART modem’s demodulator and an input
to the VN220’s UART1 RX line.
The Data In / UART1 TX line is the digital data input to the HART modem’s modulator and an output
from the VN220’s UART1 TX line.
The RTS line is a digital input to the modem from the VN220. When set high, the HART modem is put
into the demodulator mode. A logic-low puts the HART modem into modulator mode.

4.2 VS220 4-20 mA Input Connectivity
The VS220 acts as a WirelessHART sensor (transmitter) field device. The analog 4-20 mA input on the
VS220 is identified with its Primary Variable, which can be transmitted wirelessly, but it does not
support the standard HART current loop output (the VS220 accepts analog data from a non-HART 4-20
mA transmitter device through its analog input, however it does not have an analog output
configuration to transmit the measured data value by analog signaling).
On the VS220 board, the HART Maintenance Port (FSK interface) is separate from the 4-20 mA analog
input. The field device can access the maintenance port on TR1 and TR2, and normally they are isolated
from the board’s ground, so their polarity does not matter.
To connect the 4-20 mA loop to the VS220 analog input, connect the positive side to TB1, and the
negative side to TB2. Also populate J22, and depopulate J7 and J8. Refer to Figure 11 and to the HART
Development Board Schematic in Appendix B for more information.
As an option, the Maintenance Port can be physically connected to the 4-20mA input circuit via
populating jumpers J7, J8 and depopulating J22. Be aware that this will introduce a 500 Ohm resistor in
series with the current loop. Figure 11 shows the connectivity on the VS220 board, and Figure 4 shows
the circuitry on the Modem Daughter Board side.

TB1
1
1
2
2
1727010
TR1
1249
1
J7
1
MODEM_OUT+ 2 1
90120-0122
1
J22
TR2
90120-0122
1249
1
2
J8
1
MODEM_OUT- 2 1
90120-0122
R12 R13
Current sense resistors 10 10
TB2
1
1
2
2
1727010
Figure 11. HART Modem Connectivity on VS220

4.3 VS220 Input Power Options
The VS220 has the ability to have input power applied to the board via three methods described in this
section.
WARNING: FAILURE TO COMPLY WITH THE STEPS IN SECTION 4.3 FOR EACH POWER METHOD MAY
RESULT IN THE BOARD BEING DAMAGED. SPECIAL CARE MUST BE TAKEN TO COMPLY WITH EACH STEP
BELOW BEFORE APPLYING APPROPRIATE POWER TO THE BOARD.
1. External input power via TB3 connection. The external power supply’s input range is 7 to 16
volts DC. For external input power, the following steps need to be performed or verified before
applying power:
1. SW4 needs to be at switch position 1.
2. R14 needs to be de-populated (default board configuration)
3. R15 and R16 needs to be populated (default configuration).
2. Battery power via the battery holder BT1. For maximum battery life, battery power is supplied
by four 3.6V cell Lithium AA batteries. As an alternative, four 1.5V Alkaline AA batteries can be
used for approximately 3 to 8 days of battery life. For battery power, the following steps need to
be performed or verified before applying power:
a. SW4 needs to be at switch position 2.
b. R14 needs to be de-populated (default board configuration).
c. R15 and R16 needs to be populated (default configuration).
3. USB 5V power. For external USB 5V power, the following steps need to be performed or verified
before applying power:
a. SW4 needs to be at switch position 3.
b. R14 (zero Ohm resistor) needs to be populated.
c. R15 and R16 need to be de-populated.
d. A USB cable needs to be connected at J11.
Note: It is not necessary to apply board power via USB in order to update the
firmware via USB. If USB communication is necessary, the VS220 can still
communicate over the USB cable while in input power option 1 or 2 (battery or
external supply). Option 3 is not recommended by Nivis and must only be used if the
board requires 5V power from the USB cable and cannot be powered via the external
supply or battery option.

POWER_IN V_BATT VDD_5V_USB
SW4
VIN
1
4 2
Power Input Switch

Silkscreen: Position 1 = External Power
Position 2 = Battery Power
Position 3 = USB Power
Figure 12. Power Input Switch on VS220
4.4 UART1 Alternate Connectivity

The following instructions describe how UART1 should be configured for its three possible
configurations (VN220 UART1 to/from USB converter, VN220 UART1 to/from HART modem, and VN220
UART1 to/from external connector). For more information, refer to sheet 3 of the HART Development
Board Schematic in Appendix B.
VN220 UART1 to/from HART modem:
The configuration below should be used when the VN220 communicates with the HART modem. This is
the default configuration for the VS220 board used as a WirelessHART device, since it must have a HART
(FSK) Maintenance Port available.
1. Make sure jumpers J10 and J21 are disconnected.
2. Connect jumpers J12, and J16-20.
3. KBI2, pin 28 of the VN220 must be held LOW. This is automatically done by the WirelessHART
firmware after the boot process is finished.
4. Apply the power or press the RESET button on the VS220 board.
VN220 UART1 to/from USB:

The configuration below should be used only when the user wishes to communicate to the VN220 via
USB. The typical application is when perform a firmware upgrade, using the dedicated Nivis PC serial
loader program and a USB cable.
1. Make sure jumpers J16-J20 are disconnected.
2. Connect jumpers J10, J12, and J21.
3. KBI2, pin 28 of the VN220 must be held HIGH. This is automatically done by the WirelessHART
firmware during the boot process, when the communication with the dedicated Nivis PC serial
loader program is established.

VN220 UART1 to J14 connector:
The configuration below can be used to load firmware via UART1, as an alternative to the USB interface.
1. Disconnect all jumpers (J10, J12, J16-21) and connect a UART cable to J14. TTL<-> RS232 level
shifters must be employed when connecting to the PC’s RS232 port.
4.5 Additional Interfaces on the VS220

For more information on the interfaces described in this section, refer to the VS220 schematic in
Appendix B.
UART2
The VS220 provides a standard UART interface at the VN220’s UART2 port for communication using the
Nivis standard API. The connector for UART2 is J2. See below for the UART2 connector pin-out.
J2
UART2_TX 1 2 UART2_RTS
UART2_RX 3 4 UART2_CTS
WKU_RADIO 5 6 RDY _RADIO
7 8
9 10
5103309-1
TP48 TP49
Figure 13. UART2 Interface on VS220
SPI
The VS220 provides a standard SPI interface at the VN220’s SPI port for communication using the Nivis
standard API. The connector for SPI is J2. See below for the SPI connector pin-out.
J3
SPI_MOSI 1 2 SPI_CLK
SPI_MISO 3 4 SPI_SS
WKU_RADIO 5 6 RDY _RADIO
7 8
9 10
5103309-1
TP41 TP42 TP43 TP44
Figure 14. SPI Interface on VS220

Temperature/Humidity Sensor Interface
The VS220 supports a 2 wire (two GPIOs) interface from the VN220 to an on-board
temperature/humidity sensor, which is located at U13. See below for a description of the interface.
Table 3. Temperature/Humidity Sensor Connections
Temperature Sensor Pin Name Function VN220 GPIO Pin
1 GND Ground --
2 DATA Serial Data, bidirectional 35
3 SCK Serial Clock, controlled by VN220 6
4 VDD Source Voltage **
** VDD is turned on/off by VN220 pin 33.
+3.0V
TP13
3 2
Q1
BSS84LT1G R6
1
470K
3
R7 TP14
10K
U13 From pin 33 of VN220
4 5 1
Pin 6 of VN220 TEMP_HUM_1 3 4 5 6 Q2
Pin 35 of VN220 TEMP_HUM_2 2 3 6 7 BSS138LT1G R8
2 7
2
1 8 470K
C3 1 8
R9 SHT15
10K 0.1uF
Figure 15. Temperature / Humidity Interface on VS220

I2C
The VN220’s I2C interface communicates with the A/D converter on the VS220 board. The A/D converter
is used to read the current value from the 4-20mA input. Between the measurements it can be shut
down via the i2C interface to conserve power.
+3.0V +3.0V
R33 R34
5
3
From current sense amplifier 4.7K 4.7K
2 A1 4
A0
AIN GND
7
SCL I2C_SCL sheet1
6
SDA I2C_SDA sheet1
2.5V REF
1 8 NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND
VREF VDD +3.0V
U5
ADS7823E
C9
1uF
Figure 16. A-D Converter Interface on VS220
Display Status Switch

The VN220 reads in pushbutton switch SW3 at KBI_6, pin 20. SW3 is the Display Status button. Holding
this pin low for 1 second enables the STATUS LED for the next 10 seconds.
+3.0V
R5
100K
TP12
1
To KBI6 (pin 20 of VN220)

SW3
C2 EVQ-PAC07K
0.1uF
2
Figure 17. Display Status Pushbutton on VS220

Power Fail Monitor
The VN220 reads in an active low power fail monitor input at KBI_5, pin 21. Also the RESETn line asserts
(low) whenever VCC drops below the selected reset threshold voltage, which is 2.7V.
+3.0V +3.0V
R23
590K
U9 R25
C20 4.7K
1 8 0.1uF
RESET_IN VCC
R28
499K 4 7
GND RESETn KBY _5 sheet1
6 To pin 21 of VN220
WDI
3
2 SRT 5
SWT WDS
C24
MAX6749KAT
1500pF
Figure 18. Power Fail Monitoring on VS220
Red Status LED

The VN220 controls a red status LED, D1, at VN220 pin 18. The functionality of this LED is described in
the following table:
Table 4. Status LED on VS220
JOIN status LED (red) State Behavior

Device in discovery mode LED blinking with a low refresh
rate. At power-up until the
network is detected.
Device joining the network LED blinking rapidly. Advertisement
has been received and join request
will be or has been sent. Device in
the process of joining.
Joined LED on continuously. The device
has joined the network
(Operational).

TP7
D1
RED
R2
750
LS M67K-H2L1-1-0-2-R18-Z
Figure 19. Status LED on VS220
Green LED
The VN220 controls a green LED, D3, at VN220 pin 34. The functionality of this LED is described in the
following table:
Table 5. Green LED on VS220
COMM LED (green) State Behavior

Communicating with the APP processor LED on continuously. Device
is communicating with the
APP processor in a stable
manner.
Establishing communication LED blinking rapidly. VS220
has detected
communication attempts on
the communication port but
is not yet consistently
communicating with the
external APP processor.

TP9
D3
GREEN
R3
750
LG M67K-G1J2-24-0-2-R18-Z
Figure 20. Green LED on VS220
Current Monitoring Control

The VN220 can turn on/off the 2.5 voltage reference and the analog input amplifier on the VS220 by
asserting / de-asserting pin 12. De-asserting this line will turn off the board’s ability to measure the
4-20mA current loop. This switched voltage is used for power saving on the VS220.
+5.0V
R35 C27
100K 0.1uF
2
G
1
D Q4
SI1305DL
3
3
D
5V_SW
G
sheet1 5V_SW_CTRL 1
S Q3
From pin 12 of VN220 SI1300BDL
2
R32
1M
Figure 21. Power Saving Circuit on VS220

Boot Switch
The VN220 supports dual boot for Wireless HART and ISA100 stacks based on the input at pin 27 of the
VN220. If switch SW5 is placed at position 1, the VN220 will see a logic HIGH, and the ISA100 stack will
be loaded. If switch SW5 is at position 2, the VN220 will see a logic LOW, and the Wireless HART stack
will be loaded. Switch position 3 is currently not being used.
FLASH Erase
The VN220 provides a way to erase the VN220’s micro controller FLASH via pins 36 and 37 (ADC_VREFH
and ADC_VREFL respectively). Set ADC2-VREFH to Low and ADC2-VREFL to High and power the VN220
for a few seconds to erase the flash. After erasing the flash, set the ADC2-VREFH to High and
ADC2-VREFL to Low.
WARNING: This operation will erase the Nivis Bootloader and all manufacturing and non-volatile data!
The VN220 will no longer be operational, until a software re-manufacturing procedure is performed.
JTAG
The VS220 board provides a standard 20 pin JTAG interface to update the processor code residing on the
VN220. The connector designator is J1 and connects JTAG lines going to pins 42 – 46 of the VN220.
See the table below for the JTAG pin-out.
Table 6. VS220 JTAG Pin-out
JTAG Function VN220 Pin Number J2 Pin Number
RESET 41 15
RTCK 42 11
TDO 43 13
TDI 44 5
TCK 45 9
TMS 46 7
RESET Switch
The VS220 supports a reset switch at SW1. This switch is used to reset the VN220 stack modem.

5. VN220 Power Supply Considerations
5.1 Maximum Ratings

Table 7. VN220 Maximum Ratings
Parameter Min Typ Max Units Comment
Supply Voltage -0.3 3.0 3.3 V
Voltage on any digital I/O -0.3 Vcc Vcc + 0.2 V
5.2 Normal Operating Conditions

Table 8. Electrical Characteristics
Parameter Min Typ Max Units Comments
Supply voltage 2.7 3.3 V
Voltage on analog pins 0 Vcc V
Voltage supply noise 200 mVpp 50Hz – 15MHz
Peak current 60 mA TX mode, maximum output

power
Storage and operating -40 +85 °C

temperature
Operating relative humidity 10 90 %RH Non condensing
Transmit current 60 mA
Receive current 21 27 mA
Hibernate current 15 µA
For additional information please consult the VersaNode 220 datasheet (document entitled
93-00017-01_Nivis_VersaNode_220_Datasheet)

6. VN220 Layout Information and Mechanical Drawings
Figure 22. Recommended layout footprint. Primary dimensions are in inches.

Dimensions in [mm] are in millimeters.

Figure 23. Outline dimension drawing. Primary dimensions are in inches.

Figure 24. Detailed outline dimension drawing. Primary dimensions are in inches.

7. Appendix A. VL10 HART Loop Board Reference Schematic
NOTE: THIS CONNECTOR USED IN SOCKET CONFIGURATION

TP21 TP23
J1
1 2 5V
1 2
3 4
3 4
5 6 NOTE: LABEL "MAX CURRENT ON LOOP = 200 mA"
5 6 NOTE: LABEL "LOOP CURRENT +" ON SILKSCREEN
7 8 R25 C21
7 8 TB1 100K 0.1uF
2
9 10
sheet2 MODEM_KBI_CD 9 10 1 S
11 12 1
sheet2 MODEM_OCD 11 12 G
2 1
13 14 2 D Q3
13 14 SI1305DL
3
3
15 16 1727010
sheet2 MODEM_DOUT_UART2_RX 15 16 D
17 18 5V_SW
sheet2 MODEM_DIN_UART2_TX 17 18 G
sheet2 GPIO5 1
19 20 TR1 S Q2
19 20 1249 SI1300BDL
2
sheet2 MODEM_UART2_RTS 21 22 R24
21 22 TP12 TP13
1
1M
23 24 J5 5V_SW U1 2.5V
sheet2 MODEM_ON 23 24
1
1 6
25 26 2 NC1 NC3 5
25 26 MODEM_OUT+ 1 2 3 GND NC2 4
5V 27 28 VIN VOUT
27 28 90120-0122 C2 ADR121AUJZ C3 C4
29 30 0.1uF 0.1uF 0.01uF
29 30 NOTE: LABEL "MODEM OUT +" ON SILKSCREEN
2
31 32
31 32 J11
33 34 TR2
33 34 90120-0122
1249
35 36
35 36 +3.0V
1
CATHODE
37 38 J6
37 38
1
3V 3V
39 40
39 40 MODEM_OUT- 1 2 C29
LSS-120-01-L-DV-A-TR-S 90120-0122 0.1uF D5

SMS3922-079LF
NOTE: LABEL "MODEM OUT -" ON SILKSCREEN R4 R5 TP14 TP15
5
3
HART Modem Board Connector 2K 2K
ANODE
R6 R7 2 4
A1
A0
R37 AIN GND
10 10
7
U12 SCL I2C_SCL sheet2
1 8 5V_SW 100 6
-IN +IN SDA I2C_SDA sheet2
C28
TB2 2 7 0.1uF 1 8
GND VREF_1 R22 VREF VDD 3V
1 3 6
1 VREF_2 V+ U3
2 4 5 24.9 ADS7823E
2 NC OUT C7
AD8210YRZ NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND 1uF
1727010 C19 C20
1uF 0.1uF
NOTE: LABEL "MAX CURRENT ON LOOP = 200 mA"
NOTE: LABEL "LOOP CURRENT -" ON SILKSCREEN
3V 3V
5V 3V
R8
590K
R9 U4
L1 R11 R10
C8 4.7K
0.22uF 1 8 0.1uF
ELL-6SH220M 0-DNP 4.99 ohm RESET_IN VCC
TB3 C9 U6
U5 R13
D2 R12
1 3 7 2 499K 4 7
1 VIN BOOST R14 Vout GND RESETn KBI_5 sheet2
0
2 SS15-TP 2 6 3 C10 C12 + C11 6
2 C13 9 EN SW 8 Vin 1 1uF 1uF WDI
PG BD 0 GND 1000uF 3
1727010 2.2uF 10 1 C14 2 SRT 5
RT FB 22pF R15 SWT WDS
4 5 1M MCP1702T3002E/CB C15
R16 GND1 GND2 MAX6749KAT
226K LT3970EMS C16 1500pF
22uF
R17
316K
Power Fail Monitor
GPIO4
sheet2
TP1
Power D1 LS M67K-H2L1-1-0-2-R18-Z
RED
R18 APPROVALS DATE

750
DRAWN BY NIVIS LLC Atlanta, GA
DESIGNED BY
Atlanta, Georgia 30339
Phone: (678) 202-6800
Status LED ENGINEER
Fax: (678)0202-6820
QUALITY
WIRELESS HART LOOP BOARD SCHEMATIC

CONFIDENTIAL OPERATIONS
PROPRIETARY INFORMATION NOT TO BE

Size DWG NO Rev
DISCLOSED OR COPIED IN ANY FORM
WITHOUT WRITTEN PERMISSION FROM

C 41-00011-01 3
NIVIS LLC, Atlanta GA Sunday, July 25, 2010 Scale Sheet 1 OF 2
Figure 25. VL10 HART Loop Board Reference Schematic, Sheet 1

42/46
RESET
TP2
TMS
VN220 Radio Module 3V
TCK
U11
TP5 TP4 TP3 51
GND 50 J2
RF 49
GND TDI 1 2
3 4
sheet1 MODEM_UART2_RTS 1 48 5 6
2 UART2-RTS GND 47 7 8
3 UART2-CTS GND 46 9 10
sheet1 MODEM_DOUT_UART2_RX UART2-RXD JTAG-TMS
sheet1 MODEM_DIN_UART2_TX 4 45 11 12
UART1_RTS 5 UART2-TXD JTAG-TCK 44 TDO 13 14
UART1_CTS 6 UART1-RTS JTAG-TDI 43 3V 15 16
Figure 26. VL10 HART Loop Board Reference Schematic, Sheet 2

UART1_RX 7 UART1-CTS JTAG-TDO 42 TP20 17 18
UART1_TX 8 UART1-RXD JTAG-RTCK 41 JTAG_RTCK 19 20
9 UART1-TXD RESET 40
sheet1 I2C_SDA I2C-SDA GND
sheet1 I2C_SCL 10 39
TMR1 11 I2C-SCL VCC 38 3V SBH11-PBPC-D10-ST-BK
TMR0 12 TMR1 GND 37
13 TMR0 ADC2-VREFL 36 R21 RESET_B 3V U8
TP24 SPI-SCK ADC2-VREFH
TP25 14
SPI-MOSI ADC0
35 MODEM_OCD sheet1 100K
J7
NCP301LSN27T1G
JTAG Interface
VN220 Hardware Integration Application Note v.1.2

TP26 15 34 GPIO4 sheet1
SPI-MISO ADC1
2
TP27 16 33 90120-0122
SPI-SS ADC2 GPIO5 sheet1
17 32 2 1
INPUT
18 GND ADC3 31 R19
sheet1 MODEM_ON KBI0 GND
5
TP28 19 30 MODEM_KBI_CD sheet1 100K
KBI_6 20 RTC-FOUT KBI4 29 KBI3
NC
21 KBI6 KBI3 28 KBI2 TP8
sheet1 KBI_5
22 KBI5 KBI2 27 KBI1 Mode Select Jumper 1

GND KBI1 RESET
4
23 26 TP29
24 GND RTC-INT-B 25 SW1
GND
NC
GND GND C17
TP9 SW2 3V EVQ-PAC07K 0.1uF
MC1322xRM
3
ADC2_VREFL
TP18 TP19 ADC2_VREFH Reset Pushbutton
TP16 TP7 TP6
TP10 CHS-02TA
3V J3 J4
1
FLASH Erase SW
UART1_CTS 2 1 2 1
3 2
UART1_RX 4 3
UART1_TX 5 4 90120-0122
UART1_RTS 6 5
6
TP17 22-28-4060
UART
3V
R20 J9
TP11 100K
J10 J8 TMR0 1
TMR1 2
2 1 2 1 KBI1 3
KBI2 4
KBI3 5
90120-0122 90120-0122
1
6
C18 SW3
0.1uF
EVQ-PAC07K
GND DEBUG GND DEBUG 90120-0126
2
NOTE: Place J10 and J8 on opposite sides of the board.

DEBUG CONNECTOR
APPROVALS DATE
DESIGNED BY
ENGINEER Phone: (678) 202-6800
Fax: (678)0202-6820
08-00023-01
QUALITY
WIRELESS HART LOOP BOARD SCHEMATIC
Size DWG NO Rev
C 41-00011-01 3
NIVIS LLC, Atlanta GA Sunday, July 25, 2010 Scale Sheet 2 OF 2
VN220 Radio Module TP8
SW2 +3.0V
+3.0V
+3.0V
U12
TP35 TP34 TP33 TP32 TP31 TP30 TP29 TP10 51
GND 50 TP11
RF 49 CHS-02TA J1
GND TP50 TP51
43/46
1 2
UART2_RTS 1 48 3 4
to temp/humidity sensor UART2_CTS 2 UART2-RTS GND 47 5 6
UART2_RX 3 UART2-CTS GND 46 TMS 7 8
UART2_TX 4 UART2-RXD JTAG-TMS 45 TCK 9 10
5 UART2-TXD JTAG-TCK 44 TDI 11 12
sheet3 UART1_RTS TEMP_HUM_1 6 UART1-RTS JTAG-TDI 43 TDO 13 14
7 UART1-CTS JTAG-TDO 42 RTCK 15 16
sheet3 UART1_RX UART1-RXD JTAG-RTCK
8 41 RESET 17 18
sheet3 UART1_TX 9 UART1-TXD RESET 40 19 20
to ADC sheet2 I2C_SDA 10 I2C-SDA GND 39
to ADC sheet2 I2C_SCL 11 I2C-SCL VCC 38
to HART Modem Connector sheet2 HART_MODEM_ON TMR1 GND ADC2_VREFL
12 37 SBH11-PBPC-D10-ST-BK
sheet2 5V_SW_CTRL SPI_CLK 13 TMR0 ADC2-VREFL 36 ADC2_VREFH
SPI_MOSI 14 SPI-SCK ADC2-VREFH 35 TEMP_HUM_2 to temp/humidity sensor circuit
SPI_MISO 15 SPI-MOSI ADC0 34 ADC1
SPI_SS 16 SPI-MISO ADC1 33 TEMP_HUM_CTRL
17 SPI-SS ADC2 32 +3.0V
TP39 TP38 TP37 TP36 KBY_0 GND ADC3 MODEM_OCD sheet2 OCD - to HART Modem Connector
18 31
KBI0 GND
Figure 27. VS220 HART Development Board Reference Schematic Sheet 1

19 30 U2
KBY_6 RTC-FOUT KBI4 WKU_RADIO sheet3
20 29 RDY_RADIO sheet3 +3.0V NCP301LSN27T1G
21 KBI6 KBI3 28
sheet3 KBY_5 KBI5 KBI2 USB_CTRL sheet3 to USB level translator
2
22 27
GND KBI1 KBY_1 sheet3 from boot switch
23 26
MODEM_CD_WKUP sheet2 to HART Modem Connector
INPUT
24 GND RTC-INT-B 25 R1
Appendix B. VS220 HART Development Board Reference Schematic
GND GND
5
100K
MC1322xRM
NC
+3.0V TP40 TP6
1
RESET
1
4
C1 NC
GND
R5 TP45 TP46 TP47 SW1 0.1uF
100K EVQ-PAC07K
TP12

2
3
1
SW3
C2 EVQ-PAC07K
TP7

0.1uF
J24 J23
2
D1 2 1 2 1 TP9
RED
90120-0122 90120-0122 J2
D3
GREEN UART2_TX 1 2 UART2_RTS
R2 GND DEBUG GND DEBUG UART2_RX 3 4 UART2_CTS
750 WKU_RADIO 5 6 RDY_RADIO
NOTE: Place J24 and J25 on opposite sides of the board. 7 8
9 10
R3
750
LS M67K-H2L1-1-0-2-R18-Z 5103309-1
TP48 TP49
J3
LG M67K-G1J2-24-0-2-R18-Z SPI_MOSI 1 2 SPI_CLK
+3.0V SPI_MISO 3 4 SPI_SS
TP13 WKU_RADIO 5 6 RDY_RADIO
3 2 7 8
9 10
Q1
BSS84LT1G R6
1
470K 5103309-1
TP41 TP42 TP43 TP44
3
R7 TP14
10K
U13
4 5 1
TEMP_HUM_1 3 4 5 6 Q2
TEMP_HUM_2 2 3 6 7 BSS138LT1G R8
2 7
2
1 8 470K
C3 1 8
R9 SHT15
10K 0.1uF
Temperature / Humidity Sensor
APPROVALS DATE
08-00023-01
DESIGNED BY
1000 75 Circle Pkwy.
ENGINEER Atlanta, GA 30339
Phone: (678) 202.6800 Fax: (678) 202.6820
QUALITY
HART DEVELOPMENT BOARD
Size DWG NO Rev
C 41-00015-01 4
NIVIS LLC, Atlanta GA Scale Sheet 1 OF 3
8.
NOTE: THIS CONNECTOR USED IN SOCKET CONFIGURATION
J6
1 2
1 2
44/46
+5.0V
3 4
3 4
5 6 NOTE: LABEL "MAX CURRENT ON LOOP = 200 mA"
5 6 NOTE: LABEL "LOOP CURRENT +" ON SILKSCREEN
7 8
7 8 TB1 R35 C27
9 10 100K 0.1uF
sheet1 MODEM_CD_WKUP 9 10
2
1
11 12 1 S
sheet1 MODEM_OCD 11 12 2
13 14 2 1 G
13 14 D Q4
15 16 1727010 SI1305DL
sheet3 HART_TX 15 16
3
3
sheet3 HART_RX 17 18 D
17 18 5V_SW
19 20 TR1 1 G

19 20 1249 sheet1 5V_SW_CTRL
S Q3
21 22 TP52 TP53 SI1300BDL
sheet3 HART_RTS 21 22
2
1
R32
23 24 5V_SW U3 2.5V 1M
sheet1 HART_MODEM_ON 23 24 J7
1
1 6
25 26 2 NC1 NC3 5
25 26 MODEM_OUT+ 2 1 3 GND NC2 4
+5.0V 27 28 VIN VOUT
27 28 C4 ADR121AUJZ C5 C6 +3.0V
29 30 90120-0122 0.1uF 0.1uF 0.01uF
29 30 NOTE: LABEL "MODEM OUT +" ON SILKSCREEN
1
31 32
31 32 J22
TR2
CATHODE
33 34

33 34 90120-0122
1249
35 36 NOTE: A/D IS SHUTDOWN VIA I2C BUS COMMAND
35 36
1
C29
2
37 38
37 38 J8
1
0.1uF D5 +3.0V +3.0V

39 40 SMS3922-079LF
39 40 MODEM_OUT- 2 1

ANODE
LSS-120-01-L-DV-A-TR-S
90120-0122 R37
NOTE: LABEL "MODEM OUT -" ON SILKSCREEN R33 R34
5
3
HART Modem Board Connector R12 R13 100 2 4
4.7K 4.7K
A1
A0
10 10 C28 AIN GND
0.1uF 7
U14 SCL I2C_SCL sheet1
1 8 5V_SW 6
-IN +IN SDA I2C_SDA sheet1
TB2 2 7 1 8
GND VREF_1 R30 VREF VDD +3.0V
1 3 6
1 VREF_2 V+ U5
2 4 5 24.9 ADS7823E
2 NC OUT C9
AD8210YRZ 1uF
1727010 C25 C26
1uF 0.1uF
NOTE: LABEL "MAX CURRENT ON LOOP = 200 mA"
NOTE: LABEL "LOOP CURRENT -" ON SILKSCREEN
APPROVALS DATE
DESIGNED BY
Phone: (678) 202.6800 Fax: (678) 202.6820
08-00023-01
QUALITY
Size DWG NO Rev
C 41-00015-01 4
NOTE: LABEL ON SILKSCREEN "USB POWER: POPULATE R14, DO NOT POPULATE R15 AND R16"
45/46
TB3
POWER_IN
VIN
POWER SUPPLY
D2
1
1
2 SS15-TP
R14
+5.0V LDO +3.0V
2 0 ohm-DNP
1727010 U6
R16
POWER_IN V_BATT VDD_5V_USB 1 5
SW4 U7 Vin Vout
R15 0 ohm
VIN 3 7 C10 2 4
1 VIN BOOST 0.22uF VSS NC
0 ohm
2 6 L1 22uH 3 C11
4 2 EN SW SHDNn 1uF
9 8 C12
3 PG BD 1uF MCP1802T-3002I-OT
V_BATT 10 1 C13 R17

RT FB 22pF 1M
C14 C15 4 5
GND1 GND2
Power Input Switch 2.2uF 2.2uF R18
226K LT3970EMS
C16
22uF
Silkscreen: Position 1 = External Power R36
316K
TP15 Position 2 = Battery Power
Position 3 = USB Power
Notes: In bypass mode and when applying power via USB, stuff R14, do not stuff R15, R16.
In normal mode, do not stuff R14, stuff R15, R16.

+3.0V +3.0V
BT1
BH4AA-PC
Battery Holder
R23
590K
U9 R25

D4 C20 4.7K
LG M67K-G1J2-24-0-2-R18-Z TP16 1 8 0.1uF
J9 RESET_IN VCC
VDD_5V_USB 3.3V_USB
R20
F1
2 1 R28
499K 4 7
FB1 TP17 GND RESETn KBY_5 sheet1
MICROSMD050F-2
1.6K 90120-0122 120 OHM, BLM18AG TP18 6
C18 WDI
2 1 R21 15K 3
CHASSIS_GND 2 SRT 5
C17 U8 SWT WDS
0.1uF 9 0.1uF C24
RST 12 MAX6749KAT
TP19 C19 TP20 SUSPND 11 1500pF
47pF 7 SUSPND 2
REGIN R1 TP22
8
6
6 1 TP21
J11 1 R22 27 4 Vdd DCD 28
2 R24 27 5 D+ DTR 27
D- DSR
1
3
4 TP24 C23 TP23
8
3 VBUS TxD
26
25
Power Fail Monitor
5 47pF C21 C22 GND RxD 24
R26 R27 RTS 23
CTS
2
4
TP25 15K 15K 22uF 0.1uF
9
7
TP26 CP2102-GM TP27

R29 DA1
SP0503BAHT
TP28
0 ohm
1
Jumper Settings for UARTs:
CHASSIS_GND
USB to Serial Converter HART Modem to/from VN310: Connect jumpers J12, J16, J17, J18, J19, J20
J10 USB_CTRL = 0
2 1
VN310 to/from USB: Connect jumpers J10, J21, J12,
90120-0122
USB_CTRL = 1
J21
2 1 +3.0V 3.3V_USB
90120-0122 U11
1 14
J12 TX VCCA VCCB USB_TX
2 13
RX 3 A1 B1 12 USB_RX
2 1 RTS 4 A2 B2 11 USB_RTS
5 A3 B3 10 USB_CTS
6 A4 B4 9
90120-0122 7 NC1 NC2 8
GND OE +3.0V
TXB0104PWR
Boot Switch SW5
sheet1 USB_CTRL 1
R39
J14 sheet1 KBY_1 4 2
sheet1 UART1_TX 1 2 UART1_RTS sheet1 3
3 4 C31 10K
sheet1 UART1_RX J15
5 6
sheet1 WKU_RADIO RDY_RADIO sheet1
7 8 0.1uF
9 10 2 1
5103309-1 90120-0122
J16 J17
2 1 2 1 UART1_TX
APPROVALS DATE
NIVIS LLC Atlanta, GA
sheet2 HART_RX
DRAWN BY
90120-0122 90120-0122
08-00023-01
J18 J19
DESIGNED BY
UART1_RX
sheet2 HART_TX 2 1 2 1
90120-0122 90120-0122 Phone: (678) 202.6800 Fax: (678) 202.6820
QUALITY
J20
sheet2 HART_RTS 2 1 CONFIDENTIAL OPERATIONS
90120-0122 Size DWG NO Rev
C 41-00015-01 4
3V 3V
NOTE: THIS CONNECTOR USED
U1A
46/46
IN PLUG CONFIGURATION
2 C1 C2 470pF
J1 - C3 C4
1 R2 100K 0.1uF 0.1uF
1 2 R1 3 OUT 0.1uF R4 100K
1 2 56K 4 + R3
GND
1
3 4
3 4 C7 U2A
C5 C6 MAX9912EKA 10K D1 U2B
5 6 U1B 2 1N4148W-7-F 8
5 6 - 6 VCC
R7 -
7 8 1000pF 1000pF R5 8 1 D2 7
7 8 1000pF VCC OUT OUT
2
976K 6 3 1 2 5
KBI_CD 9 10 R6 - 7 4 + +
9 10 143K 5 OUT GND
1N4148W-7-F
OCD 11 12 C8 + MAX9912EKA 1K R8 C9
11 12 MAX9912EKA
13 14 0.01uF 1M, DNP 0.01uF
13 14 MAX9912EKA
DOUT 15 16
15 16 3V
DIN 17 18
17 18
Appendix C. Nivis HART Modem Daughter Board Reference Schematic
19 20 C10 R9 200K
19 20
RTS 21 22 0.1uF
21 22 3V
23 24
23 24 U3
R10
25 26
Figure 30. HART Modem Daughter Card Reference Schematic

25 26 6 C11
27 28 4 VCC 0.1uF
27 28 - R11
VIN 29 30 5 1 2.26M U4
29 30 REF OUT
31 32 3 1K 5
31 32 2 + 3 VCC

33 34 GND +
33 34
35 36
MAX4037EUT
Carrier Detect Circuit OUT
1
35 36 4
37 38 2 -
37 38 GND LPV7215MG
39 40
39 40 HARTM_ON_GPIO1

LSS-120-01-L-DV-A-TR-P
R12 0 ohm, DNP
U5 3V
R13 3V
2
R14 Vout
3 0 ohm C12
Vin 1 C14
C13 0 ohm GND 1uF R15 0.1uF
2
1M
1uF S
MCP1702T3002E/CB
G
1
D Q1
SI1305DL
3
C15
0.1uF
16
17
18
15
11
U6
4
1
2
3
9
RSTn
DVDD1
DVDD2
DGND1
DGND2
DGND3
DGND4
DGND5
AGND
AVDD
7
XTAL1
2
Y1
8 13
ECS-36-18-18-TR XTAL2 REF C16
1
0.1uF
10 R16
XCEN 14 200K
FSK_IN C17 R17
CENTER PAD
5
19 OCD
D_OUT 12
6 FSK_OUT R18 3300pF C18 20K
RTS
CPAD
20 200K 820pF
D_IN
DS8500-JND+ C19
21
C23 10pF
0.1uF
R19 100K
U7 MODEM_OUT+
C20 R20
6
V+ C21 R21 C22 J2
4
- 1 T1 4 R22
0.1uF 100K 1
3 OUT 499 1 2
5 + 2.2uF 10 2.2uF JP1
2 SHDN 3 6 3 4
GND LT1784CS6 TMM-102-01-T-S
TY-307P 5 6
TMM-103-01-G-D
MODEM_OUT-
TX/RX Interface Circuit
APPROVALS DATE
Sandra Senn 3/24/10
08-00023-01
DESIGNED BY
ENGINEER Phone: (678) 202-6800
Fax: (678)0202-6820
QUALITY
Wireless HART Modem Board Schematic
Size DWG NO Rev
C 41-00008-01 2
NIVIS LLC, Atlanta GA Tuesday, June 29, 2010 Scale Sheet 1 OF 1
9.

Centero VN220 HW Integration Application Note

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VersaNode 220 Hardware Integration

08-00023-01 Proprietary & Confidential – NIVIS LLC

08-00023-01 VN220 Hardware Integration Application Note v.1.2 2/46

08-00023-01 VN220 Hardware Integration Application Note v.1.2 3/46

Figure 1. VN220 Pin Assignments

08-00023-01 VN220 Hardware Integration Application Note v.1.2 4/46

No. Name Description Type Dir Comments

Standard UART communication with flow

Standard UART communication with flow

Standard UART communication with flow

Standard UART communication with flow

Optional connection to firmware load interface

6 UART1-CTS UART1 Clear to Send DIG I/O Not used.

7 UART1-RXD UART1 Receive Data DIG I Standard UART communication.

8 UART1-TXD UART1 Transmit Data DIG O Standard UART communication.

9 I2C-SDA I2C bus DATA DIG I/O Not used.

10 I2C-SCL I2C bus CLOCK DIG I/O Not used.

Turns the HART Modem on (0) or off (1). Note

12 TMR0 Timer 0 I/O DIG I/O Not used.

13 SPI-SCK SPI Clock DIG O Standard SPI Communication.

14 SPI-MOSI SPI Data Out DIG O Standard SPI Communication.

15 SPI-MISO SPI Data In DIG I Standard SPI Communication.

16 SPI-SS SPI Slave Select DIG O Standard SPI Communication.

17 GND Ground N/A N/A Connect to Ground pin.

19 RTC-FOUT 32768Hz RTC clock out DIG O Not Used

Used for Display Status button. Holding this pin

21 KBI5 Keyboard interface pin 5 DIG I Power fail monitor input.

08-00023-01 VN220 Hardware Integration Application Note v.1.2 5/46

22 GND Ground N/A N/A

23 GND Ground N/A N/A

24 GND Ground N/A N/A

25 GND Ground N/A N/A

Wakeup input from the auxiliary HART Carrier

Boot switch input from SW5. If switch SW5 is

Controls output enable of USB level translator.

RDY_RADIO line. This signal is active low and is

WKU_RADIO line. This signal is active high and is

31 GND Ground N/A N/A

Modem carrier detect signal – this is a valid

33 ADC2 ADC pin 2 DIG I/O Not used.

34 ADC1 ADC pin 1 DIG I/O Not used.

35 ADC0 ADC pin 0 DIG I/O Not used.

Set ADC2-VREFH to Low and ADC2-VREFL to

WARNING: this operation will erase the Nivis

08-00023-01 VN220 Hardware Integration Application Note v.1.2 6/46

38 GND Ground N/A N/A

Connect this pin to regulated power supply VCC.

40 GND Ground N/A N/A

Reset pin of the VN220. LOW to reset and HIGH

JTAG Return Clock /

43 JTAG-TDO JTAG Test Data Output DIG O Standard JTAG interface

44 JTAG-TDI JTAG Test Data Input DIG I Standard JTAG interface

45 JTAG-TCK JTAG Test Data Input DIG I Standard JTAG interface

46 JTAG-TMS JTAG Test Mode Select DIG I Standard JTAG interface

47 GND Ground N/A N/A

48 GND Ground N/A N/A

49 GND Ground N/A N/A

To use the Nivis antenna connector, ensure C27

51 GND Ground N/A N/A

08-00023-01 VN220 Hardware Integration Application Note v.1.2 7/46

No. Name Description Type Dir Comments

Digital output from the VN220 used for HART

2 UART2-CTS UART2 Clear to Send DIG I/O Not Used (Note1).

Digital data output of the HART modem’s