FIRST SEMESTER M.TECH (ME) DEGREE END SEMESTER EXAMINATION DECEMBER 2013 SUBJECT: ADVANCED DIGITAL VLSI DESIGN (ECE -521)
TIME: 3 HOURS MAX. MARKS: 50
ECE 521 Page 1 of 2
Instructions to candidates Answer ANY FIVE full questions. Missing data may be suitably assumed. 1A. It is required to have a 1 MB SRAM. Show the complete architecture of the memory. Also show how each block can be implemented.
1B. In a CMOS inverter, both NMOS & PMOS transistors have W=2.0m, L=0.5m, process parameters k = 110 A/V, 2 and V DD & Vth are 2.2 V and 0.6V respectively. Calculate the inverter pair delay. Assume that the sheet resistance of N+ diffusion channel is 10kOhm and the electron mobility is 270 cm2/V-s. (5+5)
2A. With the help of neat diagrams explain the fabrication of NMOS transistor 2B. What is latch up in CMOS? What are its sources? Explain. 2C. Draw the circuit of a 2 input NOR gate using only 2 transistors. (5+3+2)
3A. 2-input CMOS NAND and NOR gates have been designed with feature sized transistors and if Cg = 5fF, Cout = 20fF & Rs = 2k, i) Calculate the worst-case rise and fall times for this NAND gate. ii) Calculate the best-case rise time for this NAND gate.
3B. Show the complete circuit of a 4 X 4 NOR based ROM (including the appropriate decoder) to store data values of 3, 5, 10 and 6. What are its merits and demerits? (5+5)
4A. Explain how large capacitive loads can be driven using cascaded inverters. Derive the necessary expressions.
4B. With the help of a neat circuit diagram explain BiCMOS inverter. What are its merits and demerits? Show how you can implement 2 input NAND and NOR gates using BiCMOS logic. (5+5)
ECE 521 Page 2 of 2 5A. A CMOS inverter in 0.2um technology has pull up device of 8: 2 and pull down device of 4 : 2 . If it is used to drive four identical inverters, compute the load capacitance.
5B. Define the terms: i) Set up and Hold times, ii) Clock skew and iii) Jitter. Also discuss their impact on the circuit performance. (5+5)
6A. Explain the read and write operations in a 6T SRAM with suitable circuit. Also, discuss the design criteria and estimate the Cell Ratio and Pull up ratio.
6B. Explain the following with the help of suitable circuits: (5+5) i) Decoders of memory arrays ii) Sense amplifier