EEE 211 / ETE 212 Project 1

The following project covers 30% of the theory module and 20% of the laboratory module
of EEE 211 / ETE 212. The aim of the project is to access the students ability to tie in
theoretical and experimental knowledge from the course to complete a practical project
as a latent Electronics Engineer, and to work in a team. Information on groups and Team
Leaders is outlined in Sec. 1.
The project consists of three phases. Each phase consists of an individual deadline that
are summarised in Sec. 2. It is imperative that you meet all deadlines in order to complete
the full project in due time. The mark distribution for the project is summarised in Sec. 3.
The project description is given in Sec. 4. Objectives or tasks for each phase of the project
are described in Sec. 5.
1 Groups
Each group must assign a responsible Team Leader. The responsibilities of the team
leader include (but are not limited to) the following:
Hold meeting with group and decide on design.
Hold regular meetings with group to ensure project is on track.
Delegate tasks and deadlines to individual group members.
Ensure group members complete their assigned tasks.
Ensure project deadlines are met.
Keep track of project budget, or assign another group member to do so.
Submit an online appraisal of each group member (sample form attached).
2 Deadlines
Phase I - Combinational circuit design Tuesday, 01 April 2014
Phase II - Sequential circuit design Tuesday, 08 April 2014
Phase III - Project implementation & presentation Tuesday, 15 April 2014
EEE 211 / ETE 212 Project 2
3 Mark Distribution
Mark distribution for the project is outlined below.
Report 60
Project implementation 20
Presentation 20
Total 100
Extra credit 20
Final marks will only be conrmed upon satisfactory completion of the project. Marks
will be given at the discretion of the faculty member considering the group is capable of
the work submitted based on their overall performance.
Final marks of the project will be distributed among group members based on the ap-
praisal submitted by the Team Leader. Each member of a group will be assessed individ-
ually and his/her mark may vary from other group members based on assessment during
the presentation and the appraisal.
3.1 Late Submission
Failure to meet deadlines of Phases I and II will result in a deduction of 10% for each
deadline missed.
Failure to complete the project by the nal deadline (Phase III) will incur a penalty
of 10% for each day delayed. No submissions will be accepted after 2 days of the nal
deadline and will result in an award of 0 out of 40 marks for the project implementation
and presentation.
3.2 Plagiarism
Plagiarism will NOT be tolerated. Any form of plagiarism will result in an immediate
award of 0 mark to the group for the entire project. Same applies to the hardware
implementation. If multiple reports are found as copies, an immediate award of 0 mark
shall be awarded to ALL parties without further deliberation.
EEE 211 / ETE 212 Project 3
4 Project Description
Figure 1: Counter to seven-segment display. Pressing button counts up. Code from
counter is converted by decoder to light up corresponding segments of a seven-segment
display.
Consider the digital system shown in Fig. 1. A button triggers a digital counter that
counts up from 0 to 9, and then back to 0. The binary counter is a sequential logic
system.
The counter output is connected to an active high seven-segment display via a decoder.
The decoder comprises of a combinational logic circuit that converts the BCD code from
the counter in order to drive the individual segments of the seven-segment display to show
the number pressed on the keypad.
Figure 2: Display of decimal digits by a seven-segment display.
Fig. 2 shows how each of the decimal numbers are shown on a seven-segment display.
Fig. 3 shows the schematic of seven-segment display with its segments and corresponding
input pins labelled (a g).
Extra Credit
Add another button and modify the logic to count down as well.
EEE 211 / ETE 212 Project 4
a
b
dot
dot COM
COM
g
f
e
d
c
a b g f
e d c
Figure 3: Segment and pin conguration of a seven-segment display. For an active high
display, each segment (a g and dot) light up when a logic high is applied to its corre-
sponding input pin.
5 Objectives
Phase I - Combinational Circuit Design
Deadline: Tuesday, 01 April 2014 or before
Design the combinational logic part of the system described in Sec. 4, that is, the
8421 BCD to seven-segment display decoder.
It is at the discretion of the group to opt for their choice of design - minimal logic, universal
logic, programmable logic or otherwise. However, the group must provide rationale for
their design choice and it must be using relevant material covered in the course.
The group must complete a schematic of the circuit using Logisim and submit a hard-copy
and a soft-copy of it, on or before the deadline, and during the assigned oce hours.
Phase II - Sequential Circuit Design
Deadline: Tuesday, 08 April 2014 or before
Design the sequential logic part of the system described in Sec. 4, that is, the counter.
Combine the counter with the combinational circuit of Phase I and accomplish the com-
plete circuit schematic.
EEE 211 / ETE 212 Project 5
It is at the discretion of the group to opt for their choice of design. However, the group
must provide rationale for their design choice and it must be using relevant material
covered in the course.
The group must complete a schematic of the circuit using Logisim and submit a hard-copy
and a soft-copy of it, on or before the deadline, and during the assigned oce hours.
Phase III - Project Implementation and Presentation
Date: Tuesday, 15 April 2014
The group must complete the hardware implementation of the system before this deadline
and present it on this day, along with the submission of the full report. Each member will
be asked questions and must be suitably prepared to answer any question on the project,
irrespective of the person who worked on that part.
6 Report
The report must contain the following (you can have your own headings):
Cover page with Group Name, Name of Members and IDs
Table of contents
Project specication
Design
Complete circuit design
(truth table, minimisation, etc. as required by your design)
Rationale for choice of design
Modications to design
Project costs
Diculties faced
(design, costs, resources, etc.)
EEE 211 / ETE 212 Project 6
7 Resources
Logisim: Logisim software can be downloaded from:
http://ozark.hendrix.edu/~burch/logisim/download.html
EEE 211 / ETE 212 Project 7
Appraisal Form
This form is to be completed by the Team Leader only.
Please provide details of each group member.
This form will not be shown to any other members of the group.
Please indicate the technical, theoretical, team work and initiative-taking capability of
each member of your group.
Marks must be distributed among team members such that total accounts for 100%.
Name of Group:
Full Name and ID Assess member for each category. Mark
0 being the worst, 5 being the best. distribution
Team Leader: Technical: 0 1 2 3 4 5
Theoretical: 0 1 2 3 4 5
Team work: 0 1 2 3 4 5
Initiative: 0 1 2 3 4 5
Comments:
Member 1: Technical: 0 1 2 3 4 5
Theoretical: 0 1 2 3 4 5
Team work: 0 1 2 3 4 5
Initiative: 0 1 2 3 4 5
Comments:
Member 2: Technical: 0 1 2 3 4 5
Theoretical: 0 1 2 3 4 5
Team work: 0 1 2 3 4 5
Initiative: 0 1 2 3 4 5
Comments:
Member 3: Technical: 0 1 2 3 4 5
Theoretical: 0 1 2 3 4 5
Team work: 0 1 2 3 4 5
Initiative: 0 1 2 3 4 5
Comments:
Signature of Team Leader and Date