Binary Decoder

Truth Table for a 74x138 3-to-8 binary decoder.

Enable Inputs Outputs
G1 G2 G3 A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1

Data flow style VHDL program for 3-to-8 binary decoder
library ieee;
use ieee.std_logic_1164.all;

entity B_D is
port (G1,G2,G3: in std_logic; ---- enable inputs
A: in std_Logic_vector (2 downto 0); ---- select inputs
Y: out std_logic_vector(0 to 7)); ---- decoded outputs
end B_D;

architecture AA of B_D is
signal out: std_Logic_vector (0 to 7);
begin
with A select out <=
"11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
Y<= out when (G1 and not G2 and not G3)= '1'
else "11111111";
end AA;


Binary Encoders
Truth Table for 8-to-3 Binary Encoder
Inputs Outputs
I(7) I(6) I(5) I(4) I(3) I(2) I(1) I(0) Y(2) Y(1) Y(0)
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

Data flow style VHDL program for 8-to-3 binary encoder
library ieee ;
use ieee.std_logic_1164.all;
entity B_E_1 is
port (
I : in std_logic_vector(7 downto 0) ;
y : out std_logic_vector (2 downto 0) ) ;
end B_E_1 ;

architecture Lab5 of B_E_1 is
begin

Y(0) <= I(1) OR I(3) OR I(5) OR I(7);
Y(1) <= I(2) OR I(3) OR I(6) OR I(7);
Y(2) <= I(4) OR I(5) OR I(6) OR I(7);

End Lab5;






VHDL program for 8-to-3 binary encoder (Using with select statement)
library ieee ;
use ieee.std_logic_1164.all;

entity B_E_1 is
port (G1: in std_logic;
I : in std_logic_vector(7 downto 0) ;
y : out std_logic_vector (2 downto 0) ) ;
end B_E_1 ;

architecture Lab5 of B_E_1 is
signal Out1: std_logic_vector (2 downto 0) ;
begin
with I select Out1 <=
"000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
"000" when others;
Y<= out1 when G1='1'
else "000";
end Lab5 ;


Multiplexer
Truth Table for 8-input, 1-bit multiplexer
Input Output
En S(2) S(1) S(0) Y(0)
1 x 1 0 Z --High Impedance
0 0 0 0 D
0
---- 000
0 0 0 1 D
1
---- 001
0 0 1 0 D
2
---- 010
0 0 1 1 D
3
---- 011
0 1 0 0 D
4
---- 100
0
0
0
1
1
1
0
1
1
1
0
1
D
5
D
6
D
7
---- 101
---- 110
---- 111

Dataflow VHDL program for 8-input, 1-bit multiplexer
library ieee;
use ieee.std_logic_1164.all;

entity Lab_7 is port ( s: in integer range 0 to 7;
d0,d1,d2,d3,d4,d5,d6,d7: in std_logic;
en: in std_logic;
Y: out std_logic); end lab_7;
Architecture AA of lab_7 is
signal Q1:std_logic;
begin
with s select Q1<=
d0 when 0, d1 when 1,
d2 when 2, d3 when 3,
d4 when 4, d5 when 5,
d6 when 6, d7 when 7,
'Z' when others;
Y<= Q1 when en='0' else 'Z';
end AA;


Behavioral program for 8-input, 1-bit multiplexer
library ieee;
use ieee.std_logic_1164.all;

entity mux is port ( s: in integer range 0 to 7;
d0,d1,d2,d3,d4,d5,d6,d7: in std_logic;
en: in std_logic;
Y: out std_logic); end mux;

Architecture AA of mux is
begin
process(s,d0,d1,d2,d3,d4,d5,d6,d7)
begin
if en='1' then
case s is
when 0 => y <= d0; when 1 => y <= d1;
when 2 => y <= d2; when 3 => y <= d3;
when 4 => y <= d4; when 5 => y <= d5;
when 6 => y <= d6; when 7 => y <= d7;
when others => y <= 'Z';
end case;
else Y<='Z';
end if;
end process;
end AA;


Full Adder

S= X + Y + Cin
Cout= X.Y + X.Cin + Y. Cin

Truth Table for the full adder
INPUTS OUTPUTS
CIN A B SUM COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Structural style VHDL program for the full adder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Lab_8 IS
PORT(
x : IN STD_LOGIC;
y : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END lab_8;

ARCHITECTURE ll OF Lab_8 IS
signal (q1,q2,q3,q4: std_logic;
component xor1 is port( X,Y: in std_logic; f:out std_logic); end component;
component and1 is port( X0,Y0: in std_logic; f0:out std_logic); end component;;
component or1 is port( X1,Y1,Z1: in std_logic; f1:out std_logic); end component;
Begin
u1: xor1 port map (x,y,q1);
u2: xor1 port map (q1,c_in,sum);
u3: and1 port map (x0,y0,q2);
u4: and1 port map (x0,c_in,q3);
u5: and1 port map (y0,c_in,q4);
u6: or1 port map (q2,q3,q4,c_out);
end ll;


Ripple Adder

Structural program for 4-bit ripple adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ra is
port ( x0,x1,x2,x3,c0,y1,y2,y3,y0:in std_logic;
s0,s1,s2,s3,c4: out std_logic);
end ra ;

architecture logicfunc of ra is
signal c1,c2,c3:std_logic;

COMPONENT l8 IS PORT(x,y,CN:in std_logic; sum,cout: out std_logic);end component;

BEGIN
u1: l8 PORT MAP (x0,Y0,c0,s0,c1);
u2: l8 PORT MAP (c1,x1,y1,s1,c2);
u3: l8 PORT MAP (c2,y2,x2,s2,c3);
u4: l8 PORT MAP (c3,x3,y3,c4,s3);
END logicfunc;


Carry Lock-Ahead Adder

P
i
= A
i
+ B
i
Carry propagate
G
i
= A
i
. B
i
Carry generate
S
i
= P
i
+ C
i

C
i+1
= G
i
+ P
i
C
i
Equations for a 4-bit adder:
G
0
= X
0
. Y
0
G
1
= X
1
. Y
1
G
2
= X
2
. Y
2
G
3
= X
3
. Y
3

P
0
= X
0
+ Y
0
P
1
= X
1
+ Y
1
P
2
= X
2
+ Y
2
P
3
= X
3
+ Y
3

S
0
= P
0
+ C
0
S
1
= P
1
+ C
1

S
2
= P
2
+ C
2

S
3
= P
3
+ C
3



C
1
= G
0
+ P
0
C
0
C
2
= G
1
+ P
1
C
1
= G
1
+ P
1
(G
0
+ P
0
C
0
) = G
1
+ P
1
G
0
+ P
1
P
0
G
0

C
3
= G
2
+ P
2
C
2
= G
2
+ P
2
G
1
+ P
2
P
1
G
0
+ P
2
P
1
P
0
C
0

C
4
= G
3
+ P
3
C
3
= G
3
+ P
3
G
2
+ P
3
P
2
G
1
+ P
3
P
2
P
1
G
0
+ P
3
P
2
P
1
P
0
C
0

C
1
= G
0
+ P
0
C
0
C
2
= G
1
+ P
1
C
1
C
3
= G
2
+ P
2
C
2
C
4
= G
3
+ P
3
C
3
Dataflow style VHDL program for the carry look-ahead adder
library ieee;
use ieee.std_logic_1164.all;

entity CLA_D is
port( x:in std_logic_vector(3 downto 0);
y:in std_logic_vector(3 downto 0);
c0: in std_logic;
s: out std_logic_vector(3 downto 0);
c4:out std_logic);
end CLA_D;

architecture CLA of CLA_D is
signal c1,c2,c3,g0,g1,g2,g3,p0,p1,p2,p3:std_logic;

begin
g0<=x(0) and y(0);
g1<=x(1) and y(1);
g2<=x(2) and y(2);
g3<=x(3) and y(3);

p0<=x(0) xor y(0);
p1<=x(1) xor y(1);
p2<=x(2) xor y(2);
p3<=x(3) xor y(3);

s(0)<=p0 xor c0;
s(1)<=p1 xor c1;
s(2)<=p2 xor c2;
s(3)<=p3 xor c3;

c1<=g0 or (p0 and c0);
c2<=g1 or (p1 and c1);
c3<=g2 or (p2 and c2);
c4<=g3 or (p3 and c3);

end CLA;


Subtractor
D= X + Y + Bin
Bout= X.Y + X.Bin + Y. Bin

Input Output
Bin X Y D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1
1
1
0
1
1
1
0
1
0
0
1
1
0
1

Structural VHDL program for Full Subtractor
library ieee;
use ieee.std_logic_1164.all;

entity FS is
port ( x,y,Bin: in std_logic;
D, Bo: out std_logic);
end FS;

architecture Sub of FS is
signal NX,Q1,Q2,Q3,Q4: std_logic;

Component and1 is port ( X0,Y0:in std_logic; F0:out std_logic);end component;
Component xor1 is port ( x1,y1:in std_logic; F1:out std_logic);end component;
Component or1 is port ( X2,y2,z:in std_logic;F2:out std_logic);end Component;
Component inv is port ( X3:in std_logic; F3:out std_logic);end Component;

Begin
U1: inv port map(x,NX);
U2: xor1 port map(x,y,Q1);
U3: xor1 port map(Q1,Bin,D);
U4: and1 port map(NX,Y,Q2);
U5: and1 port map(NX,Bin,Q3);
U6: and1 port map(Y,Bin,Q4);
U7: or1 port map(Q2,Q3,Q4,Bo);

end Sub;







Behavioral (if statement) VHDL program for Full Subtractor
library IEEE;
use IEEE.std_logic_1164.all;

entity FSB is
port (x,y,Bin: in std_logic;
D, Bout: out std_logic);

end FSB;

architecture bb of FSB is
begin
process (x,y,Bin)
begin
if (x = '0' and y = '0' and Bin ='0') then
D <= '0' ;
Bout <= '0';

elsif (x = '0' and y = '1' and Bin ='0') then
D <= '1' ;
Bout <= '1';

elsif (x = '1' and y = '0' and Bin ='0')then
D <= '1' ;
Bout <= '0';

elsif (x = '1' and y = '1' and Bin ='0') then
D <= '0' ;
Bout <= '0';

elsif (x = '0' and y = '0' and Bin ='1') then
D <= '1' ;
Bout <= '1';

elsif (x = '0' and y = '1' and Bin ='1') then
D <= '0' ;
Bout <= '1';

elsif (x = '1' and y = '0' and Bin ='1')then
D <= '0' ;
Bout <= '0';

elsif (x = '1' and y = '1' and Bin ='1') then
D <= '1' ;
Bout <= '1';

else
D <= '0' ;
Bout <= '0';
end if;
end process;
end bb;

Behavioral (Simple statement) VHDL program for Full Subtractor
library ieee;
use ieee.std_logic_1164.all;

entity FS is
port ( X,Y,Bin: in std_logic;
D,Bout:out std_logic);
end FS;

architecture Sub of FS is
begin

process(x,y,Bin)

begin
D<= (X xor Y) xor Bin;
Bout<= (not x and Y)or(not X and Bin)or(Y and Bin);
end process;

end Sub;



Active High Input ( S-R Latches)



Behavioral style VHDL program for the Active High S-R Latch(With case statements
library ieee;
use ieee.std_logic_1164.all;

entity AH is
port( S_R: in std_logic_vector (1 downto 0) ;
Q_QN:buffer std_logic_vector (1 downto 0));
end AH;

architecture F of AH is
begin
process (S_R)
begin
case s_r is

when "00" => Q_QN <= "ZZ";
when "01" => Q_QN <= "01";
when "10" => Q_QN <= "10";
when "11" => Q_QN <= "00";

end case;
end process;
end F;



Behavioral style VHDL program for the Active High S-R Latch(With if statements)
library ieee;
use ieee.std_logic_1164.all;

entity AH1 is
port( S,R: in std_logic ;
Q, QN:buffer std_logic);
end AH1;

architecture F of AH1 is
begin
process (S,R)
begin
if ( s='0' and r='0') then Q<='Z';QN<='Z';
elsif ( s='0' and r='1') then Q<='0';QN<='1';
elsif ( s='1' and r='0') then Q<='1';QN<='0';
elsif ( s='1' and r='1') then Q<='0';QN<='0';

end if;
end process;
end F;end process;
end F;



Active Low Input (S-R Latches)


Behavioral style VHDL program for the Active Low S-R Latch(With simple statements)
library ieee;
use ieee.std_logic_1164.all;

entity AL is
port( S,R:in std_logic ;
Q,QN:buffer std_logic);
end AL;

architecture F of AL is
begin

Q<= s nand QN;
QN<= r nand Q;

end F;


Behavioral style VHDL program for the Active Low S-R Latch(With if statements)
library ieee;
use ieee.std_logic_1164.all;

entity AL1 is
port( S,R: in std_logic ;
Q, QN:buffer std_logic);
end AL1;

architecture F of AL1 is
begin
process (s,r)
begin
if ( s='0' and r='0') then Q<='1';QN<='1';
elsif ( s='0' and r='1') then Q<='1';QN<='0';
elsif ( s='1' and r='0') then Q<='0';QN<='1';
elsif ( s='1' and r='1') then Q<='Z';QN<='Z';

end if;
end process;
end F;