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Electronics 284

Digital / Analog Simulations - PSpice Notes

(Handout prepared by P. Ribeiro and Ken Morgan)


Creating a Circuit - Get New Part











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Draw - Wire Components


Draw Get New parts - Add DigitaI SignaI Sources









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Edit Attributes


WaveIorms


Construct Circuit and Add V and I Markers


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AnaIysis - SimuIation Setup





AnaIysis - Probe Setup

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AnaIysis - SimuIate




Probe


BuiIding CompIex Pure DigitaI Circuits
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BuiIding AnaIog / DigitaI Circuits




Ior extra credit - Try your own circuits















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Electronics 284

Digital / Analog Simulations - PSpice

(Handout prepared by Ken Morgan)

Ideas to Implement the Design Labs

Note: These are onIy intended as ideas. They don`t necessariIy represent the best way to impIement the
design.

Design Lab |1



Notes: Output oI the IIip-IIop becomes the cIock signaI to the next one. The output oI the IoIIowing IIip-
IIop becomes haII the Irequency oI the previous one. The AND gates aIIow the switches to decide iI the
Iight wiII Iunction.


Design Lab |2



Notes: The second pattern is just haII the Irequency oI the Iirst pattern. The third pattern wiII be a zero
when patterns one and two are both zero. The XOR`s onIy aIIow one pattern to be shown at a time.
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Design Lab |3



Notes: The two J K IIip-IIops count up. The switches and the Iogic gates decide when to stop counting and
start over.


Design Lab |4



Notes: The universaI shiIt register moves a bit aIong the outputs. II L1 and L2 are both zero, the next bit
shiIted in wiII be a zero.
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Design Lab |5



Notes: The universaI shiIt register shiIts in a high bit untiI L3 is Iit. When L3 is Iit, the register Ioads in the
Iow bits on inputs A, B, and C. The 4-input NAND gate keeps the circuit going as Iong as a Iight is on.


Design Lab |6



Notes: The universaI shiIt register Ioads in the vaIues oI A, B, and C, when SW3 changes. Those bits pass
through a Iogic array that sets Q high on the D-Iatch iI the correct combination is appIied. The OR gates
keep the Iatch Irom changing once it`s set. The two NOT gates in a row provide a time deIay. There are
aIso extra AND gates to make sure the numbers are suppIied in the correct order.
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Design Lab |7



Notes: The universaI shiIt registers move a high bit aIong the eight outputs. The D IIip-IIops aIIow a
change in SW8 to act as a paddIe to hit the baII and send it the other direction. The OR gates in series
test the outputs and aIIow the baII to be put into pIay onIy when aII outputs are zero. The J K IIip-IIop
toggIes S1 and S0 in order to determine the direction the baII traveIs.