Design and Implementation of a Fully Digital 4FSK

Demodulator
Nariman Moezzi Madani, Javad Hadi and S. Mehdi Fakhraie
*



*
Department of Electrical and Computer Engineering, University of Tehran, Iran
e-mail: n.moezi@ece.ut.ac.ir, fakhraie@ut.ac.ir.
Abstract: In this paper a fully digital 4FSK demodulator
for double-conversion superheterodyne pager receivers
based on ERMES standard is proposed. The
demodulator includes three major parts: frequency
discriminator, symbol detector and clock recovery
modules. The key point in this design is its
implementation through a simple hardware by avoiding
complex algorithms and expensive hardware such as
multipliers and dividers. Low power consumption is
another important factor that has been considered in
system-level and hardware-level design. The system was
designed in 0.6um CMOS process and resulted in a
module with only 5472 transistors. Its performance was
tested by FPGA-emulated experiments and good
agreement between measurement and simulation is
observed.
1 INTRODUCTION
Recently, there has been a strong trend forward fully
integrated wireless communication systems. Full
integration reduces power consumption, chip area and
lowers the cost. Frequency modulation with its
superior performance over amplitude modulation is
used in many different wireless communication
standards. There are many analog structures for
FM/FSK demodulators but reliability, flexibility,
scalability and ease of integration of digital CMOS
circuits attract more work in the field of digital signal
processing [1]. There are structures for MFSK
demodulators for wireless communication systems
[2],[3],[4] and [5]. Direct conversion was very
common because of its compact and low cost nature. It
was first used for a POCSAG radio paging receiver
and demonstrated its value in feature works, but as the
paging system advanced to use the higher speed FLEX
or ERMES protocols, considerable effort was naturally
put in the implementation of direct-conversion in these
new systems.
Unlike POCSAG, FLEX and ERMES make use of
4FSK modulation and support more than 6Kbits/s data
rates. While the available bandwidth keeps unchanged,
the modulation index is decreased and additional
difficulties are imposed on the design of Direct-
conversion receivers [5].
Another structure is superheterodyne that is the first
structure in radio receivers. This structure dealt good
with receivers because of simplicity of its circuits. In
this method, some out of chip components such as
ceramic filters were used that increased the area and
power of the chip. By using double-conversion
superheterodyne some of the problems were solved.
We can design an efficient, simple and fully digital
demodulator. The structure of double conversion
superheterodyne receiver is shown in Figure 1. After
antenna, there is a pass-band amplifier that amplifies
the desired signal in RF band and eliminates the
others. In theory, we can get the bandwidth as narrow
as we want, simply by going to a lower IF frequency.
But if we do that, then the image frequency gets closer
to the desired frequency, and then RF tuned circuits
may not be able to get rid of it. So we have two
conflicting requirements: 1) To get better selectivity-
lower bandwidth- we want to lower the IF frequency
2) to get better rejection of the image frequency, we
want to raise the IF frequency [6].
For example, to receive 169.4 MHz, the first oscillator
runs at 169.4-10.7 MHz, so the signal will be at first
IF, 10.7 MHz. The second oscillator and mixer convert
the 10.7MHz first IF signal to 455KHz. By using two
IF frequencies, the double conversion receiver solves
our two problems. The higher first IF frequency does
not provide much selectivity, but it helps to eliminate
the image. The second IF frequency of 455KHz, is low
enough that even transformers with reasonable Q can
provide a narrow bandwidth [7].

RF
Section
First
Oscillator
Antenna
Second
Oscillator
DATA
157.64 MHz 11.155 MHz
10.7 MHZ 455 KHZ 169.4 MHZ
1st
Mixture
1st
IF
2nd
Mix.
2nd
IF
4FSK
Demodulator


Figure 1.Double conversion receiver structure [7].

Symbol Symbol Frequency
10 +F2=Fc+4.6875KHz
11 +F1=Fc+1.5626KHz
01 -F1=Fc-1.5625KHz
00 -F2=Fc-4.6875KHz
Table 1. Parameters and their values [8].
Frequency
Discrimin
Half Symbol
Integrator
DC Offset
Compute
IF
Input
DC Removing
CLK(Fs)
+
ERR
Compute
ERR
Compute
ERR
Compute
ERR
Compute
F2,F1
+
-
+
+
+
-
Minimum
Select
MUX
2*1
Loop
Filter
NCO
Baud-Rate
D0
D1
Err_Early(+f2)
Err_Late(+f2)
Err_Early(+f1)
Err_Late(+f1)
Err_Early(-f1)
Err_Late(-f1)
Err_Early(-f2)
Err_Late(-f2)
+L1
-L1
+L2
-L2
Err(+f2)
PD(+f2)
Err(+f1)
Err(-f1)
Err(-f2)
PD(-f2)
ERR
PD
PD

Figure 2: 4FSK Demodulator.
Compare to 5
ZC
Fi Fi
IF
Input
Comparator Counter
CLK CLK
CLK CLK
Counter
Ti
Pos-Edge
detector
Period
Measurment
Pulse-Width
Control

Figure 3. Frequency Discriminator.

The receiver receives the signal from a specific
channel with symbol rate of F
b
=3125Hz and bit rate
of 6250 bit/s. In the 4FSK modulator, data is formed
into 2 bit groups and then into 4PAM signal. This
signal will be transmitted by carrier frequency of F
c
=
169.4MHz [8]. Each 2-bit symbol changes the central
carrier frequency a little as it is shown in Table 1.

2 FSK DEMODULATOR

This demodulator is made of 3 parts: frequency
discriminator, symbol detector, and clock recovery
(Fig. 2). There is proposed a new technique for
frequency discriminator that uses period measurement
and time-to-frequency conversion using a simple
method. It has a 1-bit output with linear characteristics.
Symbol detector is an I&D (integrate and dump) unit
that computes frequency error for all symbols, twice in
each symbol period. The symbol corresponding to the
minimum frequency error value is considered as an
estimation of the transmitted symbol. Clock recovery
is carried out by using a digital PLL. The DPLL
consists of a phase detector, plus a digital filter
together with a numerically controlled oscillator
(NCO). For phase detection, a double gate scheme
(Early-Late) has been employed. The major advantage
of the synchronization structure is that it is fully digital
and can be reliably implemented. In this section, all
parts of the system are described.

400 450
500
640
-640
f(KHz)

Figure 4. I&D Output.
2.1. Frequency Discriminator

The input signal to this block is at the second IF
frequency. A hard limiter is used at the first stage of
the demodulator and converts the sinusoidal signal into
rectangular pulses. In this paper, a new technique for
measuring frequency is proposed (Fig. 3). This method
calculates the period of the input signal. At first, the
time distance between any two rising edge of the input
signal is measured by the mean of a counter that works
with frequency of F
s
=2MHz. By selecting higher
frequencies, we can obtain more accurate
measurements, but in order to achieve a low-power
system, we selected this frequency as the lowest
possible one.
The input signal frequency is between 455+4.687KHz
and 455-4.687KHz, so the counter output always will
have the value 4 or 5 that is stored in a latch. If it is 5,
a pulse with the width of 5*T
s
will be generated at the
output of the frequency discriminator, and if it is 4,
output will be zero. This system has a linear
characteristic as shown in Figure 4. This characteristic
is obtained by using an Up/Down counter with 2MHz
frequency at the end of this discriminator. In order to
eliminate the offset between 450KHz and 455KHz
signals, we have used a simple circuit.
+F2 -F2
Early Late
Transmitter
Clock
Rciever
Clock

Figure 5. Phase difference.

+
REG
PDOut
PDF
K0
K1
Baud Rate

Figure 6. Loop filter.

RESET
LOGIC
Toggle
Flip-Flop
PDF
Counter
Baud Rate
Fd=200KHz

Figure 7. Numerically controlled oscillator.


2.2. Symbol Detector

The symbol detector system includes some blocks of
the clock recovery system and uses Early-Late
technique. In this block, with the help of an up-down
counter as I&D block, we integrate the output of the
frequency discriminator in half symbol periods. The
results are as shown in Figure 4. Comparing the
measured integral with pre-measured values in Fig. 4,
we can modify the received symbol. Firstly, we
calculate the absolute value of the difference between
the measured integral and specific values for each of
the 4 symbols, and select the symbol that has the
minimum error. However, since there is always some
jitter between transmitter and receiver clocks, the sum
of errors of both early and late periods specifies the
right symbol. For example the error calculated for +F2
(459.6KHz) frequency is shown:

+ =
=
=
Late Err Early Err Err
L Late Late Err
L Early Early Err
_ _
2 _
2 _
(1)
L2 is the output of I&D block when the input
frequency is accurately 459.6875 KHz.

2.3. Clock Recovery

In ERMES standard, clock pulse is not transmitted
with signal and must be generated at the receiver, and
then to be synchronized with the transmitter clock. The
clock recovery system in this paper uses Early-Late
technique [10]. In ERMES standard data is sent in 60-
second sequences, each sequence is divided into 5
subsequences. Each subsequence includes 16 batches
and in the first of each batch there is the preamble.
Preamble is a sequence with 15 symbols and is formed
by repeating the symbols 00,01 [9]. The clock
recovery system uses preamble to make itself in-phase
with transmitter at the beginning of each frame.
To understand the operation of this system, assume
that there is a negative phase difference between the
receiver clock and the received symbols (Fig. 5), so the
early period includes symbol +F2 while the late period
includes some of F2 symbol too. So, the error value
of symbol +F2 for early is zero while this value for late
is non-zero. The difference between two values
determines the Phase Difference between sender and
receiver clocks. In this example, we have:

PD = (Err_Early Err_Late) < 0 (2)

This negative value enters a digital filter (Fig. 6) with
coefficients
4
1
7
0
2 , 2

= = K K
. This filter has strong
effect on the stability of PLL system. These
coefficients are powers of 2 in order to be
implemented simply by shift operation; the transfer
function of the filter is:
1
1 0
. ) (

+ = z K K z H (3)
The third block of the clock recovery system is a NCO
(Fig. 7). NCO is a programmable counter that
generates baud-rate clock with center frequency of F
b
=
6250Hz. The counter works with clock frequency of
F
d
= 200KHz and the reset logic resets the counter on
specific times. The frequency deviation of the baud
rate is defined by the output of the loop filter (PDF).
The period of generated signal by NCO can be
calculated by:

Fd
PDF
T T
b NCO
* 2 =
(4)

3 RESULTS

The clock recovery circuit is the most important part of
the circuit. It has to synchronize transmitter and
receiver under different jitter conditions. The whole
system was simulated in Additive White Gaussian
Noise environment. The loop filter output (Fig. 8)
shows that the system makes itself in-phase with
transmitter in the first few symbols of each frame
(preamble) with different jitter values between the
transmitter and the receiver. The most important
parameters that introduce the performance of the
circuit are Bit Error Rate (BER) and Frame Error. In
our simulations, it was found that for SNRs greater
than 7dB, there is no frame error and the BER value
for SNRs greater than 8dB is lower than 10
-4
that is a

a)

b)

c)
Figure 8. Loop filter output versus time (s) with
different jitters: a) 25% b) 45% c) 70%.


Figure 9: BER and frame error versus SNR.


#Logic Cells Max. Clock Frequency
210 (%18) 75.5 MHz
Table 2. Implementation results on FPGA IC.

#Transistor Max. Clock Frequency
5472 414MHz
Table 3. Implementation Results with 0.6um CMOS Process.

common rate for communication systems (Fig. 9). By
using time interleaving and error correction techniques
in ERMES standard, BER will be lowered more.
The demodulator unit was implemented on the Altera
FPGA IC: FLEX-EPF10K20RC208 and also was
synthesized and simulated with 0.6um CMOS process.
Tables 2 and 3 show the implementation parameters of
the demodulator.
4 Conclusion

In this paper we proposed design of a fully digital
4FSK demodulator in detail. Double conversion
superheterodyne structure was selected for the
receiver. This structure allowed us to design a fully
integrated system with a simple implementation,
avoiding using complex algorithms and expensive
hardware such as multipliers and dividers. System-
level techniques were used to make a very low-power
demodulator. The demodulator was implemented on a
FPGA IC and in 0.6um CMOS process and resulted in
a module with only 5472 transistors.

5 Acknowledgement

The authors wish to express their thanks to Iran
Telecommunication Research Center (ITRC) for the
financial support during the course of this research.

References

[1] H. M. Eissa, K. Sharaf and H. Ragaie, ARCTAN
differentiated digital demodulator for FM/FSK
digital receivers, IEEE 45th Midwest Symposium
on Circuits and Systems (MWSCAS), vol. 2, pp. II-
200 - II-203, Aug. 2002.
[2] Hans Gustat and Frank Herzel, Integrated FSK
with very high sensitivity, IEEE J. of Solid-State
Circuits, vol. 38, no. 2, pp. 357-360 Feb. 2003.
[3] H. C. Liu and H. Samueli, A low power
baseband receiver IC for frequency hopped spread
spectrum communications, IEEE J. Solid-State
Circuits, vol. 31, no. 3, pp. 384-394, March 1996.
[4] Z. Chen etal. , Circuit requirements of a direct-
conversion paging receiver, IEEE Tran. Circuits
Syst. II, vol. 46, no. 6, pp. 802-807, June 1999.
[5] J. Lau, A CMOS 2- and 4-FSK demodulator for
direct-conversion radio paging receivers, IEEE
International Conference on Communications,
Circuits and Systems and West Sino
Expositions, vol. 2, pp. 1289 292, July 2002.
[6] T. Yang and W. Mikhael, Baseband image
rejection for diversity superheterodyne receivers,
IEEE Wireless Communications and Networking
Conference, vol. 4, pp. 2232-2234, Mar. 2004.
[7] Electronic file available at
www.users.cloud9.net/~stark/ct9.pdf, 2004.
[8] ETSI 300 133-3, Radio Equipment and Systems
(RES), Enhanced Radio Message System
(ERMES), Part3: Network Aspects, Jan. 1997.
[9] ETSI 300 133-4, Radio Equipment and Systems,
Enhanced Radio Message System (ERMES),
Part4: Air Interface Specification, Jan. 1997.
[10] W. C. Lindsey and C. M. Chie, A survey of
digital phased-locked loops, IEEE Proc., vol. 69,
no. 4, pp. 410-431, Apr.1981.