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2003 by CRC Press LLC

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ROM/PROM/EPROM

2.1 Introduction ........................................................................

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2.2 ROM.....................................................................................

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Core Cells Peripheral Circuitry Architecture

2.3 PROM ..................................................................................

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Read-Only Memory Module Architecture Conventional
Diffusion Programming ROM Conventional VIA-2 Contact
Programming ROM New VIA-2 Contact Programming
ROM Comparison of ROM Performance

2.1 Introduction

Read-only memory (ROM) is the densest form of semiconductor memory, which is used for the appli-
cations such as video game software, laser printer fonts, dictionary data in word processors, and sound-
source data in electronic musical instruments.
The ROM market segment grew well through the rst half of the 1990s, closely coinciding with a jump
in personal computer (PC) sales and other consumer-oriented electronic systems, as shown in Fig. 2.1.

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Because a very large ROM application base (video games) moved toward compact disk ROM-based
systems (CD-ROM), the ROM market segment declined. However, greater functionality memory prod-
ucts have become relatively cost-competitive with ROM. It is believed that the ROM market will continue
to grow moderately through the year 2003.

2.2 ROM

Read-only memories (ROMs) consist of an array of core cells whose contents or state is preprogrammed
by using the presence or absence of a single transistor as the storage mechanism during the fabrication
process. The contents of the memory are therefore maintained indenitely, regardless of the previous
history of the device and/or the previous state of the power supply.

2.2.1 Core Cells

A binary core cell stores binary information through the presence or absenc of a single transistor at the
intersection of the wordline and bitline. ROM core cells can be connected in two possible ways: a parallel
NOR array of cells or a series NAND array of cells each requiring one transistor per storage cell. In this
case, either connecting or disconnecting the drain connection from the bitline programs the ROM cell.
The NOR array is larger as there is potentially one drain contact per transistor (or per cell) made to each
bitline. Potentially, the NOR array is faster as there are no serially connected transistors as in the NAND
array approach. However, the NAND array is much more compact as no contacts are required within
the array itself. However, the serially connected pull-down transistors that comprise the bitline are
potentially very slow.

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Jen-Sheng Hwang

National Science Council

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Memory, Microprocessor, and ASIC

Encoding multiple-valued data in the memory array involves a one-to-one mapping of logic value to
transistor characteristics at each memory location and can be implemented in two ways:
(i) Adjust the width-to-length (W/L) ratios of the transistors in the core cells of the memory array, or
(ii) Adjust the threshold voltage of the transistors in the core cells of the memory array.

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The rst technique works on the principle that the W/L ratio of a transistor determines the amount of
current that can ow through the device (i.e., the transconductance). This current can be measured to
determine the size of the device at the selected location and hence the logic value stored at this location.
In order to store 2 bits per cell, one would use one of four discrete transistor sizes. Intel Corp. used this
technique in the early 1980s to implement high-density look-up tables in its i8087 math co-processor.
Motorola Inc. also introduced a four-state ROM cell with an unusual transistor geometry that had variable
W/L devices. The conceptual electrical schematic of the memory cell, along with the surrounding periph-
eral circuitry, is shown in Fig. 2.2.

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2.2.2 Peripheral Circuitry

The four states in a 2-bit per cell ROM are four distinct current levels. There are two primary techniques
to determine which of the four possible current levels an addressed cell generates. One technique
compares the current generated by a selected memory cell against three reference cells using three separate
sense ampliers. The reference cells are transistors with W/L ratios that fall in between the four possible
standard transistor sizes found in the memory array as illustrated in Fig. 2.3.

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The approach is essentially a 2-bit ash analog-to-digital (A/D) converter. An alternate method for
reading a two-bit per cell device is to compute the time it takes for a linearly rising voltage to match the
output voltage of the cell. This time interval then can be mapped to the equivalent 2-bit binary code
corresponding to the memory contents.

FIGURE 2.1

The ROM market growth and forecast.

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ROM/PROM/EPROM

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FIGURE 2.2

Geometry-variable multiple-valued NOR ROM.

FIGURE 2.3

ROM sense amplier.

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Memory, Microprocessor, and ASIC

2.2.3 Architecture

Constructing large ROMs with fast access times requires the memory array to be divided into smaller
memory banks. This gives rise to the concept of divided word lines and divided bit lines that reduces
the capacitance of these structures, allowing for faster signal dynamics. Typically, memory blocks would
be no larger than 256 rows by 256 columns. In order to quantitatively compare the area advantage of
the multiple-valued approach, one can calculate the area per bit of a 2-bit per cell ROM divided by the
area per bit of a 1-bit per cell ROM. Ideally, one would expect this ratio to be 0.5. In the case of a practical
2-bit per cell ROM,

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the ratio is 0.6 since the cell is larger than a regular ROM cell in order to accommodate
any one of the four possible size transistors. ROM density in the Mb capacity range is in general very
comparable to that of DRAM density despite the differences in fabrication technology.

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In user-programmable or eld-programmable ROMs, the customer can program the contents of the
memory array by blowing selected fuses (i.e., physically altering them) on the silicon substrate. This allows
for a one-time customization after the ICs have been fabricated. The quest for a memory that is nonvolatile
and electrically alterable has led to the development of EPROMs, EEPROMs, and ash memories.

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2.3 PROM

Since process technology has shifted to QLM or PLM to achieve better device performance, it is important
to develop a ROM technology that offers short TAT, high density, high speed, and low power. There are
many types of ROM, each with merits and demerits:

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The diffusion programming ROM has excellent density but has a very long process cycle time.
The conventional VIA-2 contact programming ROM has better cycle time, but it has poor density.
An architecture VIA-2 contact programming ROM for QLM and PLM processes has simple pro-
cessing with high density which obtains excellent results targeting 2.5 V and 2.0 V supply voltage.

2.3.1 Read-Only Memory Module Architecture

The details of the ROM module conguration are shown in Fig. 2.4. This ROM has a single access
mode (16-bit data read from half of ROM array) and a dual access mode (32-bit data read from both

FIGURE 2.4

ROM module array conguration.

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ROM/PROM/EPROM

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ROM arrays) with external address and control signals. One block in the array contains 16-bit lines and
is connected to a sense amplier circuit as shown in Fig. 2.5. In the decoder, only one bit line in 16 bits
is selected and precharged by P1 and T1.

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16 bits in half array at a single access mode or 32 bits in a dual access mode are dynamically
precharged to VDD level. Dl is a pul-down transistor to keep unselected bit lines at ground level. The
speed of the ROM will be limited by bit line discharge time in the worst-case ROM coding. When
connection exists on all of bit lines vertically, total parasitic capacitance Cbs on the bit line by N-
diffusions and Cbg will be a maximum. Tills situation is shown in Fig. 2.6a. In the 8KW ROM, 256
bit cells are in the vertical direction, resulting in 256 times of cell bit line capacitance. In this case,
discharge time from VDD to GND level is about 6 to 8 ns at VDD = 1.66 V and depends on ROM
programming type such as diffusion or VIA-2. Short circuit currents in the sense amplier circuits
arc avoided by using a delayed enable signal (Sense Enable). There are dummy bit lines on both sides
of the array, as indicated in Fig 2.4. This line contains 0s on all 256 cells and has the longest discharge
time. It is used to generate timing for a delayed enable signal that activates the sense amplier circuits.
These circuits were used for all types of ROM to provide a fair comparison of the performance of each
type of ROM.

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FIGURE 2.5

Detail of low power selective bit line precharge and sense amplier circuits.

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2.3.2 Conventional Diffusion Programming ROM

Diffusion programmed ROM is shown in Fig. 2.6. This ROM has the highest density because bit
line contact to a discharge transistor can be shared by 2-bit cells (as shown in Fig. 2.6). Cell-A in
Fig. 2.6(a) is coding 0 adding diffusion which constructs transistor, but Cell-B is coding 1 which
does not have diffusion and results in eld oxide without transistor as shown in Fig. 2.6(c). This
ROM requires a very long fabrication cycle time since process steps for the diffusion programming
are required.

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2.3.3 Conventional VIA-2 Contact Programming ROM

In order to obtain better fabrication cycle time, conventional VIA-2 contact programming ROM was
used as shown in Fig. 2.7. Cell-C in Fig. 2.7(a) is coding 1; Cell-D is coding 1. There are determined
by VIA-2 code existence on bit cells. The VIA-2 is nal stage of process and base process can be completed
just before VIA-2 etching and remaining process steps are quite few. So, VIA-2 ROM fabrication cycle
time is about 1/5 of the diffusion ROM. The demerit of VIA-2 contact and other types of contact
programming ROM was poor density. Because diffusion area and contact must be separated in each
ROM bit cell as shown in Fig. 2.7(c), this results in reduced density, speed, and increased power. Metal-
4 and VIA-3 at QLM process were used for word line strap in the ROM since RC delay time on these
nobles is critical for 100 MIPS DSP.

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2.3.4 New VIA-2 Contact Programming ROM

The new architecture VIA-2 programming ROM is shown in Fig. 2.8. A complex matrix constructs each
8-bit block with GND on each side. Cell-E in Fig. 2.8

(

a) is coding 0. Bit 4 and N4 are connected by
VIA-2. Cell-F is coding 1 since Bit 5 and N5 are disconnected. Coding other bit lines (Bit 0, 1, 2, 3,5,
6, and 7) follows the same procedure. This is one of the coding examples to discuss worst-case operating
speed. In the layout shown in Fig. 2.8(b), the word line transistor is used not only in the active mode
but also to isolate each bit line in the inactive mode. When the word line goes high, all transistors are
turned on. All nodes (N0N7) are horizontally connected with respect to GND. If VIA-2 code exists on

FIGURE 2.6

Diffusion programming ROM.

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ROM/PROM/EPROM

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FIGURE 2.7

Conventional VIA-2 programming ROM.

FIGURE 2.8

New VIA-2 programming ROM.

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Memory, Microprocessor, and ASIC

all or some nodes (N0N7) in the horizontal direction, the discharge time of bit lines is very short since
this ROM uses a selective bit ne precharge method.

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Figure 2.9 shows timing chart of each key signal and when Bit 4 is accessed, for example, only this
line will be precharged during the precharge phase. However, all other bit lines are pulled down to
GND by Dl transistors as shown in Fig. 2.4. When VIA-2 code exists like N4 and Bit 4, this line will
be discharged. But if it does not exist, this line will stay at VDD level dynamically, as described during
the word line active phase, which is shown in Fig. 2.9. After this operation, valid data appears on the
data out node of data latch circuits.

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In order to evaluate worst-case speed, no VIA-2 coding on horizontal bit cell was used since transistor
series resistance at active mode will be maximum with respect to GND. However, in this situation, charge
sharing effects and lower transistor resistance during the word line active mode allow fast discharge of
bit lines despite the increased parasitic capacitance on bit line to 1.9 times. This is because all other nodes
(N0N7) will stay at GND dynamically. The capacitance ratio between bit line (Cb) and all nodes except
N4 (Cn) was about 20:1. A fast voltage drop could be obtained by charge sharing at the initial stage of
bit line discharging. About ve voltage drop could be obtained on an 8KW conguration through the
charge sharing path shown in Fig. 2.9(c). With this phenomenon, the full level discharging was mainly
determined by complex transistor RC network connected to GND as shown in Fig. 2.8(a). This new
ROM has much wider transistor width than conventional ROMs and much smaller speed degradation
due to process deviations, because conventional ROMs typically use the minimum allowable transistor
size to achieve higher density and are more sensitive due to process



variations.

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FIGURE 2.9

Timing chart of new VIA-2 programming ROM.

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2.3.5 Comparison of ROM Performance

The performance comparison of each type of ROM is listed in Table 2.1. An 8KW ROM module area
ratio was indicated using same array conguration, and peripheral circuits with layout optimization to
achieve fair comparison. The conventional VIA-2 ROM was 20% bigger than diffusion ROM, but the
new VIA-2 ROM was only 4% bigger. The TAT ratio (days for processing) was reduced to 0.2 due to
nal stage of process steps. SPICE simulations were performed to evaluate each ROM performance
considering low voltage applications. The DSP targets 2.5 V and 2.0 V supply voltage as chip specication
with low voltage comer at 2.3 V and 1.8 V, respectively. However, a lower voltage was used in SPICE
simulations for speed evaluation to account for the expected 7.5 supply voltage reduction due to the IR
drop from the external supply voltage on the DSP chip. Based on this assumption, VDD = 2.13 V and
VDD = 1.66 V were used for speed evaluation. The speed of the new VIA-2 ROM was optimized at 1.66
V to get over 100 MHz and demonstrated 106 MHz operation at VDD = 1.66 V, 125 dc (based on typical
process models). Additionally, 149 MHz at VDD = 2.13 V, 125 dc was demonstrated with the typical
model and 123 MHz using the slow model. This is a relatively small deviation induced by changes in
process parameters such as width reduction of the transistors. By using the fast model, operation at 294
MHz was demonstrated without any timing problems. This means the new ROM has very high produc-
tivity with even three sigma of process deviation and a wide range of voltages and temperatures.

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References

1. Karls, J.,

Status 1999: A Report on the Integrated Circuit Industry

, Integrated Circuit Engineering
Corporation, 1999.
2. Gulak, P. G., A Review of Multiple-Valued Memory Technology,

IEEE International Symposium on
Multi-valued Logic

, 1998.
3. Rich, D. A., A Survey of Multi Valued Memories,

IEEE Trans. on Comput.

, vol. C-35, no. 2, pp.
99106, Feb. 1986.
4. Prince, B.,

Semiconductor Memories

, 2nd ed., John Wiley & Sons Ltd., New York, 1991.
5. Takahashi, H., Muramatsu, S., and Itoigawa, M., A New Contact Programming ROM Architecture
for Digital Signal Processor,

Symposium on VLSI Circuits,

1998.

TABLE 2.1

Comparison of ROM Performance

Comparison Item Diffusion ROM Conventional VIA-2 ROM New VIA-2 ROM
8KW (Area ratio) 1.0 1.2 1.04
TAT (Day ratio) 1.0 0.2 0.2
Speed @ 2.13 V,
83 MHz 86 MHz 123 MHz
125 dc. Weak.
Speed @ 2.13 V,
166 MHz 98M Hz 149 MHz
125 dc. Typical.
Speed @ 2.81 V,
277 MHz 179 MHz 294 MHz
40 dc. Strong.
Speed @ 1.66 V.
103 MHz 75 MHz 106 MHz
125 dc. Typical.
Power @ 2.81 V,40dc.
15.6 mW 19.3 mW 2 UrnW Strong. 100 MHz.
(16-bit single access)
Power @ 2.81 V @ 40 dc.
29.6 mW 37.1 mW 401 mW Strong. 100 MHz.
(32-bit dual access)

Performance was measured with worst coding (all coding 1 ).

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