MIT3042-Embedded Systems

1. What are the various categories of embedded systems E!"#ai$

%$s& Embedded Systems are categorized into the following types:
1. Stand-alone embedded systems
2. Real-time embedded systems
3. Networed embedded systems
Stand-alone embedded systems: !t wors alone itself. "he entertainment de#ices of #ideo game
console$ mp3$ digital camera$ and microwa#e are s%ch typical systems that fall into this category.
Real-time embedded systems: & system is said to be real-time if the response time is critical.
Some partic%lar wor m%st be done in a specified time period. !n addition to f%nctional
correctness$ the time constraint m%st be satisfied.
a' 'ard rea#-time systems: (or a hard or immediate real-time system$ the completion of an
operation after its deadline may lead to a critical fail%re and res%lt in life$ loss and property
damage. E)ample: & car airbag control system is a hard real-time system beca%se a delayed
reaction may ca%se dri#er*s life and the delay response in heart pacemaers will also lead to a
se#ere res%lt.
b' Soft rea#-time system: !n some other embedded system$ there is response deadline b%t the
lateness can be tolerated to some degrees. "he #iolation of time constraints will res%lt in
degraded +%ality$ b%t the system can contin%e to operate. ,icrowa#e and washing machine
fall into this s%b-category.
Networed embedded systems: "he networed embedded systems are connected to networ with
networ interfaces to be accessed or to access other reso%rces. "he connected networ can be
-ocal &rea Networ .-&N'$ /ide &rea Networ ./&N'$ or !nternet. "he connection can be
wired or wireless. & home sec%rity system is an e)ample of -&N networed embedded system
where all sensors are wired and r%nning on the "012!1 protocol. & home Sec%rity system can be
integrated into a web based sec%rity system with additional web camera r%nning on 3""1
protocol.
2. What is a microco$tro##er (ist the si#e$t features of )0*1 microco$tro##er.
%$s& & microcontroller is an integrated chip that has processor$ memory and se#eral other
hardware %nits in it. "hese form the microcomp%ter part of the embedded system.
,icrocontrollers are %s%ally dedicated de#ices embedded within an application. (or e)ample$
microcontrollers are %sed as engine controllers in a%tomobiles and foc%s controllers in cameras.
!n order to ser#e these applications$ they ha#e a high concentration of on-chip facilities s%ch as
serial ports$ parallel inp%t o%tp%t ports$ timers$ co%nters4 interr%pt control$ analog-to-digital
con#erters$ random access memory$ read only memory$ etc. "he !25$ memory$ and on-chip
peripherals of a microcontroller are selected depending on the specifics of the target application.
Embedded control applications also disting%ish the microcontroller from its relati#e$ the general-
p%rpose microprocessor. Embedded systems often re+%ire real-time operation and m%ltitasing
capabilities. Real-time operation refers to the fact that the embedded controller m%st be able to
recei#e and process the signals from its en#ironment as they are recei#ed.
"he silent feat%res of 6781 microprocessor are:
a' 9 :; on chip program memory.
b' 126 bytes on chip data memory .R&,'.
c' 9 register bans.
d' 126 %ser defined software flags.
e' 6-bit data b%s
f' 1<-bit address b%s
g' 32 general p%rpose registers each of 6 bits
h' 1< bit timers .%s%ally 2$ b%t may ha#e more$ or less'.
i' 3 internal and 2 e)ternal interr%pts.
=' ;it as well as byte addressable R&, area of 1< bytes.
' (o%r 6-bit ports$ .short models ha#e two 6-bit ports'.
l' 1<-bit program co%nter and data pointer.
m' 1 ,icrosecond instr%ction cycle with 12 ,3z 0rystal.
3. (ist the various ty"es of addressi$g modes i$ )0*1 a$d e!"#ai$ a$y three.
%$s& "he #ario%s ways of accessing data are called addressing modes.
"he #ario%s addressing modes of 6781 are as follows:
a' !mmediate &ddressing ,ode
b' Register &ddressing ,ode
c' >irect &ddressing ,ode
d' Register indirect &ddressing ,ode
e' !nde)ed &ddressing ,ode
f' Relati#e &ddressing
g' &bsol%te addressing
h' -ong &ddressing
ALU
PSW
A B
PC
DPT
R
DPH
SFR and
General
Purpose
RAM
ROM
Port
0
Port
1
Port
2
Port

!"O
!#T
C#TR
S$R!AL
RD"WR
!"O
A%&A1'
!"O
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A0&A(
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!mmediate addressing mode: !n this mode$ the operand comes immediately after the opcode.
3ere the immediate data m%st be preceded by the sign$ ?@A. "his addressing mode can be %sed to
load information into any of the registers$ incl%ding the >1"R register.
& >1"R which is a 1<-bit register can also be accessed as two 6-bit registers$ >13 and >1-$
where >13 is the high byte and >1- is the low byte. "he following e)ample clarifies this
concept
EB&,1-E:
,5C &$ @2834 load 283 into &
,5C R9$ @<24 load the decimal #al%e <2 into R9
,5C ;$ @9734 load 973 into ;
,5C >1"R$ @982134 >1"RD98123
!f the #al%e is larger than 1< bits$ then instr%ctions wo%ld prod%ce an error. "his is clear from the
following e)ample.
,5C >1"R$ @<6EF84 illegalGG Cal%e H <8838 .(((((3'
Io% can also %se immediate addressing mode to send data to 6781 ports. (or e)ample: ?,5C 1!$
@<F3A is a #alid instr%ction.
Register addressing mode: !n this mode$ the registers are %sed to hold the data to be manip%lated.
5ne of the registers R7 to RF can be specified as the instr%ction operand. !n assembly lang%age
doc%mentation$ a register is generically represented as Rn where n #al%e may from 7 to F.
E)ample of instr%ctions %sing Rn:
,5C R2$ &4 0opy the contents of & into R2
,5C &$ R74 0opy the contents of R7 into &.
&>> &$ R84 &dd the contents of R8 to contents of &
!t is important to remember that the so%rce and destination registers m%st match in size. (or
e)ample$ coding ?,5C >1"R$ &A will gi#e an error$ beca%se the so%rce is an 6-bit register and
the destination is a 1<-bit register. See the following e)ample.
,5C >1"R$ @28(83
,5C RF$ >1-
,5C R<$ >13
Notice that we can mo#e data between the acc%m%lator and Rn .for n 7 to F'$ b%t mo#ement
of data between registers is not allowed. (or e)ample$ the instr%ction ?,5C R9$ RFJ is in#alid.
Relati#e &ddressing: "his is a special addressing mode %sed with certain =%mp instr%ctions. "he
relati#e address$ often referred to as an offset$ is an 6-bit signed n%mber$ which is a%tomatically
added to the 10 .1rogram 0o%nter' to mae the address of the ne)t instr%ction. "he 6-bit signed
offset #al%e gi#es an address range of K12F to -126 locations. &n ad#antage of relati#ssse
addressing is that the program code is easy to relocate in memory in that the addressing is
relati#e to the position in memory.
4. What are the +T,S -er$e# com"o$e$ts E!"#ai$
&ns: Real-"ime 5perating System .R"5S' is a m%ltitasing operating system intended for real-
time applications. & real-time operating system .R"5S' is a type of operating system designed to
s%pport real-time programs.
,ost R"5S ernels contain the following components:
Schedu#er is contained within each ernel and follows a set of algorithms that determines
which tas e)ec%tes when. Some common e)amples of sched%ling algorithms incl%de ro%nd-
robin and preempti#e sched%ling.
,b.ects are special ernel constr%cts that help de#elopers create applications for real time
embedded systems. 0ommon ernel ob=ects incl%de tass$ semaphores$ and message +%e%es.
Services are operations that the ernel performs on an ob=ect or$ generally operations s%ch as
timing$ interr%pt handling$ and reso%rce management.
The Schedu#er& !t is at the heart of e#ery ernel. "he sched%ler is responsible for e)ec%ting
tass in accordance with a sched%ling mechanism. & sched%ler pro#ides the algorithms needed to
determine which tas e)ec%tes when.
"o %nderstand how sched%ling wors:
Sched%lable entities
,%ltitasing
0onte)t switching
>ispatcher and
Sched%ling algorithms
Schedu#ab#e E$tities& !t is a ernel ob=ect that can compete for e)ec%tion time on a system$
based on a predefined sched%ling algorithm. "ass and processes are all e)amples of sched%lable
entities fo%nd in most ernels. & task is an independent thread of e)ec%tion that contains a
se+%ence of independently sched%lable instr%ctions. Some ernels pro#ide another type of a
sched%lable ob=ect called a process. 1rocesses are similar to tass in that they can independently
compete for 01L e)ec%tion time. 1rocesses differ from tass in that they pro#ide better memory
protection feat%res$ at the e)pense of performance and memory o#erhead. >espite these
differences$ for the sae of simplicity$ we %se tas to mean either a tas or a process. ,essage
+%e%es and semaphores are not sched%lable entities. "hese items are intertas comm%nication
ob=ects %sed for synchronization and comm%nication. & sched%ler handles m%ltiple sched%lable
entities that need to r%n sim%ltaneo%sly by m%ltitasing.
Mu#titas-i$g& !t is the ability of the operating system to handle m%ltiple acti#ities within set
deadlines. & real-time ernel might ha#e m%ltiple tass that it has to sched%le to r%n. !n this
scenario$ the ernel m%ltitass in s%ch a way that many threads of e)ec%tion appear to be r%nning
conc%rrently4 howe#er$ the ernel is act%ally interlea#ing e)ec%tions se+%entially$ based on a
preset sched%ling algorithm. "he sched%ler m%st ens%re that the appropriate tas r%ns at the right
time. &n important point to note here is that the tass follow the ernel*s sched%ling algorithm$
while interr%pt ser#ice ro%tines .!SR' are triggered to r%n beca%se of hardware interr%pts and
their established priorities. &s the n%mber of tass to sched%le increases$ so do 01L performance
re+%irements. "his is d%e to increased switching between the conte)ts of the different threads of
e)ec%tion.
The /o$te!t S0itch& Each tas has its own conte)t$ which is the state of the 01L registers
re+%ired each time it is sched%led to r%n. & conte)t switch occ%rs when the sched%ler switches
from one tas to another. "o better %nderstand what happens d%ring a conte)t switch$ let*s
e)amine f%rther what a typical ernel does in this scenario.
E#ery time a new tas is created$ the ernel also creates and maintains an associated "as
0ontrol ;loc ."0;'. "0;s are system data str%ct%res that the ernel %ses to maintain tas
specific information. "0;s contain e#erything a ernel needs to now abo%t a partic%lar tas.
/hen a tas is r%nning$ its conte)t is highly dynamic. "his dynamic conte)t is maintained in the
"0;. /hen the tas is not r%nning$ its conte)t is frozen within the "0;$ to be restored the ne)t
time the tas r%ns. /hen the ernel*s sched%ler determines that it needs to stop r%nning tas 1
and start r%nning tas 2$ it taes the following steps:
1. "he ernel sa#es tas 1*s conte)t information in its "0;.
2. !t loads tas 2*s conte)t information from its "0;$ which becomes the c%rrent thread of
e)ec%tion.
3. "he conte)t of tas 1 is frozen while tas 2 e)ec%tes$ b%t if the sched%ler needs to r%n tas 1
again$ tas 1 contin%es from where it left off =%st before the conte)t switch.
"he time it taes for the sched%ler to switch from one tas to another is the conte)t switch time.
!f an application*s design incl%des fre+%ent conte)t switching$ howe#er$ the application can inc%r
%nnecessary performance o#erhead. "herefore$ design applications in a way that does not in#ol#e
e)cess conte)t switching.
E#ery time an application maes a system call$ the sched%ler has an opport%nity to determine if it
needs to switch conte)ts. /hen the sched%ler determines a conte)t switch is necessary$ it relies
on an associated mod%le$ called the dispatcher$ to mae that switch happen.
The 1is"atcher& "he dispatcher is the part of the sched%ler that performs conte)t switching and
changes the flow of e)ec%tion. &t any time an R"5S is r%nning$ the flow of e)ec%tion$ also
nown as flow of control$ is passing thro%gh one of three areas: thro%gh an application tas$
thro%gh an !SR$ or thro%gh the ernel. /hen a tas or !SR maes a system call$ the flow of
control passes to the ernel to e)ec%te one of the system ro%tines pro#ided by the ernel. /hen it
is time to lea#e the ernel$ the dispatcher is responsible for passing control to one of the tass in
the %ser*s application. !t will not necessarily be the same tas that made the system call. !t is the
sched%ling algorithms of the sched%ler that determines which tas e)ec%tes ne)t. !t is the
dispatcher that does the act%al wor of conte)t switching and passing e)ec%tion control.
>ispatching can happen differently depending on how the ernel is first entered. /hen a tas
maes system calls$ the dispatcher is %sed to e)it the ernel after e#ery system call completes. !n
this case$ the dispatcher is %sed on a call-by-call basis so that it can coordinate tas-state
transitions that any of the system calls might ha#e ca%sed. 5n the other hand$ if an !SR maes
system calls$ the dispatcher is bypassed %ntil the !SR f%lly completes its e)ec%tion. "his process
is tr%e e#en if some reso%rces ha#e been freed that wo%ld normally trigger a conte)t switch
between tass. "hese conte)t switches do not tae place beca%se the !SR m%st complete witho%t
being interr%pted by tass. &fter the !SR completes e)ec%tion$ the ernel e)its thro%gh the
dispatcher so that it can then dispatch the correct tas.
Schedu#i$g %#gorithms& "he sched%ler determines which tas r%ns by following a sched%ling
algorithm. ,ost ernels today s%pport two common sched%ling algorithms:
1reempti#e priority-based sched%ling$ and
Ro%nd-robin sched%ling.
*. What are the fu$ctio$s that i$terru"t a$d eve$t ha$d#i$g mecha$ism of a$ +T,S
"rovide
%$s&