FLIP-FLOP IMPLEMENTATION

1. BASIC RS FLIP FLOP (Asynchronous Sequent!" Lo#c$

The above flip flop is used in asynchronous sequential circuits. The outputs of any
combinational control logic, that drives the R and S inputs, must be glitch free. (eg.
Lift Sets must be used to cover adjacent loops in the Karnaugh aps!
%. CLOC&E' FLIP-FLOPS (Synchronous Seqent!".Lo#c$
These circuits use a cloc" input in such a manner that there is no continuous path
through the flip#flops at any time. The flip#flop inputs are disabled $hen their outputs
change so that any glitches fed bac" into the inputs don%t have any effect.
%.1 RS F"( F"o( )th En!*"e In(ut
&n enable line can be used to turn off the path through the flip#flops $hen the enable
is lo$, as indicated belo$.
'
'
R
S
Set ( S or )reset, Reset ( R or *lear
(*$ RS )th Preset !n+ C"e!r In(uts
'
'
R
S
)reset
*lear
(!$ RS F"(-,"o(
S
R
'
'
*lear
)reset
R + S ,nputs to -lip#-lops
(must be glitch#free!
Asynchronous Sequent!" "o#c Crcut usn# Non C"oc-e+ F"(-F"o(s
*ombinational Logic
,nputs
-lip#-lop .utputs
(State /ariables!
This path is continually open,
so logic must be glitch free
RS -lip#-lops
( non#cloc"ed!
.utputs
,nputs
0nable
'
R
S
S1 ( S and 0nable
R1 ( R and 0nable
S1
R1
'
'
*lear
)reset )reset
S
R
'
'
*lear
0nable
RS )th Preset. C"e!r !n+ En!*"e In(uts
path
no path
,n this case the path through the 1 2and gates is only opened then the enable line is at
logic 3. 4o$ever, there $ould still be a continuous unbro"en loop around the circuit
$hen the enable $as true. Thus any combinational logic producing the R and S
inputs $ould still have to be glitch#free as indicated belo$.
%.% RS M!ster-S"!/e F"( F"o( )th C"oc- In(ut
.ne $ay of ensuring that there is never a continuous path through the flip#flop is to
use 1 flip#flops in series. The input flip#flop is the M!ster and the output flip#flop is
the S"!/e as indicated belo$.
2ote the asynchronous Preset and C"e!r inputs are inputs to the S"!/e flip#flop, and
override the effect of the M!ster. Thus $hen a *lear is applied to the Slave, the RS
inputs (and the cloc"! have no effect on the output '%s, since the Slave is held in the
.-- mode via its *lear input.
5litches no$ have no effect on the ' outputs, as indicated belo$
RS F"(-F"o(s
($ith enable input!
R + S ,nputs to -lip#-lops
(must be glitch#free!
Sequent!" "o#c Crcut usn# F"(-F"o(s )th En!*"e
Co0*n!ton!" Lo#c ,nputs .utputs
-lip#-lop .utputs
(State /ariables!
This path is open $hen enable is true,
so logic must still be glitch free
0nable
.pen
*losed
0nable
R
S
MASTER
Sm
Rm
'm
'm
O(en M!ster
(R,S (6 aster!
)reset
S
R
'
'
*lear
*loc"
C"oc-e+ M!ster-S"!/e F"( F"o(
1s ch!n#es !t ths (ont )hen M!ster 23 S"!/e
(&ny glitches at R,S inputs are ignored by the aster!
C"oc-
path
SLA4E
Ss
Rs
's
's
*loc"
)reset
*lear
O(en S"!/e
(aster (6 Slave!
O(en S"!/e
(Transfer to S!
O(en M!ster
(set up aster!
%.5 RS F"( F"o( )th E+#e Tr##ere+ C"oc- In(ut
&nother $ay of ensuring that there is never a continuous path through the flip#flop is
to use a single flip flop and only open its input circuit for a very short time (eg.
37nSecs!. Thus by the time its outputs change state (and possibly produce glitches!
the input gates are closed, so the glitches have no effect.
2ote the asynchronous Preset and C"e!r inputs again override the effect of any RS
inputs and cloc".
C"oc-e+ RS F"(-F"o(s
,nputs to -lip#-lops
(glitches .K!
Sequent!" "o#c Crcut usn# C"oc-e+ F"(-F"o(s
Co0*n!ton!" Lo#c ,nputs .utputs
-lip#-lop .utputs
(State /ariables!
This path is ne/er fully open
(so all glitches are neglected by --%s!
*loc"
asters Slaves
S
)reset
S
R
'
'
*lear
*loc"
16s ch!n#es !t ths (ont )hen ! short +e"!y !,ter C"oc- #oes 7 -3 1
(&ny glitches at R,S inputs are ignored by the flip#flop!
C"oc-
path
B!sc
F"(-F"o(
S
R
's
's
*loc"
)reset
*lear
S
R
*loc"
E+#e 'etector
C"oc-e+. E+#e Tr##ere+ F"(-F"o(
En!*"e
En!*"e
"oc-
path
1 Out(ut
(e8ample!
C"oc-
path
5. CLOC&E' FLIP-FLOP T8PES
5.1 '-Ty(e
& 9#type flip flop is a cloc"ed RS flip#flop (either edge triggered or aster:Slave!
$ith an input inverter as sho$n belo$.
5.1 9&-Ty(e
& ;K flip flop is a cloc"ed RS flip#flop (either edge triggered or aster:Slave! $ith
input gating and additional feedbac" as indicated belo$.
2ote< The t$o &29 gates are usually incorporated into the input gating of the basic
cloc"ed RS flip#flop
5.1 T-Ty(e
& T#type flip flop is essentially a cloc"ed ;K flip#flop (either edge triggered or
aster:Slave! $ith both the ; and K inputs tied together to form the T input, as
indicated belo$.
)reset
9 '
'
*lear
*loc"
9
)reset
S
R
'
'
*lear
*loc"
)reset
; '
'
*lear
*loc"
)reset
S
R
'
'
*lear
*loc"
;
K
K
)reset
T '
'
*lear
*loc"
T
)reset
;
K
'
'
*lear
*loc"