Chapter 6: Power Amplifiers and Output Stages: Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

Microelectronics: Analysis and Design January 9, 2003 Sundaram Natarajan
479
CHAPTER 6: POWER AMPLIFIERS AND OUTPUT STAGES
6.0: INTRODUCTION
The analysis and design of small-signal amplifiers were discussed so far. These amplifiers operate
in the linear range, and the output will normally be undistorted. The operation of the transistors is confined
to the active mode. This permitted the use of small-signal models to analyze these circuits. Such small-signal
amplifiers have inherently low power output capability and are not expected to drive low impedance loads
such as speakers and motor drives.
Requirements of Power Amplifiers
In this chapter, we consider power amplifiers. Both discrete and IC power amplifiers will be
examined. These amplifiers usually constitute the output stages in a multistage amplifier. There are some
specific requirements of such amplifiers. Some important ones are:
1. Power amplifiers must have low output impedance so they can drive low impedance loads with no
reduction in the voltage gain.
2. Power amplifiers must deliver a large amount of power while dissipating only a low amount of power
internally; i.e., they must have a high power efficiency. There are two important reasons for this:
(a) While the amplifier is expected to deliver a specific amount of output (load) power, the input
power to the amplifier comes essentially from the dc power supply (Section 1.4) Therefore,
if the amplifier is inefficient, there will be a large drain on the power supply.
(b) The difference between the battery power and the power delivered to the load must be
dissipated by the transistors. If the amplifier is inefficient, the power dissipation ratings of
the transistors must be higher, and large size heat sinks will be required to prevent any
damage to the transistors. High power transistors are expensive, and the size and cost of the
amplifier will escalate.
These reasons clearly suggest the importance of efficiency.
3. Power amplifiers handle large voltage and current signals since they are the final stages of multi-
stage amplifiers. Therefore, the distortion of the output signal is also an important consideration.
These amplifiers should deliver power to a specific load with acceptably low levels of distortion. A
measure of the distortion in the output signal is the total harmonic distortion (THD). In a good power
amplifier, THD should be less than 0.1 %.
4. Since the power amplifiers handle large signals, the small-signal approximations are not generally

1
Sinusoidal signals are used to study and assess the properties of many electrical and electronic circuits. The
properties of the power amplifiers are studied using a single frequency sinusoidal signal. Therefore, unless otherwise
specified, both input and output signals will be sinusoidal throughout this chapter.
480
valid in the analysis of power amplifiers. Instantaneous values of the signals should be used instead.
However, as mentioned earlier, we cannot accept large distortion either. Therefore, linearity is also
an important consideration in power amplifiers.
In this chapter, we first consider the classification of power amplifiers using the signal-swing
considerations. Then, power amplifiers under the different classifications starting with the simplest
configuration of the emitter follower circuit are discussed. Thermal considerations due to the power
dissipation in the transistors are included. Also examined are short-circuit protection and current-limiting
features. We conclude the chapter with a discussion on power MOSFETs.
6.1: CLASSIFICATION OF POWER AMPLIFIERS
Power amplifiers are classified according to the waveform of the collector current (drain current if
FETs are used). They are Class-A, Class-AB, Class-B, and Class-C amplifiers. While the first three types of
amplifiers find wide use in the audio power applications, the Class-C operation is usually employed in the
RF (radio frequency) power amplifiers. In this chapter, we focus on the first three categories only.
In the Class-A operation, the BJT is biased with a dc bias current I
CQ
so the instantaneous value of
the collector current never becomes zero. The waveform of the collector current under the Class-A operation
is shown in Fig. 6.1.1(a) using a sinusoidal signal
1
as an example. The transistor conducts during the entire
cycle, and the collector current never goes to zero. This is like any other small-signal amplifier addressed in
the earlier chapters. All small-signal linear amplifiers belong to the Class-A category. Therefore, in a Class-A
power amplifier, the distortion will be the least. The value of I
CQ
is typically chosen to be equal to half the
maximum expected value of the collector current. This provides the maximum symmetrical signal-swing and
maximum efficiency in this category.
In the Class-B operation, the transistor is biased to operate with a zero bias current; i.e., I
CQ
= 0. With
sinusoidal inputs, the collector current exists during either the positive or negative half cycles only. Therefore,
the waveform of the collector current of a npn transistor will be as shown in Fig. 6.1.1(b). With the same
input, a pnp transistor will conduct during the negative-half cycles of the input only. Since the input voltage
has to overcome the cut-in voltage of the base-emitter junction, the collector current will be distorted near
the zero crossings. This situation is exactly similar to what exists in a half-wave rectifier. If only one
transistor is used to amplify signals with Class-B operation, the output will be heavily distorted. Fortunately,
481
Fig. 6.1.1: Collector current waveforms of the npn transistors operating in (a) class-A,
(b) class-B, (c) class-AB, and (d) class-C power amplifiers.
(a)
I
m
i
C
(t)
I
CQ
0
2 3 4
t
(b)
i
C
(t)
0
2 3 4
t
I
m
(c)
i
C
(t)
0
2 3 4
t
I
m
I
CQ
(d)
i
C
(t)
0
2 3 4
t
both halves of the input signal can be amplified using the complementary symmetry (push-pull) arrangement.
With this arrangement, the power amplifier will be highly efficient because there is no dc power dissipation
under the quiescent conditions, i.e., with no input signal.
To avoid the distortion during the zero crossings, each transistor in the push-pull arrangement can
be biased with a small dc bias current so that the conduction angle is more than 180 as shown in Fig.
6.1.1(c). This is called the Class-AB operation because this operation is intermediate between the Class-A
and Class-B operations. Of course, the efficiency will reduce in comparison to the Class-B operation because
of the quiescent dc power dissipation but the distortion during the zero-crossings can be avoided. However,
in all types of power amplifiers, whether it is Class-A, -AB, -B, the distortion due to the transistor saturation
cannot be avoided. Therefore, the maximum signal-swing should be limited to the transistor saturation levels,
and we assume this to be the case throughout this chapter.
482
Fig. 6.2.1: (a) A class-A power amplifier with a constant-current source biasing, and (b) its
transfer characteristics.
+V
CC
Q
1
Q
3
+v
I
Q
2
I
REF
R
I
BIAS
i
E1
+v
O
i
L
R
L
+
-
v
BE1
-V
EE
v
BE1
v
I
v
O
V
CC
-V
CES1
-(V
EE
-V
CES2
)
-I
BIAS
R
L
In the Class-C operation, the transistor is biased to conduct for less than half a cycle as shown in Fig.
6.1.1(d). This type of operation is used in RF power amplifiers (in radio and TV transmitters), where
efficiency is required to be very high. The output waveform is almost pulsating. The output is fed to an LC
tank circuit, which essentially operates as a tuned amplifier (see Fig. 1.9.3) and selects the fundamental
component for further amplification. Although the Class-C amplifier is very efficient, it is only used in some
special applications where high power is delivered to the load. The analysis of the Class-C amplifier is tedious
and beyond the scope of this book.
6.2: CLASS-A POWER AMPLIFIERS
The simplest power amplifier is an emitter(or the source) follower. A Class-A power amplifier using
a constant-current source biasing, along with its transfer characteristic, has been reproduced here in Fig. 6.2.1
(see Fig. 3.6.9). Emitter- and source-followers have been analyzed in the earlier chapters for their small-signal
behavior. Now we consider their large-signal operation and power efficiency. This circuit may be used in a
discrete design also. To keep the analysis simple, it is assumed that 1 for the BJTs in this and future
sections.
Power Dissipation and Efficiency
A power amplifier is designed to deliver a specified maximum value of the average amount of power
to a given load. It is convenient to assume the output signal to be a sinusoid and develop all the equations in
terms of its amplitude. Thus, let

2
In calculating the total power drawn from the power supplies, we neglect the average power drawn from the
negative power supply by the bias resistance R. We discuss its influence soon.
483
v
O
( t ) V
m
sin t ,
(6.2.1)
v
CE1
V
CC
v
O
V
CC
V
m
sint , and i
C1
i
E1
I
BIAS
( V
m
/ R
L
) sin t .
(6.2.2)
p
D1
v
CE1
i
C1
V
CC
I
BIAS
( V
2
m
/ R
L
) sin
2
t ( V
CC
/ R
L
) I
BIAS
V
m
sint . (6.2.3)
p
D1
V
CC
I
BIAS
( V
2
m
/ R
L
) sin
2
t . (6.2.4)
P
D2
1
T
t T
t 0
( V
m
sint V
CC
) I
BIAS
dt V
CC
I
BIAS
.
(6.2.5)
P
D1
1
T
t T
t 0
V
CC
I
BIAS
V
2
m
R
L
sin
2
t dt V
CC
I
BIAS
V
2
m
2R
L
.
(6.2.6)
where V
m
V
CC
. Then, we find that
The input current from the signal source is very small in comparison to the collector currents of the
transistors. Therefore, in power calculations, the power input from the signal source is ignored, and the input
power to the circuit is assumed to be the power supplied by the power supplies only (see (1.4.1)). The power
dissipation in a transistor, also known as the collector-dissipation, is mainly due to the collector current (see
(1.4.2)). The instantaneous value of the power dissipation in Q
1
is
If V
CC
= I
BIAS
R
L
, the above equation reduces to
The maximum power dissipation equal to (V
CC
I
BIAS
) occurs in Q
1
at t = 0 or if V
m
is zero (there is no
signal). Therefore, Q
1
must be able to dissipate this power without any increase in its junction temperature.
However, if R
L
(when no load is connected to the amplifier), we find from (6.2.3) that the maximum
power dissipation can be as much as (V
CC
+ V
m
)I
BIAS
, when sin(t) = -1. Since such a special condition exists
only at specific instants of time and is not sustained, the design need not be this conservative; it is sufficient
if the transistor power dissipation rating is greater than (V
CC
I
BIAS
). Another possible extreme condition is R
L
= 0 (short-circuit). Under this condition, the transistor Q
1
may draw a large current, and consequently, its
junction temperature will start increasing. If this condition persists even for a small period, the transistor will
be damaged. Therefore, most power amplifiers are provided with a short-circuit protection (see Fig. 6.4.7).
The collector current of Q
2
has a constant value of I
BIAS
. Taking V
CC
= V
EE
, its maximum collector-
dissipation is [(V
CC
+ V
m
)I
BIAS
] and occurs when v
O
(t) reaches V
m
. This again is only an instantaneous
maximum but not the average. The average power dissipation in Q
2
is
The (average) power dissipation in Q
1
is
The power conversion efficiency is calculated as the percentage of the useful (average) power P
L
supplied to the load to the total power P
S
drawn from the dc sources (see (1.4.4)). We can find the latter
2
as
484
P
S
P
D1
P
D2
P
L
,
P
L
1
T
t T
t 0
V
2
m
sin
2
t
R
L
dt
V
2
m
2R
L
.
(6.2.7)
P
L
P
S
1
4
V
2
m
V
CC
I
BIAS
R
L
1
4
V
2
m
V
2
CC
.
(6.2.8)
R
Leff
a
2
R
L
,
(6.2.9)
v
O
( t ) V
m
sin t .
I
Cmax
( V
CC
aV
m
)
a
2
R
L
, and I
CQ
aV
m
a
2
R
L
V
m
aR
L
.
(6.2.10)
where
Therefore, P
S
= (2V
CC
I
BIAS
), and the efficiency is
The efficiency is maximum if V
m
= V
CC
, and the maximum attainable efficiency is only 25%. Since
the biasing resistor R also draws a current approximately equal to I from the negative power supply, we have
to add another (V
CC
I
BIAS
) to P
S
. If so, the maximum power efficiency will only be 16.7%, when this biasing
scheme is used. If the amplitude V
m
of the output signal is close to the value of V
CC
, considerable distortion
of the output can occur due to saturation of the transistors. Therefore, the value of V
m
should be less than V
CC
.
Then, the efficiency will be even lower than 16.7% in this circuit.
A Transformer coupled Class-A Power Amplifier
In the audio power applications, one uses mostly a single power supply scheme, and the load
resistance is capacitively coupled to the emitter follower (see Fig. 3.8.5). However, with the use of a
transformer coupling, the maximum efficiency can be increased to almost 50%. The emitter follower circuit
with a transformer coupling and its load lines are shown in Fig. 6.2.2. The transformer can also serve the
purpose of providing impedance matching between the load and the output resistance of the amplifier, which
is an added advantage. This helps to transfer maximum power to the load.
The resistance of the transformer primary coil is negligible and is almost a short-circuit for dc.
Therefore, the dc load line will be almost vertical. However, for sinusoidal signals, the effective resistance
on the primary side is
where a is the turns-ratio (n
1
/n
2
). Therefore, the slope of the ac load line will be (-1/R
Leff
). Let the output
voltage be
Then, the sinusoidal signal across the collector-emitter terminals will have an amplitude of (aV
m
) around V
CC
.
The maximum and dc bias values of the collector current are
485
V
CC
aV
m
, and I
CQ
I
Cmax
2
V
CC
a
2
R
L
.
(6.2.11)
P
S
V
CC
I
CQ
V
2
CC
a
2
R
L
.
(6.2.12)
P
L
P
S
1
2
a
2
V
2
m
V
2
CC
.
(6.2.13)
P
D
( V
CC
I
CQ
/ 2 ).
P
D
V
CC
I
CQ
.
Fig. 6.2.2: (a) A transformer-coupled power amplifier and (b) its load lines.
(a)
Q
R
B1
R
B2
+v
I

i
E
i
L
n
1
:n
2
+v
O
+V
CC
R
L
(b)
V
CC
V
CC
+ aV
m
v
CE
I
CQ
I
Cmax
dc load line,
slope
i
C
0
ac load line,
slope =
-1
R
Leff
To obtain the maximum symmetrical signal-swing, I
CQ
must bisect the ac load line (see Fig. 3.8.3); i.e., the
following conditions must be fulfilled:
The average current drawn from the power supply is I
CQ
. Therefore,
(6.2.7) gives the load power in this circuit also. Therefore, the efficiency is
Since V
m
(V
CC
/a), the maximum attainable efficiency is 50%. In this calculation, the power dissipation in
R
B1
and R
B2
has been ignored. Therefore, the actual efficiency will be lower than 50%. However, in
comparison to the previous Class-A amplifier, the efficiency has doubled for the same supply voltage and the
amplitude of the output signal.
If V
m
= (V
CC
/a), the collector-dissipation is equal to the power dissipation in the load because the
efficiency is 50%. The average power dissipation in the BJT is then
However, with no input signal, the maximum average collector-dissipation is
Therefore, transistor power dissipation rating should exceed twice the maximum power dissipation in the
load; i.e.,
486
P
D
2P
Lmax
,
(6.2.14)
V
m
2P
L
R
L
4 V .
I
CQ
V
CC
a
2
R
L
12
94
1
3
A .
2
4 0.403
45.4 %.
where P
Lmax
occurs for V
m
= (V
CC
/a).
Example 6.1 (Design)
Using the circuit of 6.2.2, design a power amplifier to supply a maximum load power of 2 W to a 4-
load. Assume that V
CC
= 12 V.
SOLUTION
Using (6.2.9),
For maximum efficiency, the transformer turns-ratio is Next, using (6.2.11), we find that a ( V
CC
/ V
m
) 3.
The current rating of the transistor should exceed 2I
CQ
= (2/3) A, and its power rating should exceed (V
CC
I
CQ
)
= 4 W. The maximum signal-swing across the collector-emitter terminals is (2V
CC
), which is 24 V. Since we
need a relatively low current device, a general purpose transistor such as 2N2270 may be used in this circuit.
It has V
CEO
= 45 V, and I
Cmax
= 1 A. Usually, a general purpose transistor cannot be used in power applications
without a heat sink. With a heat sink provided, the maximum power dissipation rating for this transistor is
5 W. Thus, the power dissipation rating is also satisfied.
The typical value of the base-emitter voltage is about 0.88 V at I
C
= 150 mA, and h
FE
= 135 at this
current for this transistor. Therefore, we use the same value in this design, although we require (1/3) A.
Allowing (I
CQ
/10) through R
B2
, since the dc voltage drop across R
B2
should be 0.88 V, a standard value of
may be selected. The current through R
B1
should be (I
B
+ I
CQ
/10) = 35.8 mA, and the voltage R
B2
27
drop across R
B1
should be about 11.12 V. Therefore, R
B1
should be 310.6 . We select a standard resistance
of R
B1
330 .
Let us calculate the efficiency of this design including the power dissipation in R
B1
and R
B2
. The total
power dissipated in these two resistors is about 403 mW. Then, including this power dissipation, the
efficiency is
487
T
Jmax
T
C

JC
P
D
,
(6.2.15)
Fig. 6.2.3: The typical power derating characteristic of a transistor.
P
D
P
Dmax
0
T
CO
T
Jmax
T
C
slope =
-1
JC
Power Dissipation and Thermal considerations
The power dissipated in a transistor generates heat and causes an increase in its collector-base
junction temperature. In an improper design, the temperature increase may damage the transistor permanently.
Therefore, the designer should choose a power transistor with appropriate power rating and should also
consider the details of the heat sink that may be necessary for a given application. Let us now address the
effect of the power dissipation on the junction temperature.
The junction temperature of a transistor should be kept below the maximum allowable junction
temperature T
Jmax
. For silicon transistors, the value of T
Jmax
is about 150 to 200 C, and the manufacturers
usually specify this value. The heat is transmitted from the junction to the case and then to the environment.
Unless this heat is taken away from the case as fast as it reaches, the case temperature and the temperature
at the environment will also increase. If so, for a given amount of power dissipation, the junction temperature
increases. The ambient temperature decides how fast the heat can be transferred away from the case, and
therefore, how much power can be dissipated in a transistor.
The manufacturers usually provide the maximum power dissipation and the power derating curve,
similar to the one shown in Fig. 6.2.3, for a transistor. In this plot, T
C
is the case temperature, and T
CO
is
typically about 25 C. The value of T
Jmax
can be read from the point where the curve (a straight line) cuts the
temperature axis; i.e., if T
C
= T
Jmax
, the transistor cannot transfer any heat from the junction to the case and
hence cannot dissipate any power. Nonzero power dissipation is possible, only if T
C
< T
Jmax
. For T
C
< T
jmax
,
we can find the maximum permissible power dissipation level of the transistor at a specified case temperature
T
C
from this curve. The manufacturers also give the slope of this curve, known as the power derating factor,
the unit of which is W/ C. The linear portion of the power derating curve can be described by
where P
D
is the permitted power dissipation at a case temperature T
C
and
JC
is called the thermal resistance
expressed in C/W. The value of the thermal resistance value can be computed from the inverse of the slope
488
T
Jmax
T
A
(
JC

CS

SA
) P
D

JA
P
D
,
(6.2.16)
P
D
( T
Jmax
T
C
)
JC
100
0.875
114.3 W.
T
J
T
C
0.875100 157.5 C.
of derating characteristic. Usually, the manufacturers provide the thermal resistance
JC
from the junction to
the case. Sometimes, they also provide the value of
JA
, which is the thermal resistance from the junction to
the ambient without any heat sink added. With a heat sink, one has to take the thermal resistance of the heat
sink also into account. Including all the effects, we can write that
where
CS
is the thermal resistance from the case to the heat sink, and
SA
is the thermal resistance of the heat
sink to the ambient. Without a heat sink,
JA
=
JC
+
CA
. It should be noted that the thermal resistance from
the case to the ambient without a heat sink would be much greater than the effective thermal resistance (
CS
+
SA
) with a heat sink. Hence the need is for a heat sink.
Example 6.2
A 200-W power transistor is operated at a case temperature of 100 C with no heat sink. Its maximum
allowable junction temperature is 200 C and
JC
= 0.875 C/W. (a) Find the maximum allowed power
dissipation. (b) If T
C
= 70 C, and the transistor dissipates 100 W, find the junction temperature.
SOLUTION
(a) Using the values of
JC
in (6.2.15),
Obviously, the maximum power dissipation should not exceed 114.3 W, although its maximum power rating
of the transistor is 200 W.
(b) Using (6.2.15) again, we find that
Although the thermal resistance from the junction to the case is typically small, the thermal resistance
from the junction to the ambient
JA
is usually high with a typical value of 60 C/W. Assume that a transistor
has a maximum power rating of 60 W,
JA
= 60 C/W, and T
Jmax
= 150 C. If it is to be operated at a room
temperature of 25 C, the transistor can only dissipate 2.1 W.
A 200-W power transistor has T
Jmax
= 200 C and
JC
= 0.875 C/W. It has a typical value of
CS
=
489
JC

CS

SA
( T
Jmax
T
A
)
P
D
200 25
50
3.5 C/ W.
SA
3.5 / W 0.875 C/ W 1 C/ W 1.625 C/ W.
1 C/W. It is operated with a heat sink. If the transistor power dissipation is 50 W and the ambient temperature
is 25 C, what can be the maximum value of the thermal resistance of the heat sink to the ambient?
SOLUTION
Using (6.2.16), we find that
Substituting the values for
JC
= 0.875 C/W and
CS
= 1 C/W, the thermal resistance of the heat sink should
be limited to
Therefore, any heat-sink with a thermal resistance less than 1.625 C/W is acceptable.
6.3: CLASS-B POWER AMPLIFIERS
A maximum efficiency of 50% is obtained in a transformer-coupled Class-A power amplifier. This
circuit configuration, however, cannot be realized in an IC because of the presence of the transformer. The
efficiency can be improved considerably with Class-B operation both in IC and discrete circuits. Virtually,
in all practical applications, either the Class-B or its modification, Class-AB operation, is used.
A Class-B Power Amplifier using a Complementary pair of BJTs
The basic Class-B circuit, using a complementary pair of npn and pnp transistors, is shown in Fig.
6.3.1(a). This circuit is essentially a combination of two emitter follower circuits. If v
I
is zero, both Q
1
and
Q
2
do not conduct, and i
L
= v
O
= 0. We can prove this using the contradiction principle. Assume that v
I
= 0
and Q
1
conducts. If so, i
L
> 0 and v
O
> 0. If v
I
= 0 and v
O
> 0, v
BE1
< 0. For Q
1
to conduct, v
BE
must be positive
because it is an npn transistor. This contradicts our original assumption. Using a similar argument, it can be
proven that, if v
I
= 0, the pnp transistor does not conduct either. Since both transistors do not conduct, v
O
0.
Circuit Operation
Each transistor operates in the Class-B mode and conducts during alternate half cycles of the input
signal. At the output, the half cycles are combined to obtain the replica of the input signal. During the positive
half cycle, the npn transistor pushes the current i
E1
into the load, and the pnp transistor pulls the current i
E2
from the load during the negative half-cycle. Therefore, another name for this amplifier is the push-pull
amplifier. Q
1
and Q
2
operate as emitter followers during the positive and negative half cycles respectively.
If v
I
goes positive, Q
1
conducts for v
I
V
, whereas Q
2
does not. If Q
1
conducts, the load draws current from
490
v
O
v
I
V
, v
I
V
.
(6.3.1)
P
L
( V
2
m
/ 2R
L
) . (6.3.2)
I
C1
1
T
t T/ 2
t 0
( V
m
/ R
L
) sin ( t ) dt V
m
/ ( R
L
) .
(6.3.3)
I
C2
V
m
/ ( R
L
) .
(6.3.4)
Fig. 6.3.1: A class-B power amplifier and its transfer characteristic.
(a)
i
E2
R
L
i
L
i
E1
Q
1
+V
CC
-V
CC
+v
O
+v
I
Q
2
+
-
v
BE1
+
-
v
BE2
(b)
v
O
V
-V
v
I
V
CC
-V
CC
the positive power supply, and v
O
increases positively. Thus, during the positive cycle of v
I
,
v
O
can only reach a maximum value of V
CC
because the transistor Q
1
will saturate for a sufficiently large
positive input. If v
I
goes negative, Q
2
conducts and Q
1
does not; v
O
also goes negative. For a sufficiently large
negative value of v
I
, v
O
will reach a negative maximum of -V
CC
if Q
2
saturates. Therefore, the transfer
characteristic will be as shown in Fig. 6.3.1(b). Since the transistors do not conduct for v
I
V
, where V
stands for the cut-in voltages of the transistors, there is a dead zone in the transfer characteristic around v
I
=
0. If v
I
is a sinusoidal signal, the waveform of the output voltage will be as shown in Fig. 6.3.2(a). The
waveforms of the emitter and output currents are also shown in this figure.
The distortion near the zero-crossing of the output signal is called the zero crossover distortion.
Reducing or eliminating the distortion is possible. Ignoring the crossover distortion and approximating v
O
(t)
as a sinusoid, the load power is same as the one given by (6.2.9); i.e.,
Efficiency
The average current drawn from the positive power supply is
The average current drawn from the negative power supply (In fact, the current sinks into the negative supply)
has equal value in magnitude but is negative, and therefore,
Therefore, the total power drawn from the power supplies is
491
P
S
V
CC
I
C1
V
CC
( I
C2
) ( 2 V
CC
V
m
) / ( R
L
) .
(6.3.5)
P
L
P
S
4
V
m
V
CC
.
(6.3.6)
P
Lmax
V
2
CC
2R
L
.
Fig. 6.3.2: The waveforms of varuous signals in the class-B amplifier of Fig. 5.3.1. (a) v
O
(t),
(b) i
L
(t), (c) i
E1
(t), and (d) -i
E2
(t).
(b)
T
2
T
t
i
L
(t)
0
3T
2
V
m
R
L
-V
m
R
L
(d)
T
2
T
t
i
E2
(t)
0
3T
2
V
m
R
L
-V
m
R
L
(a)
T
2
T
t
v
O
(t)
V
m
-V
m
0
3T
2
(c)
T
2
T
t
i
E1
(t)
0
3T
2
V
m
R
L
-V
m
R
L
Using (6.3.2) and (6.3.5), we find that
If the amplitude of the sinusoid V
m
equals the value of V
CC
, the efficiency reaches its maximum of
78.5%. The corresponding load power is
Clearly, the efficiency of the Class-B amplifier is much higher than the efficiency of the Class-A power
amplifier. This is the most important reason for its popularity in both IC and discrete circuits. Furthermore,
if v
I
= 0, the quiescent power dissipation in the transistors is zero. Another advantage of the Class-B operation
also exists. If V
m
is less than V
CC
, the efficiency decreases linearly in a Class-B amplifier whereas being
492
P
D
P
D1
P
D2
1
2
( P
S
P
L
)
V
CC
V
m
R
L
1
4
V
2
m
R
L
. (6.3.7)
V
m
( 2 V
CC
) / .
(6.3.8)
P
Dmax
V
CC
R
L
2V
CC
1
4
2V
CC
2
1
R
L
V
2
CC
2
R
L
2
2
P
Lmax
, (6.3.9)
Fig. 6.3.3: The collector dissipation as a function of the amplitude of the output sinusoid in the
class-B power amplifier.
V
m
P
D
P
Dmax
V
CC
2V
CC
= 50%
0
= 78.5%
proportional to ( V
m
/V
CC
)
2
, it decreases quadratically in a Class-A amplifier. For values of V
m
less than V
CC
,
the percentage decrease in the efficiency of the Class-B amplifier will be lower than the percentage decrease
in the efficiency of the Class-A amplifier.
Power Dissipation in the Transistors
Because of the symmetry, the power dissipation in both transistors should be equal. Therefore, if we
subtract the load power from the total power drawn from the power supplies, it should be twice the power
dissipated in each transistor. Thus, the power dissipation in each transistor is
Unlike in Class-A amplifiers, the average power dissipation depends on the value of V
m
in a Class-B
amplifier. The plot of P
D
as a function of V
m
is shown in Fig. 6.3.3.
Under the quiescent conditions (V
m
= 0), the collector-dissipations are zero. For some value of V
m
,
the collector-dissipation reaches a maximum value. To find the condition for the maximum collector-
dissipation, we can differentiate P
D
with respect to V
m
and equate it to zero. Solving such an equation, it can
be shown that P
D
reaches the maximum value, if
Substituting this value of V
m
in (6.3.7), the value of P
Dmax
is
where P
Lmax
= P
L
when V
m
= V
CC
. Therefore, to select the transistors in this circuit, the above equation is used
493
P
L
V
2
m
/ ( 2R
L
) 20 W.
V
CC
20 V .
P
Dmax
V
2
CC
/ (
2
R
L
) 5.066 W.
I
Cmax
( V
m
/ R
L
) ( V
CC
/ R
L
) 2.5 A .
to specify their power dissipation rating. In the Class-A amplifier with the transformer coupling, the collector
power dissipation should be greater than 2P
Lmax
(see (6.2.16)). This means that, for the same load power
delivery, the collector-dissipation of the transistor in a Class-B amplifier should only be approximately 10%
of what it is in a Class-A amplifier. In the design Example 6.1, the same 2-W power could have been
delivered with transistors having only about 0.4 W power dissipation rating had we used the Class-B
configuration. If the amplitude V
m
of the sinusoid is equal to the value given by (6.3.8), the efficiency will
only be 50%. Typically, the efficiency of the Class-B amplifiers is somewhere between 50% and 78.5%.
Design the push-pull Class-B amplifier to deliver a maximum power of 20 W to an 8- load.
SOLUTION
The amplitude of the sinusoidal signal at the output can be computed from
Using the value of R
L
= 8 , we find that V
m
= 17.89 V. To avoid the distortion of the output due to saturation,
we choose
The maximum collector-dissipation can be found using (6.3.9), and thus,
The maximum current through the transistors is
If v
O
(t) reaches -V
CC
, the maximum value of V
CE
in Q
1
is about 38 V. Similarly, the maximum value
of V
EC
in Q
2
should also be about 38 V. Therefore, we select a complementary pair of transistors, MJE180
(npn) and MJE170 (pnp) from Motorola, which satisfy the required power, current, and voltage ratings. These
transistors have a continuous current rating of 3 A, and V
CEO
= 40 V. With a heat sink provided, their power
dissipation rating is 12.5 W, which is more than twice the required value.
Single Supply Schemes
A Class-B power amplifier can also be designed with transformer coupling using a single power
supply. This circuit is shown in Fig. 6.3.4. One should note that the center-tapped secondary of the
transformer at the input enables the use of the npn-type for both transistors. This amplifier works in about the
same way as the previous circuit does. The load current reconstructed with the use of the center-tapped
transformer at the output will be similar to the one shown in Fig. 6.3.2(b). All the waveforms will be similar
494
v
O
( t ) 0, 0 ( t ) ,
V
m
sin( t ) V
, ( t ) ,
0, ( t ) ,
V
m
sin( t ) V
, ( t ) 2 ,
0, 2 ( t ) 2,
(6.3.10)
Fig. 6.3.4: A class-B power amplifier with
transformer coupling.
i
L
R
L
+
-
v
O
V
CC
i
C2
Q
2
Q
1
i
C1
+
-
v
BE1
v
BE1
-
+
Fig. 6.3.5: A class-B power amplifier
using a single power supply.
R
L
i
L
Q
1
+2V
CC
+v
O
+v
I
Q
2

to the ones shown in Fig. 6.3.2 except that of i
C2
. The waveforme of i
C2
will be the negative of the waveform
of (-i
E2
), shown in Fig. 6.3.2, i.e., i
C2
and i
E2
will have the same waveform. Therefore, all the power
calculations given for the previous circuit hold for this circuit also. This circuit has the advantage in that the
transformer can be used for impedance matching at the output.
Another single supply scheme without an elaborate arrangement of transformers is shown in Fig.
6.3.5. This circuit uses a pair of large-valued coupling capacitors just as in other ac-coupled amplifiers. The
operation of this circuit is similar to that of the circuit of Fig. 6.3.1 except that the low frequency components
will be attenuated. The choice of the coupling capacitors can be made to meet a specific value of 3-dB
frequency in the low frequency range (Chapter 8). If the amplifier is designed with a symmetrical signal-
swing, the maximum signal-swing at the output should be limited to V
CC
. This circuit can be designed using
the same method used to design the circuit in Fig. 6.3.1 with two power supplies except that the supply
voltage in this circuit should be (2V
CC
).
Total Harmonic-Distortion
The output voltage waveform in Fig. 6.3.2(a) is not purely sinusoidal. An accurate description of this
waveform during one period is
where V
is the cut-in voltage, and

495
sin
1
V
V
m
.
(6.3.11)
v
O
( t )
n 1
n odd
V
mn
sin( nt ) .
(6.3.12)
V
Heff
1
2
n 3
n odd
V
2
mn
.
(6.3.13)
THD
effective value of all harmonics
effective value of the fundamental
V
Heff
V
m1
/ 2
n 3
n odd
V
2
mn
V
m1
.
(6.3.14)
V
2
Heff
1
T
T
t 0
v
2
O
( t ) dt
V
2
m1
2
. (6.3.15)
THD
1
V
2
m1
2
T
T
t 0
v
2
O
( t ) dt 1 .
(6.3.16)
v
O
(t) is an odd function since v
O
(-t) = -v
O
(t). Also, v
O
(t) has half-wave symmetry in that v
O
(t+T/2) = -v
O
(t) for
all t. The Fourier series representation of an odd function with half-wave symmetry will have the fundamental
and odd harmonic sine terms only. Therefore, v
O
(t) can be represented in terms of its fundamental and odd
harmonics as follows:
In the above sum, n = 1 corresponds to the fundamental, and the other components are the harmonics. V
m1
is
the amplitude of the fundamental, and its effective value is (V
m1
/ 2). The effective value (rms) value of all
the harmonics put together is
The total harmonic-distortion is defined with
Using Parseval's theorem,
Using the above in the definition for THD,
The percentage THD can be found by multiplying the above result with 100.
The value of the term inside the square-brackets in (6.3.16) is nothing but twice the amount of power
dissipated by the output voltage v
O
(t) in a 1- resistor. The amplitude of the fundamental component of v
O
(t)
described in (6.3.10) is
496
V
m1
2
T
T
t 0
v
O
( t ) sin t dt V
m
1
2
sin( 2)
4cos
.
(6.3.17)
2
T
T
t 0
v
2
O
( t ) dt ( V
2
m
2V
2
) 1
2
V
2
m
sin( 2)
8V
m
V
cos
.
(6.3.18)
V
m1
2
T
T
t 0
v
O
( t ) sin ( t ) dt 4.11 V, and
2
T
T
t 0
v
2
O
( t ) dt 17.04
Fig. 6.3.6: A scheme to reduce the crossover distortion in a class-B power amplifier.
R
L
i
L
Q
1
+V
CC
+v
O
+v
I
Q
2
+
-
+v
X
R
B
A
d
-V
CC
Also, for the same v
O
(t),
For a given set of values for V
m
and V
, the value of can be computed using (6.3.11). We can then find the
values of V
m1
and the square-bracketed term in (6.3.16) using (6.3.17) and (6.3.18) respectively. Knowing
these values, the value of THD can be calculated. As an example, if V
m
= 5 V and V
= 0.7 V, = 0.1405
radians. Using this value of , we find that
Using these values in (6.3.16), THD = 8.9%. In an inexpensive audio power amplifier, this may be tolerable.
However, in a good high-fidelity system, the THD should be less than 1%, and the crossover distortion in the
Class-B power amplifier may be unacceptably high.
The zero crossover distortion can be reduced significantly using an op amp with negative feedback
as shown in Fig. 6.3.6. In this circuit, the output signal is compared with the input signal in the same way as
in the voltage follower circuit of Fig. P1.43. The operation of this circuit is similar to the regular Class-B
amplifier except that the dead zone is greatly reduced. Let A
d
be the difference-mode gain of the difference
amplifier. If v
I
= 0, then v
O
= 0, and v
X
= 0. Neither Q
1
nor Q
2
conducts. If v
I
increases positively, v
X
increases
positively; Q
1
starts to conduct when v
X
= V
or v
I
= (V
/A
d
), and v
O
starts to increase thereafter. Similarly, if
v
I
goes negative, v
O
also goes negative except when v
I
= (V
/A
d
). Clearly, the dead zone is now limited to
time intervals during which v
I
= (V
/A
d
), rather than v
I
= V
if the op amp is not used. Let us now relate

497
v
O
v
X
V
,
v
O
A
d
( v
I
v
O
) V
.
v
O
A
d
1 A
d
v
I
V
1 A
d
.
(6.3.19)
v
O
v
I
70 V .
v
O
and v
I
when either Q
1
or Q
2
conducts Neglecting the base-bias currents of Q
1
and Q
2
and the voltage-drop
across R
B
,
where V
is the cut-in voltage of the base-emitter junctions of Q

1
and Q
2
. The "-" sign holds, if v
O
is positive,
and the "+" holds, if v
O
is negative. Since v
X
= A
d
(v
I
- v
O
),
Solving the above equation, the output voltage is
If A
d
= 10,000 and V
= 0.7 V,
Clearly, the op amp works in the buffer mode of Fig. P1.43, and the dead zone becomes insignificant in the
transfer characteristic. Therefore, the crossover distortion is almost be eliminated at the output. However, such
an elaborate arrangement is not a practical solution to reduce the distortion. A better solution is to use the
Class-AB operation, where a small nonzero bias current is used.
6.4: CLASS-AB AMPLIFIERS
By operating the transistors in the push-pull amplifier with a small dc bias collector current I
CQ
, the
distortion caused by the dead-zone can be eliminated. Therefore, the Class-AB operation is very popular in
both IC and discrete designs.
A Class-AB Power Amplifier using a Diode-scheme
A Class-AB amplifier and its transfer characteristic are shown in Fig. 6.4.1. The two diode-connected
transistors D
1
and D
2
are biased by a constant-current source I
BIAS
. Even if v
I
= 0, a part of the current I
BIAS
flows through the diodes generating the bias voltage V
BB
. This bias voltage keeps Q
1
and Q
2
on. Therefore,
there is no "dead zone" in this characteristic; the crossover distortion will be absent. The various current
waveforms are shown in Fig. 6.4.2. There is an important advantage in this scheme. An increase in the
collector current increases the power dissipation, which, in turn, increases the junction temperature of the
output BJTs. Any increase in the temperature causes a decrease in the diode voltage and a decrease in V
BB
,
since the diode-connected transistors are in the same neighborhood in an IC. A decrease in V
BB
causes a
reduction in the collector currents of the power transistors. Thus, there is a thermal tracking, and the output
transistors are protected from the thermal runaway.
Assume that both Q
1
and Q
2
have the same junction areas, and the junction areas of D
1
and D
2
are also
498
Fig. 6.4.1: A class-AB power amplifier using a diode scheme, and (b) transfer characteristic.
(a)
R
L
i
L
Q
1
+V
CC
-V
CC
+v
O
v
I
Q
2
+
v
BB
-
+
-
D
1
D
2
I
BIAS
(b)
v
O
-V
v
I
V
CC
-V
CC
slope 1
Fig. 6.4.2: Waveforms of collector and load currents in a class-AB power amplifier. The
collector currents and the load current are concident except near the zero
crossing. Observe that the load current is not distorted as in class-B operation.
0
I
CQ1
i
CQ2 I
CQ2
t
Amplitude of the current
i
L
i
CQ1
2
equal. However, the junction areas of the diodes need not be as large as the junction areas of the output
transistors because the diode-connected transistors need to carry only a low bias current in the order of base-
bias current of Q
1
. Let the junction area of the power transistors be n-times the junction area of the diode-
connected transistors. If so, the saturation current of the output transistors will be n-times the saturation
current of the diodes. The voltage V
BB
provides the bias for the output transistors. The dc component of v
I
is
usually such that the dc component of v
O
is zero. Therefore, under the quiescent conditions, assume that v
O
499
V
BB
2V
T
ln [ I
BI AS
( I
CQ
/
dc1
) ]/ I
S
2V
T
ln[ I
CQ
/ ( nI
S
) ],
(6.4.1)
I
CQ
I
BI AS
1/ n 1/
dc1
n I
BI AS
, if
dc1
n.
(6.4.2)
P
S
2V
CC
[ V
m
/ ( R
L
) I
CQ
] .
(6.4.3)
P
D1
P
D2
1
2
( P
S
P
L
) V
CC
V
m
R
L
I
CQ
1
4
V
2
m
R
L
. (6.4.4)
P
Dmax
V
CC
V
CC
2
R
L
I
CQ
.
(6.4.5)
= 0. There is a collector bias current I
CQ
in Q
1
and Q
2
, and the current through the diodes will be [I
BIAS
-
(I
CQ
/
dc1
)]. Therefore,
where I
S
is the saturation current of the diodes. Solving the above, the value of I
CQ
is
For a given value of I
CQ
, which is usually less than 10% of the maximum load current, the value of
I
BIAS
can be made as small possible (not zero, of course) by choosing a large value for n. However, there is
a limit to the minimum value of I
BIAS
, which limits the maximum value of n. If the base-bias current in Q
1
becomes a substantial portion of I
BIAS
, the diode current will reduce. This, in turn, will reduce the value of
V
BB
. There should be a minimum diode current to maintain the output transistors in the active-mode.
Therefore, there is a need for a minimum value for I
BIAS
. For a given I
CQ
, the value of n cannot therefore be
arbitrarily large, and the junction area of the diode-connected transistors cannot be too low.
Because of the collector-bias current in Q
1
and Q
2
, there is a quiescent power dissipation. The
equations derived in Section 6.3 for the total power drawn form the power sources and the collector-
dissipation must be modified to account for the quiescent power dissipation. The equation (6.3.5) for P
S
should be modified to
The power dissipation in each transistor also increases to
The maximum power dissipation in the output transistors will be
In the Class-AB power amplifier of Fig. 6.4.1, V
CC
= 12 V, R
L
= 100 , and v
O
(t) = 10sin(t) V. The
input bias voltage is such that the dc output offset is zero. The power transistors have I
S
= 0.1 pA,
Q1
= 100,
and V
A1
= 100 V. The diode-connected transistors have a the junction area of the power transistors. If a
minimum diode current of 1 mA is required, find the minimum value for the bias current I
BIAS
. Find the value
of I
CQ
through the transistors. Also, calculate the efficiency of the power amplifier and the required power
rating for the power transistors. Find the harmonic components in v
O
(t) up to 10
th
harmonic using PSPICE
500
I
Cmax
I
Lmax
( 12 / 0.1) 120 mA .
I
BIAS
( I
Cmax
/
dc1
) 1 2.071 mA .
I
CQ
I
BIAS
1/ 3 1/ 112
6.051 mA .
P
L
V
2
m
2R
L
10
2
2100
0.5 W.
P
S
212( 31.83 6.051) 909.1 mW.
simulation. The transient analysis is required for this purpose. Find the percentage of THD assuming that the
amplitudes of components beyond 10
th
harmonic are insignificant.
SOLUTION
Under the quiescent conditions, V
O
= 0, and
dc1
= 112. The maximum collector current in Q
1
is
Since the minimum diode current should be 1 mA, the value of I
BIAS
should be at least
Then,
In this scheme, once the value of I
BIAS
is chosen, there is no control on I
CQ
except through the value of n. To
lower the value of I
CQ
, we have to lower the value of n. This emphasizes the point that we cannot increase
n to a high value.
The power absorbed by the load is
Using (6.4.3), we find that
Therefore, the efficiency is Using (6.4.5), we find that the maximum power dissipation in the output 55 %.
power transistors is 0.219 W. Therefore, a transistor should be adequate in this application. 1/4 W
The transient analysis was carried out with a sinusoidal input signal with an arbitrarily chosen
amplitude of 10 V and a frequency of 1000 Hz. The plot of the output signal is shown in Fig. 6.4.3. There
was an output offset voltage of about 6.299 mV. Otherwise, the output is very close to a sinusoidal signal.
The Fourier analysis was also carried out, and the amplitudes of the harmonics up to the 10
th
were obtained.
These values are available in the output file along with the value of THD and are listed here in Table 6.1. The
THD is about 0.15%. The total harmonic distortion is indeed very small as anticipated in a Class-AB
amplifier.
501
I
BIAS
I
C3
I
R
.
(6.4.6)
V
BB
V
BE3
( 1 R
1
/ R
2
) ,
(6.4.7)
V
BE3
V
T
ln ( I
C3
/ I
S3
) .
(6.4.8)
Fig. 6.4.3: The waveform of the output signal in Design Example 6.5
Time in ms
O
u
t
p
u
t

v
o
l
t
a
g
e

v
O
0 0.5 1.0 1.5 2.0 2.5 3.0
-10.0 V
-5.0 V
0 V
5.0 V
10.0 V
Table 6.1: The amplitudes of the fundamental and the other harmonics in Example 6.5.
NORMALIZED PHASE NORMALIZED FOURIER FREQUENCY HARMONIC
PHASE (DEG) (DEG) COMPONENT COMPONENT (HZ) NO
0.000E+00 8.178E-04 1.000E+00 9.903E+00 1.000E+03 1
9.275E+01 9.276E+01 7.756E-04 7.682E-03 2.000E+03 2
-1.791E+02 -1.790E+02 1.194E-03 1.183E-02 3.000E+03 3
7.911E+01 7.912E+01 6.955E-05 6.888E-04 4.000E+03 4
1.789E+02 1.789E+02 4.474E-04 4.430E-03 5.000E+03 5
9.919E+01 9.920E+01 3.279E-05 3.247E-04 6.000E+03 6
-1.790E+02 -1.790E+02 2.069E-04 2.049E-03 7.000E+03 7
8.094E+01 8.094E+01 1.784E-05 1.767E-04 8.000E+03 8
1.792E+02 1.792E+02 1.108E-04 1.098E-03 9.000E+03 9
9.125E+01 9.125E+01 6.666E-06 6.602E-05 1.000E+04 10
TOTAL HARMONIC DISTORTION = 1.512880E-01 PERCENT
A Class-AB Power Amplifier using a V
BE
-multiplier Circuit
To keep the value of V
BB
relatively constant, a V
BE
-multiplier circuit may be used instead of the
diodes. This scheme is shown in Fig. 6.4.4, which is more flexible than the diode scheme and is also popular
in IC amplifiers. Q
3
has relatively a smaller area because its collector current needs to be in the order of the
maximum value of the base-bias current of the output transistor Q
1
. For a given value of the bias current I
BIAS
,
the ratio (R
1
/ R
2
) can be adjusted to produce the required value of V
BB
that sets a specified value of I
CQ
in the
output transistors. Under the quiescent conditions, neglecting the base-bias current of Q
1
,
where I
R
is the current through R
1
. Neglecting the base-bias current of Q
3
, we find that
where
Since V
BB
is obtained by multiplying V
BE3
with a factor, this scheme is called the V
BE
-multiplier scheme. The
advantage of the scheme is that a specific value of I
CQ
can be set by controlling the resistance ratio. Besides,
502
V
BB
2V
T
ln ( 10mA / 0.1pA ) 1.317 V.
V
BB
( 1 R
1
/ R
2
) V
BE3
( 1 R
1
/ R
2
) V
T
ln
I
BIAS
V
BB
/ ( R
1
R
2
) I
CQ
/ 115
I
S3
.
Fig. 6.4.4: A class-AB power amplifier using a V
BE
- multiplier sheme.
Q
1
+V
CC
+v
O
v
I
+
+
-
I
BIAS
R
L
i
L
-V
CC
Q
2
v
BB
-
I
R
I
C3
Q
3
R
1
R
2
the change in V
BB
will be very small even if there is a large increase in the collector current of Q
1
. An increase
in the collector current of Q
1
causes an increase in the base-bias current of Q
1
. Then, the collector current of
Q
3
decreases. However, if Q
3
remains in the active-mode, a large change in I
C3
causes only a very small
change in the value of V
BE3
keeping the value of V
BB
relatively constant.
In the Class-AB amplifier of Fig. 6.4.4, V
CC
= 15 V, and R
L
= 100 . The saturation current of the
power transistors is 0.1 pA and that of the small-signal transistor Q
3
is 0.01 pA. It is required to establish I
CQ
= 10 mA. The maximum amplitude of the output signal is expected to be 15 V. V
A
= 100 V and = 100 for
Q
1
. Design the circuit.
SOLUTION
dc1
= 115. The maximum expected collector current of Q
1
is 150 mA, and the maximum base current
of Q
1
will be approximately 1.3 mA. Therefore, I
BIAS
should be more than 1.3 mA. The value of V
BB
required
under the quiescent condition is
Under the quiescent conditions, we also find that
503
R
1
R
2
( 1.317 / 0.5 ) 2.634 k.
1
R
1
R
2
1.317
0.026 ln ( 2mA / 0.01 pA )
1.947.
R
2
1.353 k, and R
1
1.281 k.
I
C3
I
BIAS
I
C1
dc1
V
BB
R
1
R
2
2.5
150
115
1.317
2.634
0.7 mA.
V
BB
1.9470.026 ln( 0.7 mA/ 0.01 pA ) 1.282 V.
There is only one equation with three unknowns, R
1
, R
2
, and I
BIAS
. Therefore, some unknowns can be
arbitrarily selected. We can choose which is greater than 1.3 mA, the maximum base I
BIAS
2.5 mA,
current of Q
1
. This allows us to provide a minimum 1.2 mA for (I
C3
+ I
R
). Allowing I
R
= 0.5 mA and noting
that V
BB
is relatively constant,
Neglecting the base-bias current of Q
1
under the quiescent conditions, I
C3
will be 2 mA. Therefore, using
(6.4.7) and (6.4.8),
Solving for R
1
and R
2
from the above two equations, the values of R
1
and R
2
can be found to be
The closest standard values for R
1
and R
2
may be picked in a discrete design. However, using a variable
resistor, the value of V
BB
can be adjusted for a specific value of I
CQ
. In an IC, the initial design can be set for
the required values. This completes the design. If the load current reaches the maximum of 150 mA,
We have used an approximate value for V
BB
in the above equation. However, using the new possible value
of I
C3
, a correct estimate for the value of V
BB
is
Clearly, the value of V
BB
remains relatively constant in this scheme, as the collector current of the output
transistor changes.
Small-Signal Analysis of Class-AB Amplifiers
Under the Class-AB operation, the power amplifier becomes almost a linear amplifier. Since the
Class-AB power amplifier is also the output stage of a multi-stage amplifier (for example, an op amp), it is
also necessary to know how to estimate its primary parameters, such as the voltage gain. During this analysis,
we assume that the input source is a voltage source v
s
with a source impedance R
s
. While the input signal is
directly fed to the base-node of Q
2
, the signal path to the base-node of Q
1
has an additional resistance of the
base-bias circuits for small signals in both configurations of Figs. 6.4.1 and 6.4.4. Fortunately, this additional
resistance is very small in comparison to the input resistance looking into the base-node of Q
1
and can be
neglected. This is essentially equivalent to the assumption that the biasing part of the amplifier can be short-
504
r
ee
( r
e1
r
e2
) , r
e
( r
1
r
2
) , k
be
( r
ee
/ r
e
) , and r
oe
( r
o1
r
o2
) .
(6.4.9)
i
o
v
i
r
ee
( R
L
r
oe
)
v
i
100.7
.
v
s
k
be
i
o
R
s
v
i
, v
i
0.8029 v
s
.
v
o
0.8029 v
s
98.51
100.7
0.7854v
s
, A
vs
v
o
v
s
0.7854 V/ V.
R
i
R
s
( v
s
/ v
i
) 1
8.147 k.
Fig. 6.4.5: The small-signal equivalent circuit of class-AB amplifier. The boxed-part shows the
model of the composite (parallel combination of Q
1
and Q
2
) BJT in a power
amplifier. The parameters are defined in (6.4.9).
+
-
v
s
R
s
k
be
i
o
+
-
+
-
v
i
1v
i
r
ee
i
o
r
oe
R
L
+v
o
R
o
R
i
i
i
circuited for small-signals. With this excellent approximation, the amplifier becomes a parallel connection
of the two output transistors, and one can obtain the small-signal equivalent in the form of Fig. 3.5.3(b) to
represent this circuit as shown 6.4.5, where the small-signal parameters of the composite BJT are
The small-signal parameters of the individual transistor can be easily calculated using the usual
formulas at the corresponding collector-bias currents (I
CQ1
and I
CQ2
for Q
1
and Q
2
respectively). Using the
equivalent circuit of Fig. 6.4.5, one can easily find the amplifiers primary parameters. As an example,
consider the situation in Example 6.5. Assume that the input source has an internal resistance of 2 k. In
addition to the parameters given in Example 6.5, assume that V
A1
= 100 V, and V
A2
= 50 V, and
Q2
= 50. Since
V
CE1
= V
CE2
= 12 V,
dc1
= 112, and
dc1
= 62. Since I
EQ1
= I
EQ2
I
CQ1
= 6.501 mA, r
e1
= r
e2
= 4.3 , and r
ee
=
2.15 . r
1
= 485.9 , r
2
= 270.9 , and r
e
= 173.9 . Therefore, k
be
= (2.15/173.9) = 0.01236. Furthermore,
r
o1
= 18.51 k, r
o2
= 10.25 k, and r
oe
= 6.6 k. This leads to (R
L
r
oe
) = 98.51 . Using these parameters,
Using KVL,
Clearly then,
The input resistance is
Since the load resistance is relatively small, input resistance is also relatively small. Clearly, most of the
attenuation of the signal occurs at the input of the amplifier. Of course, the output resistance of the amplifier
505
R
o
r
ee
k
be
R
s
26.87 .
Fig. 6.4.6: A class-AB power amplifier using the compound transistors.
Q
1
+V
CC
+v
O
R
L
i
L
-V
CC
Q
2
v
I
+
-
I
BIAS
Q
3
R
1
R
2
Q
4
Q
5
Q
6
is
Clearly, it is very simple to evaluate the amplifiers parameters using the equivalent circuit of Fig. 6.4.5.
Class-AB Amplifier using Darlington Pairs
To reduce the base-bias currents of the power transistors, the Darlington pair and composite
transistors may be used for Q
1
and Q
2
in the circuits of Figs. 6.4.1 and 6.4.4. An example circuit is shown in
Fig. 6.4.6. In this circuit, the base-bias current of Q
1
will be approximately (i
L
/
1
2
). The compound transistor,
formed by Q
4
, Q
5
, and Q
6
, behaves as a pnp transistor with an effective value of (
4
6
). In IC
technology, the pnp transistor is usually a lateral pnp transistor having a low -value ( 5 to 10) (see
Appendix-A). Since (
1
2
) is likely to be very high, the use of two npn transistors Q
5
and Q
6
in conjunction
with Q
4
permits a similar effective current gain to be achieved. This is necessary to keep the positive and
negative signal-swings approximately equal. The lateral pnp transistors also have poor frequency response.
If this scheme is used in a discrete circuit design, it may be sufficient to use only one npn transistor in the
compound pnp transistor. In the recent past, vertical pnp transistors have been realized in IC technology (see
Fig. A.8(b) in Appendix-A), and they may also be used to realize current mirror circuits. Vertical pnp
transistors, with high frequency responses closely matching those of npn transistors, may also be used in the
IC designs. There is an inherent stability problem in the circuit of Fig. 6.4.6. Because of the internal feedback
506
Fig. 6.5.1: A class-AB MOSFET output
amplifier.
i
L
i
D2
R
L
+v
O
-V
SS
+V
DD
M
1
M
2
+v
I
M
4
M
3
I
BIAS
i
D1
+
-
V
GG
Fig. 6.4.7: A class-AB power amplifier with
short-circuit protection.
Q
1
+V
CC
+v
O
R
L
i
L
-V
CC
Q
2
Q
4
Q
5
v
I
+
-
I
BIAS
Q
3
R
1
R
2
R
3
R
4
in the composite connection of Q
4
and Q
5
, there could be high frequency oscillations. This problem can be
handled with a proper frequency compensation (Chapter 9).
Short-circuit Protection
If there is an accidental short-circuit (R
L
= 0), the collector current in the output transistors can
become excessively high causing a thermal runaway. If the junction temperature increases beyond T
Jmax
, the
transistors will be damaged. Therefore, it is critical to provide the output transistors with a short-circuit
protection. A modification of the Class-AB power amplifier of Fig. 6.4.4 with a short-circuit protection is
shown in Fig. 6.4.7. Besides the usual components as in the circuit of Fig. 6.4.4, this circuit has four
additional components, namely Q
3
-R
3
and Q
4
-R
4
combinations. These combinations provide the short-circuit
protection to the amplifier. The transistors, Q
3
and Q
4
, need only be small-size transistors as they are expected
to carry collector currents in the order of the base-bias currents of the power transistors.
The resistance values of R
3
and R
4
are small (usually a fraction of an ohm to a few tens of ohms
depending upon the maximum collector current). Under the normal operating conditions, the voltage drops
across these resistances are adjusted to be less than V
(about 0.5 V), and therefore, Q

3
and Q
4
will be under
507
v
Omax
V
DD
V
tn
(
2
n
/ 2)
n
V
DD
V
SS
V
tn
(
2
n
/ 4) .
(6.5.1)
v
Omin
V
SS
V
tp
(
2
p
/ 2)
p
V
DD
V
SS
V
tp
(
2
p
/ 4) .
(6.5.2)
i
Omax
( v
Omax
/ R
L
) , and i
Omin
( v
Omin
/ R
L
) .
(6.5.6)
i
Omax
K
1
( V
DD
v
Omax
V
t 1
)
2
, and i
Omi n
K
2
( V
SS
v
Omi n
V
t 2
)
2
,
(6.5.7)
the cutoff conditions normally. However, if the collector currents in Q
1
and Q
2
become excessively large due
to accidental short-circuits, the voltage drops across these resistors turn on the transistors Q
3
and Q
4
starving
the bases of Q
1
and Q
2
. This process, in turn, virtually shuts the collector currents through the power
transistors protecting them from the thermal runaway.
6.5: MOSFET CONFIGURATIONS
A Class-AB MOSFET output amplifier is shown in Fig. 6.5.1. This configuration is very similar to
that of the BJT amplifier of Fig. 6.4.1. The diode-connected MOSFETs M
3
and M
4
provide the bias voltages
for M
1
and M
2
. The operation of this circuit is also very similar to that of its BJT counterpart, and indeed this
circuit can be operated either as a Class-B or a Class-AB amplifier. However, the signal-swing and biasing
considerations are different because MOSFETs suffer from body effects. When the gate-node potential of M
1
can be taken to the level of V
DD
, the output signal reaches the maximum positive signal v
Omax
. Let the
corresponding drain current of M
1
be (v
Omax
/R
L
). We can find the value of v
Omax
using (4.7.11). Typically, (V
DD
+ V
SS
- V
t1
) Neglecting this excess gate voltage ( i
Omax
/ K
1
) . ( i
Omax
/ K
1
) ,
Following similar steps, assuming that the gate-node potential of M
2
can be lowered to the level of -V
SS
and
that only M
2
conducts under this condition, we can show that the minimum possible output signal (negative
value) is
The maximum and minimum possible output currents are
However, these currents are also given by
where V
t2
is the threshold voltage of M
2
corrected for its body effect.
The fundamental parameters of the n-channel MOSFETs in the circuit of Fig. 6.4.6 are: KP =
V
tn
= 0.7339 V,
n
= 0.03122 V
-1
,
n
= 0.4823 V
1/2
, and (2
f
) = 0.7 V. The parameters of the p- 51.17 A/V
2
,
channel MOSFETs are: KP = 16.53 A/V
2
, V
tp
= -0.7776 V,
p
= 0.04349 V
-1
,
p
= 0.6727 V
1/2
, and (2
f
) =
508
v
Omax
5 0.7339
0.4823
2
2
0.4823 5 5 0.7339 ( 0.4823
2
/ 4) 2.91 V,
v
Omi n
5 0.7776
0.6727
2
2
0.6727 5 5 0.7776 ( 0.6727
2
/ 4) 2.393 V.
i
Omax
v
Omax
R
L
2.91 mA, and i
Omi n
v
Omi n
R
L
2.393 mA.
V
t 2
0.7776 0.6727 5.7 2 0.7 2.081 V.
2 mA K
2
( 5 2 2.081)
2
.
W
L
2
574
2
.
W
L
1
16.53
51.17
574
2
186
2
.
0.7 V. Assume that V
DD
= V
SS
= 5 V, I
BIAS
= 10 A, and R
L
= 1 k. Assuming that the gate-node potentials of
M
1
and M
2
can be taken to V
DD
and -V
SS
respectively, find the possible output voltages and the corresponding
output currents. Since
p
>
n
, by comparing (6.4.12) and (6.4.13), it may be noted that
Assume that the load current is limited to when the gate-node potential of M
2
v
Omi n
< v
Omax
. 2 mA,
reaches -V
SS
. Obtain the sizes of M
2
and M
1
. It is also required to have v
O
= 0, and I
D1
= I
D2
= 0.1 mA, if the
signal input v
i
is zero. Find the required input dc bias voltage and the sizes of M
3
and M
4
. Choose the
minimum length of L = 2 m for all the MOSFETs and neglect the channel-length modulation. Verify the
signal-swings of the design using PSPICE simulation. Also, use Fourier analysis in PSPICE by applying a
sinusoidal signal of 1000 Hz frequency and of suitable amplitude to avoid saturation and find the THD.
SOLUTION
Using (6.5.4) and (6.5.5), we find that
and
Clearly,
If i
O
= -2 mA, v
O
= -2 V. At this voltage,
Therefore, ignoring the channel-length modulation,
From the above equation, we find the required value of K
2
and hence the required width choosing L
2
= 2 m.
This results in the aspect ratio of
Since M
1
should carry the same level of current at the same output voltage, we choose
With these choices,
509
K
1
51.17
2
186
2
2379.4 A/ V
2
, and K
2
16.53
2
574
2
2372.1 A/ V
2
.
V
t 2
0.7776 0.6727 5.7 0 0.7 1.821 V.
V
SG2
V
t 2
100
2372.1
2.026 V.
W
L
3
1
10
W
L
1
19
2
, and
W
L
4
1
10
W
L
2
58
2
.
Fig. 6.5.2: The transfer characteristic of the class-AB amplifier designed in Example 5.7
Input in V
O
u
t
p
u
t

i
n

V
-4
-2
0
2
4
-6 -4 -2 0 2 4 6
At v
O
= 0,
Since I
D2
= 100 A under this condition,
Therefore, the dc input bias voltage should be At the zero output bias voltage, V
I
V
SG2
2.026 V.
the bias currents of M
1
and M
3
are in the ratio of (1/10) and those of M
2
and M
4
are also in the ratio of (1/10).
Besides, the same gate-to-source voltages of M
1
and M
3
and those of M
2
and M
4
are equal. Therefore, the
aspect ratios of M
3
and M
4
can be found to be
The circuit was simulated in PSPICE, and the transfer characteristic is shown in Fig. 6.5.2 with a dc
input bias voltage of V
I
= -2.026 V. From this characteristic, the output offset was found to be which -6.7 mV,
is indeed very small. Besides, at v
I
= -2.026, V
GG
= 3.7 V. When the gate-node potential of M
1
becomes 5.72
V, the output voltage reached a level of approximately equal to +2.91 V. In our original design, we calculated
this output level at the gate-node potential of M
1
at +5 V. However, in this calculation, we ignored the excess
gate-to-source voltage. Similarly, when the gate-node potential of M
2
reached a level of -5.48 V, the output
reached the level of -2.39 V. Again, in our original calculation, at the output level of -2.39 V, the gate-node
potential of M
2
should be at -5 V. The error is again due to the excess gate-to-source voltage. From the
510
Fig. 6.5.3: The waveform of the output signal in the Design Example 6.7.
O
u
t
p
u
t

v
o
l
t
a
g
e

v
O
Time in ms
0 0.5 1.0 1.5 2.0 2.5 3.0
-2.5V
-2.0V
-1.5V
-1.0V
-0.5V
0V
0.5V
1.0V
1.5V
2.0V
PSPICE simulation, we found that, at the output levels of +2 V and -2 V, the inputs were required to be
+1.144 V and -5.021 V respectively. With an input of 0 V, the output offset voltage was 1.2806 V, and an
input voltage of -2.1174 V was required to offset this and bring the output to zero. Finally, it should be noted
that the nonlinear transfer characteristic is not only due to the square-law characteristic of the MOSFETs but
also because of the nonlinear body effect which depends on the output voltage.
A sinusoidal signal with an amplitude of 3 V and a frequency of 1000 Hz was applied at the input.
The input offset was set to -2.1174 V. The transient response, obtained from the PSPICE, is shown in Fig.
6.5.3. Even though the input offset was set to be the required value, one can observe the fact that the positive
and negative peaks are not identical. The Fourier analysis showed that the fundamental component was
The second harmonic, as was pointed out in Chapter 4, was the next dominant term with an 1.939 V.
amplitude of 55.86 mV. The third and fourth harmonics were respectively 13.17 mV and 9.753 mV. We
found the amplitudes of the harmonics up to 10
th
harmonic. The THD was found to be 3.01%. Clearly, a
Class-AB MOSFET power amplifier suffers from considerably more distortion than its BJT counterpart.
Although the output amplifier of Fig. 6.5.1 has a low output impedance, since the MOSFETs M
1
and
M
2
suffer from body effects, the signal-swings of the output are severely limited. The gate-node potentials
of M
1
and M
2
can not even reach the levels of +V
DD
and -V
SS
in a practical realization of circuit shown in Fig.
6.5.1. An alternate scheme is to use the inverter configuration of Fig. 6.5.4, which can source current from
a high output impedance node without wasting any current. This circuit can also be operated either in Class-B
or Class-AB by adjusting the gate voltages of M
3
and M
4
. If it operates in Class-B, as the input goes positive,
511
Fig. 6.5.4: Push-pull inverting CMOS output amplifier with a high impedance output.
i
o
R
L
+v
O
-V
SS
+V
DD
+v
I
+V
G1
+V
G2
M
1
M
2
M
4
M
5
M
3
M
6
M
7
M
8
+V
T2
-V
T1
i
D7
i
D8
the current in M
1
increases, and M
2
is turned off. This current in M
1
is reflected as the drain current in M
8
,
which is the load current because the current in M
7
should be zero. Similarly, if v
I
goes negative, the current
in M
2
increases and is reflected as the current in M
7
, which will be load current because M
8
is now cutoff. It
can be noted that the output voltage can swing almost to the supply voltages. However, the circuit constitutes
a voltage-controlled current source because the output resistance, at the quiescent conditions, is (r
o7
r
o8
),
which is relatively high. Such an output stage can be used in an operational transconductance amplifier
(OTA). This circuit is very attractive from all points of view except possibly the output resistance. Consider
a design example on the sizing of the MOSFETs and the calculation of the required bias voltages V
G1
and V
G2
.
The process parameters of the MOSFETs in the circuit of Fig. 6.5.4 are the same as those in Example
6.7. Assume that V
DD
= V
SS
= 5 V, and R
L
= 1 k. The load current is limited to It is also required 4 mA.
to have v
O
= 0, and I
D1
= I
D2
= 0.4 mA, if v
I
= 0. Obtain the sizes for all MOSFETs. Choose the minimum
length of L = 2 m for all the MOSFETs. Verify the signal-swings using PSPICE simulation.
SOLUTION
At the maximum possible output current of +4 mA, the output voltage should be +4 V. The MOSFET
M
7
should remain in the pinch-off mode at least until this level. Therefore, it is required that
512
V
DD
v
O
v
O
K
7
R
L
K
7
4000 A/ V
2
.
KP
2
W
L
7
4000 A/ V
2
W
L
7
484.
W
L
7
970
2
.
W
L
8
16.53
51.17
970
2
313.4
2
,
W
L
8
314
2
.
K
7
16.53
2
970
2
4008.5 A/ V
2
, and K
8
51.17
2
314
2
4016.8 A/ V
2
.
V
GS6
V
GS8
0.7339
400
4016.8( 1 0.031225)
1.0274 V.
40 A
51.17
2
W
L
6
( V
GS6
V
tn
)
2
( 1 0.03122V
GS6
)
W
L
6
36
2
.
V
SG5
V
SG7
0.7776
400
4008.5( 1 0.043495)
1.0639 V,
40 A
16.53
2
W
L
5
( V
SG5
V
tp
)
2
( 1 0.04349V
SG5
)
W
L
5
113
2
.
Therefore, the aspect ratio of M
7
must satisfy the condition of
We choose
The size of M
8
is given by
and we choose
With these aspect ratios, we find that
At any output current level, the current through M
3
and M
5
(similarly in M
4
and M
6
) need not be that
high. We choose a current scaling ratio of 10 in the current mirrors formed by M
5
-M
7
and M
6
-M
8
pairs and
design the circuit to operate as a Class-AB amplifier with the drain currents I
D7
= I
D8
= 0.1 4 mA = 400 A,
if v
I
= v
O
= 0. If the current scaling ratio of 10 is used, then the current through M
5
and M
6
should be 40 A,
when v
I
= v
O
= 0. With I
D8
= 400 A, the required bias voltage V
GS6
= V
GS8
can be calculated to be
Next,
Proceeding in the same way, we find that
and
513
V
t 1
V
tn

n
( V
T1
V
SS
0.7 0.7) V
tn

n
V
T1
V
SS
.
V
T1
V
t 1
I
D1
/ K
1
.
V
T1
V
tn

n
V
T1
V
SS
.
V
T1
V
tn

2
n
/ 2
n
V
SS
V
tn

2
n
/ 4 1.6205 V.
V
t 1
V
tn

n
V
T1
V
SS
0.7 0.7 1.3045 V.
I
D1
40 A
KP
2
W
L
1
V
T1
V
t 1
2
1 0.0312 V
DS1
W
L
1
26
2
.
V
T1
V
tn
I
D1
/ K
1

2
n
/ 2
n
0.7
n
V
SS
V
tn
I
D1
/ K
1
0.7
n
0.7
2
n
/ 4 1.648 V,
V
t 1
V
tn

n
( V
T1
V
SS
0.7 0.7) 1.3012 V.
V
t 4
V
tp

p
( 6.648 0.7 0.7) 2.0383 V.
V
T1
and V
T2
depend on the threshold voltages of M
1
and M
2
, which, in turn, depend V
T1
and V
T2
because of the body effect. We do not know the sizes of M
1
and M
2
yet, and therefore, we can only evaluate
the approximate values of V
T1
and V
T2
. First, consider M
1
with v
I
= 0. Its threshold voltage is
and the equation for V
T1
is
Since V
t1
as first order approximation, we can neglect the second term in the above equation and I
D1
/ K
1
,
get the following approximate equation for V
T1
:
Solving the above equation, we obtain
Using the above value of V
T1
, an approximate value of V
t1
is
Then,
With the above choice of the aspect ratio for M
1
, Since we now know the values for K
1
332.6 A/ V
2
.
drain current of M
1
and its conductivity parameter, we can find the accurate value of V
T1
and its threshold
voltage using
and
The approximate values found earlier and the above accurate values agree very well. Proceeding further, we
find that V
BS4
= 6.648 V, V
SD4
= 2.3246 V, and
The value of V
G2
should be less than and we choose Next using the drain ( V
T1
V
t 4
) , V
G2
4 V.
bias current of 40 A in M
4
, we find the size of M
4
using
514
I
D4
40 A
KP
2
W
L
4
( V
G2
V
T1
V
t 4
)
2
( 1 0.04349 V
SD4
)
W
L
4
90
2
.
V
T2
V
tp

2
p
/ 2
p
V
DD
V
t p

2
p
/ 4 1.952 V.
V
t 2
V
tp

p
( V
DD
V
T2
0.7 0.7 ) 1.5159 V.
I
D2
40 A
KP
2
W
L
2
V
T2
V
t 2
2
1 0.04349 V
SD2
W
L
2
36
2
.
V
T2
V
tp
I
D2
/ K
2

2
p
/ 2
p
0.7
p
V
DD
V
tp
I
D2
/ K
2
0.7
p
0.7
2
p
/ 4 2.023 V.
V
t 3
V
tn

n
( V
T2
V
SS
0.7 0.7 ) 1.6707 V.
I
D3
40 A
KP
2
W
L
3
( V
G1
V
T2
V
t 3
)
2
( 1 0.03122 V
DS3
)
W
L
3
32
2
.
W
L
2
34
2
, and
W
L
3
29
2
,
Proceeding further to find the required sizes of M
2
and M
3
, we first find the approximate value of V
T2
using
Next, the threshold voltage of M
2
can be found to be
Also, V
SD2
= 6.952 V. Since I
D2
= 40 A,
With the above choice of the aspect ratio of M
2
, We can refine the value of V
T2
using K
2
148.75 A/ V
2
.
Therefore,
V
G1
should be greater than (V
T2
+ V
t3
), and we can choose We also find that V
DS3
= 1.913 V. V
G1
4 V.
Finally, we find the size of M
3
using
The above design was simulated in PSPICE. The transfer characteristics are shown in Fig. 6.5.5.
From these characteristics, at v
I
= 0, the output current was found to be 37.5 A (the output offset). The drain
currents of M
7
and M
8
were 469.9 A and 432.4 A respectively. Besides, the bias voltages V
T1
and V
T2
were
1.635 V and 2.002 V respectively, which are very close to the predicted values. The drain bias currents of M
1
and M
3
were 44.23 A and 47.16 A respectively. This imbalance causes the differences in the drain currents
of output MOSFETs and hence the offset voltage. By scaling M
2
and M
3
to
the imbalances can be reduced considerably reducing the output offset current to 4.9 A.
515
i
D1
v
O
0
I
DQ1
, and i
D2
v
O
0
I
DQ2
,
v
SG1
V
DD
A( v
O
v
I
) , and v
GS2
A( v
O
v
I
) V
SS
.
Fig. 6.5.6: Push-pull inverting CMOS output amplifier with feedback to reduce the output
impedance and the transfer characteristics of a typical design.
Input voltage v
I
in V
c
u
r
r
e
n
t
s

i
n

m
A
-4.0 -2.0 0 2.0 4.0
-40
-20
0
20
40
i
D2
i
D1
i
O
i
o
R
L
+v
O
-V
SS
+V
DD
+v
I
M
1
M
2
i
D1
i
D2
+
-
A
+
-
A
Fig. 6.5.5: The transfer characteristics of the output stage designed in Example 6.8.
Input voltage v
I
in V
c
u
r
r
e
n
t
s

i
n

m
A
-2.5 -2.0 -1.5 -1.0 -0.5 0 1.0 1.5 2.0 2.5
-5.0
-2.5
2.5
5.0
0.5
0
i
D7
i
D8
i
O
One can increase the output resistance of the circuit of Fig. 6.5.4 using the cascode mirror at the
expense of decreased signal-swing for the output voltage. Feedback can be employed to the circuit of Fig.
6.5.4 to decrease the output resistance (Chapter 7). A circuit arrangement using such feedback is shown in
Fig. 6.5.6.
Assume that the output MOSFETs are biased with an I
Q
such that
where I
DQ1
and I
DQ2
are the quiescent bias currents, which are usually a fraction of the maximum load current.
From the circuit, it can be found that
Since v
O
is expected to be less than v
I
in the circuit, the MOSFETs never reach ohmic mode but they may
516
i
D1
K
1
V
DD
A( v
O
v
I
) V
t 1
2
, and i
D2
K
2
V
SS
A( v
O
v
I
) V
t 2
2
.
K
1
V
DD
A( v
O
v
I
) V
t 1
2
K
2
V
SS
A( v
O
v
I
) V
t 2
2
v
O
R
L
0.
v
O
2 A K R
L
2 V
DD
V
t 1
V
t 2
2 A K R
L
2 V
DD
V
t 1
V
t 2
1
v
I
K R
L
2 V
DD
V
t 1
V
t 2
V
t 2
V
t 1
2 A K R
L
2 V
DD
V
t 1
V
t 2
1
.
(6.5.8)
I
DQ1
K
1
V
DD
V
t 1
2
, and I
DQ2
K
2
V
DD
V
t 2
2
.
v
O
2 A R
L
K I
DQ1
KI
DQ2
2 A R
L
K I
DQ1
KI
DQ2
1
v
I
( I
DQ1
I
DQ2
) R
L
2 A R
L
K I
DQ1
KI
DQ2
1
,
A( g
m1
g
m2
) R
L
A( g
m1
g
m2
) R
L
1
v
I
I
O
R
L
A( g
m1
g
m2
) R
L
1
,
(6.5.9)
R
o
v
O
i
O
Q
1
A( g
m1
g
m2
)
,
(6.5.10)
reach cutoff depending the bias currents and the gate-to-source voltages. When the MOSFETs operate in the
pinch-off mode, the drain currents are given by
Since i
D1
= i
D2
+i
O
and i
O
= (v
O
/R
L
), we get
Assume that we choose the aspect ratios of the MOSFETs such that K
1
= K
2
= K and the supply voltages such
that V
SS
= V
DD
. Then, using these equalities in the above equation and solving for v
O
,
It is clear that v
O
has a linear relationship with v
I
except for the unavoidable but a small output offset due to
the difference in the threshold voltages of the MOSFETs. Since at v
I
= 0, v
O
is nearly zero, the zero-input bias
currents are
Using the above in (6.5.8),
where g
m1
and g
m2
are the small-signal transconductances of the MOSFETs. If [A(g
m1
+g
m2
)R
L
] 1, it is clear
that v
O
closely follows v
I
. Furthermore, we can show that, for small-signals, the output resistance of the circuit
is
which will be much lower than the output resistance without feedback.
As v
I
increases to a sufficiently large positive or negative value, one of these MOSFETs enters the
cutoff mode. For example, if v
I
> v
O
+ (V
SS
- V
t2
)/A, M
2
enters the cutoff, and i
O
= i
D1
. For such values of input,
the output current has square law characteristic, which increases the harmonic distortion. Furthermore, as v
O
increases to a large positive value, v
SD1
falls below the value to keep M
1
in the pinch-off mode, and M
1
may
enter the cut-off mode. Therefore, the increase in the value of i
O
is reduced. A similar situation occurs for the
negative inputs also, and M
2
may enter the cut-off mode for large negative inputs. However, we can choose
a larger value of I
DQ
to increase the linear range and reduce the distortion but at the risk of lower efficiency.
517
6.6: IC POWER OPERATIONAL AMPLIFIERS
IC op amps are versatile and find a very wide range of applications. This is the most important reason
for their popularity. Their output current, however, is limited to a few tens of mA, and their maximum power
output is also limited. For example, if an op amp, energized with a 15 V dc source, can supply a maximum
output current of 50 mA and the output is sinusoidal, the maximum output power is limited to 375 mW. This
amount of power is sufficient in most small-signal applications but it is quite low in power applications.
Current boost transistors are therefore added to increase their power handling capability, and they are then
called power operational amplifiers. There is a wide range of commercial IC power amplifiers. These
amplifiers essentially consist of a preamplifier with a Class-AB output stage or a simplified form of an op
amp with an internal feedback. The main difference between a normal op amp and a power operational
amplifier is in the power handling capability of the output power transistors. The IC power amplifiers
typically have a voltage gain of 30-50 dB with moderately high (but not as much as in a regular op amp) input
impedance. They can usually handle power output of 5-20 W without any current boost. Their current
handling capability can be increased by adding Class-AB power stages externally. IC power amplifiers can
be used for most audio and video power applications and are also available in the dual-in-line packages for
stereo systems. The application areas of the IC power op amps include phonographs, intercoms, alarms, AM-
FM radios, TV, etc.
An example of the IC power amplifier is LM384 from National Semiconductor corporation. This is
a 5-W audio power amplifier whose schematic is shown in Fig. 6.6.1. The input stage is a difference amplifier
(Chapter 6) with Darlington pairs at the input. The difference amplifier is biased by (R
1
+ R
2
) and R
3
. Q
2
is
a high gain CE-amplifier. The 10-pF capacitor provides frequency compensation to achieve adequate stability
margins (Chapter 9). The output of the CE-amplifier is fed to a Class-AB power amplifier with short-circuit
protection. R
3
also provides feedback, which reduces the closed-loop gain to about 50. LM384 can be used
with a maximum supply voltage of 28 V. It can be noted that Therefore, the [ R
3
/ ( R
1
R
2
) ] 0.5.
approximate value of the dc output voltage is about (V
s
/2), and there is a maximum symmetrical swing at the
output. If the amplifier is used with a single-ended supply, a coupling capacitor is required to remove the dc
at the output. One end of the input may be left open in the circuit because there is a dc path for the base-bias
currents through R
5
and R
6
. This power amplifier comes in a dual-in-line package. The total harmonic
distortion is only 0.25% when an output power of 4 W is delivered to an 8- load. If a 5-W power is drawn,
the THD increases to 10% because of the saturation of the output transistors.
The junction-to-ambient thermal resistance of LM384 is 85 C/W, and the maximum junction
temperature should be limited to 150 C. Therefore, if it is operated without a heat sink at a room temperature
518
Fig. 6.6.2: A typical application of the IC power amplifier LM384. (Courtesy of National
Semiconductor Corporation)
+
-
3,4,5,7,1
0,11,12
1 6
5 F
0.1 F
+22 V
8
0.1 F
2.7
500 F
V
I
N
10k
8
Fig. 6.6.1: The schematic of the IC power amplifier LM384 (Courtesy of National
semiconductor Corporation)
R
5
= 150k R
6
= 150k
1k
R
2
= 25k
R
1
= 25k
R
3
= 25k
+IN (2)
-IN (6)
GND (7)
BYPASS (1)
GND
(3,4,5,10,11,12)
V
s
(14)
Output
(8)
0.5
0.5
10 pF
Q
2
of 25 C, the internal power dissipation of the IC should be limited to 1.5 W. With a maximum efficiency of
about 70%, the output power should be limited to 1 W. With all the ground points soldered to a total copper
foil area of 6 in
2
on a printed circuit board, the thermal resistance can be reduced to 35 C/W, which increases
the maximum power output capability to 2.5 W. However, with a larger heat-sink, the output power can be
as high as 5 W. The type of heat sink to be used is suggested by the manufacturer in the application notes.
A typical audio application of LM384 is shown in Fig. 6.6.2.
519
Current Boosting
The power output from IC power amplifiers may not be sufficient in some applications. Greater
output power can be obtained with the use of external power transistors in Class-AB operation driven by IC
power amplifiers or operational amplifiers with feedback similar to the circuit shown in Fig. 6.3.6 or a
modification of this scheme. This is effectively achieved by increasing the maximum current that can be
drawn from the power supply, and this is why the process is called current boosting.
LM391 from National Semiconductor is an audio power driver, which is an example of this type of
amplifier. It can drive a Class-AB power stage in 10-100 W power amplifier circuits. Its supply voltage can
be as high as 50 V (100 V with a single ended supply). This also comes in dual-in-line package for stereo
applications. It has many applications, and the interested readers can find its applications from the
manufacturer's data book.
6.7: POWER MOSFETS
Power MOSFETs are available from several manufacturers, and they have distinct advantages over
the BJTs. Some of them are:
1. The transfer characteristic in the pinch-off mode is linear for currents over a small current range
(usually a fraction of an ampere) in some power MOSFETs. This means that the harmonic distortion
of the output will be negligible.
2. The breakdown voltages between the drain and source terminals may be as high as 500 V.
3. Power MOSFETs are majority carrier devices. Consequently, switching speeds are high. This enables
one to use power MOSFETs in the high frequency applications.
4. Because of the inherent high input impedance at the gate terminal, very small input power is required.
Of course, the power gain is extremely high.
5. For low voltage devices, r
DS
in the ohmic region is very low.
6. In the ohmic mode, r
DS
has positive temperature coefficient. However, in the pinch-off mode, there
is an operating region where the drain current has negative temperature coefficient, and the current
becomes self-limited, if the device heats up.
7. Power MOSFETs have extremely low noise figures.
Because of the above advantages, power MOSFETs are very popular and are widely used not only
in the output stages but also in switching power supplies, motor control, etc. Therefore, in this section, the
structures of power MOSFETs will be addressed. MOSFET power amplifiers can be developed by replacing
the BJTs with power MOSFETs in most circuits.
520
n
+
n
+
S oxide
p
Fig. 6.7.1: The structure of the V-groove
MOSFET with a short vertical
channel.
n
-
n
+
D
G
Fig. 6.7.2: The structure of the DMOS.
n
-
n
+
D
G
n
+
n
+
S
oxide
p
n
-
The cross-sectional view of the enhancement type MOSFET is shown in Section 4.1 (see Fig. 4.1.1).
The structure of Fig. 4.1.1 is not suitable for high current applications. To examine this, consider the
equations (4.2.4)-(4.2.8). To increase the current capacity, there should be an increase in the value of KP with
an increase in the width and a decrease in the length. Reducing the length results in the reduction of the
breakdown voltage between the drain and the source. Therefore, the conventional short-channel devices
cannot handle high voltages, which are typical of power circuits. However, with a change in the structure of
the MOSFET, it became possible to fabricate short-channel devices (with L 1 to 2 m) having high
breakdown voltages using double diffusion.
The initial concept used a V-groove MOSFET (VMOS) shown in Fig. 6.7.1. The drain terminal at
the bottom has a large area and can be placed in direct contact with the heat sink for removal of the heat
dissipated in the device. The fabrication starts with the n
+
-substrate. The n
-
-epitaxial region is grown on top
of the substrate. Then, two diffusions take place, the first with p-type and the second with n-type impurities.
The channel length is the vertical length of the p-region. However, the breakdown voltage depends on the
thickness and the resistivity of the n-epitaxial region. It is a lightly doped n
-
-region, and therefore, its
resistivity is high making it possible to have large breakdown voltages between the drain and source
terminals. The breakdown voltages can be many hundreds of volts. The low power MOSFETs described in
Chapter 4 are symmetrical between the drain and source, and therefore, they are interchangeable. However,
VMOS is unsymmetrical, and the drain and source terminals are not interchangeable. These devices can be
521
i
D
1
2
C
OX
WU
sat
v
GS
V
t
,
(5.7.1)
Fig. 6.7.3: The transfer characteristics of a typical DMOS in the pinch-off mode at various
temperatures.
i
D
v
GS
0
square law
Linear
-55 C
25 C
100 C
connected in parallel to increase the current capacity.
Due to the nonplanar structure of the VMOS, the cost of manufacturing was high, and for this reason,
this structure has been replaced by a vertical planar structure shown in Fig. 6.7.2. Because of the double
diffusion, this device is called the DMOS. This device operates in exactly same way as the VMOS. Again,
because of the n
-
-epitaxial region, the breakdown voltage between the drain and the source is high for the
DMOS. The transfer characteristic of a typical DMOS in the pinch-off mode is shown in Fig. 6.7.3. Note that,
for larger currents, i
D
-v
GS
characteristic is linear. At higher values of v
GS
, because of the short channel length,
the electric field in the channel becomes high. This causes the velocity of the charge carriers to reach an upper
limit (about 6 10
4
m/s for electrons in silicon), known as the velocity saturation. Under this condition in
the saturation mode, i
D
becomes proportional to (v
GS
- V
t
). In this region of operation, an approximate equation
for the drain current of a short-channel device is
where U
sat
is the saturated velocity. g
m
becomes independent of V
GSQ
in the linear region and is proportional
to the width of the device. This is in contrast to the low power device where g
m
is proportional to square root
of W. Since W is usually large in the high power devices, power MOSFETs have relatively high
transconductance values.
We observe from the transfer characteristics of Fig. 6.7.3 that there is a value of v
GS
at which the
temperature coefficient of i
D
is zero. At values of v
GS
above this point, the temperature coefficient is negative.
Therefore, if the MOSFET is operated above the zero temperature coefficient point, the device does not suffer
from the thermal runaway because of the self-limiting of the current. However, at low operating currents, the
522
thermal runaway can occur because of the positive temperature coefficient, and therefore, heat sinks are
necessary.
The third MOSFET structure that has been commercialized in the 1990s is the UMOS, which is
similar to VMOS. The name for this structure comes from the U-shaped groove formed in the gate area as
opposed V-groove in the VMOS. The fabrication of UMOS is also similar to that of VMOS. However,
UMOS has higher channel density than either of VMOS and DMOS, which causes a considerable reduction
in the on-resistance of the channel, which is in the order of Siliconix has lately introduced 0.05 m
2
.
power MOSFETs based on UMOS technology with an on-resistance of 0.01 -m
2
.
6.8: CONCLUSIONS
In this chapter, we discussed several types of power amplifiers, which are usually the output stages
in amplifier configurations. The detailed analyses of Class-A, B, and -AB power amplifiers were provided.
In most practical applications, the Class-B or Class-AB power amplifiers are used at the output stage because
of their high efficiencies. The distortion of the output signal is also of concern in power amplifiers, and in a
good high fidelity system, the THD should be less than 1%. Therefore, except in the inexpensive circuits,
Class-AB is preferred as a compromise between high fidelity and high efficiency. We also addressed the
power dissipation in the transistors along with the related thermal considerations with illustrative examples
in this chapter. Low power IC monolithic power amplifiers are available from many manufacturers. We
discussed some IC power amplifiers in Section 6.6.
BIBLIOGRAPHY
1. B. Jayant Baliga, Power Semiconductor Devices, PWS Publishing Company, Boston, MA, 1996.
PROBLEMS
SECTION 6.1
6.1. In Fig 6.1.1(a), assume that I
CQ
= 10 mA, and I
m
= 5 mA. What is the average power dissipated by
i
C
(t) in a 1-k resistor?
6.2. Repeat Problem 6.1, if I
CQ
= 5 mA, and I
m
= 5 mA.
6.3. In Fig. 6.1.1(b), if I
m
= 5 mA, what is the average power dissipated by i
C
6.4. In Fig 6.1.1(c), if I
CQ
= 0.5 mA, and I
m
= 5 mA, what is the average power dissipated by i
C
(t) in a 1-
k resistor?
6.5. In Fig. 6.1.1(b), assume that the waveform of i
C
(t) is triangular with a peak value of I
m
= What 5 mA.
523
Fig. P6.11.
+V
CC
Q
1 +v
I
M
2
-V
SS
i
D
i
L
R
L
+v
O
Fig. P6.12.
i
L
R
L
= 10 k
+v
O
-5 V
+5 V
M
1
M
2
+v
I
-3 V
is the average power dissipated by i
C
SECTION 6.2
6.6. In the circuit of Fig. 6.2.1, V
CC
= V
EE
= 9 V, R = R
L
= 1 k. All the transistors are identical. Assume
that V
BE
= 0.7 V, V
CES
0.3 V, and 1. What are the upper and lower limits of the output signal
and the corresponding inputs, if there should be no distortion due to saturation?
6.7. Repeat Problem 6.6, if the junction area of Q
3
is (a) half the junction areas of Q
1
and Q
2
; (b) twice
the junction areas of Q
1
and Q
2
.
6.8. Repeat Problem 6.6, if all the parameters remain the same except that R = 2 k.
6.9. Find the efficiency in Problem 6.6 including the power loss in R. Also find the power dissipation
ratings for the transistors. Assume that (a) the output is a sinusoid with an amplitude of 5 V and (b)
the output is a symmetrical triangular waveform having a peak-to-peak value of 10 V with a zero
average value.
6.10. Repeat Problem 6.9 if the output is a symmetrical square wave with an amplitude of and a zero 5 V
average.
6.11. The circuit shown in Fig. P6.11 uses a depletion-type MOSFET to realize the constant-current
source. Assume that V
CC
= V
SS
= 9 V, V
BE
= 0.7 V, and V
CES
= for the BJT. The MOSFET has 0.3 V
K = and V
t
= -2 V. (a) In the linear range of operation, what is the range of output 10 mA/ V
2
voltages obtained with R
L
= . (b) Repeat (a) if R
L
= 1 k. (c) What is the smallest value of R
L
, if the
output should be an undistorted sinusoidal signal? What is the corresponding efficiency?
6.12. The n-channel MOSFETs in the Class-A amplifier of Fig. P6.12 have (
n
C
OX
) = 51.17 A/V
2
, V
tn
=
524
0.7339 V,
n
= 0.03122 V
-1
,
n
= 0.4823 V
1/2
, and (2
f
) = 0.7 V. The aspect ratios are (W/L)
1
= (20/2)
and (W/L)
2
= (80/2). Assuming that M
1
can be driven by an input v
I
ranging from +1 V to +5 V, find
the peak-to-peak output signal.
D6.13. In the circuit of Fig. 6.2.1, it is desired to have an undistorted sinusoidal output with a minimum
amplitude of 8.5 V. Assume that all BJTs are identical with V
BE
= 0.7 V and V
CES
= 0.3 V. Select the
power supply voltage and the value of R to establish the appropriate bias current I, if R
L
= 1 k.
Determine the efficiency of your design including the power dissipation in R, if the output is a
sinusoidal signal with an amplitude of 8.5 V. Also obtain the power dissipation ratings for the
transistors.
D6.14. R
L
= 100 , a = (n
1
/n
2
) = 3, and v
O
(t) is a sinusoidal signal having an amplitude of 3 V in the circuit
of Fig. 6.2.3(a). Find the required dc bias current I
CQ
. Obtain the values of R
B1
and R
B2
to establish
this bias current. Find the efficiency of your design including the losses in R
B1
and R
B2
.
6.15. A power transistor operating at an ambient temperature of 50 C has a thermal resistance
JA
of
1 C/W and dissipates 50 W. What is the junction temperature?
6.16. A 100-W power transistor has its maximum junction temperature of 150 C. Its thermal resistance
JC
is 1.5 C/W. If the case temperature should not exceed 50 C, what is the maximum power
dissipation allowed? If its power dissipation is reduced to half the level, what could be the maximum
case temperature?
D6.17. A power transistor has T
Jmax
= 150 C and
JC
= 1.5 C/W. It operates with a heat sink for which
CS
= 0.5 C/W and
SA
= 1 C/W for each cm of heat sink length. The overall
SA
is inversely proportional
to the heat sink length. For example, if the heat sink length is 10 cm, then
SA
= 0.1 C/W. If the
transistor dissipates 50 W, the ambient temperature should not exceed 25 C. What should be length
of the heat sink? If the heat sink length is doubled, how much increase can we achieve in the power
dissipation level for the same ambient temperature?
SECTION 6.3
6.18. If V
CC
= 15 V, R
L
= 100 , and v
O
(t) is a sinusoidal signal with an amplitude of 15 V in the circuit
of Fig. 6.3.1, find the load power and the power drawn from the power supplies. Determine the
efficiency and the power dissipation ratings for the transistors.
6.19. Repeat Problem 6.18, if v
O
(t) = 10sin(t).
D6.20. Design the circuit of Fig. 6.3.1 to deliver an output power of 50 W into a 4- load, if the output
signal is a sinusoid. The power supply voltage should be at least 2 V more than the peak amplitude
of the sinusoid to avoid distortion due to saturation. Find the requirement of the dc power supply.
Determine the peak current through the transistors, power dissipation ratings for the transistor, and
525
the efficiency of your design.
6.21. In the circuit of Fig. 6.3.1, if the output is a symmetrical triangular waveform with a peak to peak
value of 2V
m
and zero average, find the load power, supply power, and the maximum attainable
efficiency. For what value of V
m
, will the power dissipation in the BJTs reach maximum? What is the
efficiency of the circuit under this condition?
6.22. In Problem 6.18, assume that V
= 0.7 V. Find the amplitude of the fundamental component and the

percentage of THD.
6.23. If A
d
= 1000 and V
= 0.7 V in the circuit of Fig. 6.3.6, sketch the transfer characteristic. Assume that
the output saturates at V
CC
.
6.24. In the Class-B amplifier using MOSFETs shown in Fig. P6.24, V
DD
= V
SS
= 5 V. The fundamental
parameters of the MOSFETs are the same as those in Example 6.7. Find the transfer characteristics
if (a) R
L
= and (b) R
L
= 1 k. Are they linear? Identify the dead zone. Verify your results using
PSPICE simulation.
SECTION 6.4
D6.25. I
BIAS
= 0.1 mA in the circuit of Fig. 6.4.1. If the output resistance seen by the load should be less than
10 , what should be the minimum value of n?
D6.26. V
CC
= 15 V, I
BIAS
= 0.5 mA, n = 2, R
L
= 100 , V
A1
= 100 V, and
Q1
= 100 in the circuit of Fig. 6.4.1.
(a) What is the value of I
CQ
? (b) What are the maximum positive and negative output signal levels
without saturation being reached? (c) What is minimum value of I
BIAS
to achieve equal values for
positive and negative peaks? (d) Repeat (c), if the current through the diodes should be at least 1 mA.
D6.27. The Class-AB power amplifier of Fig. 6.4.1 should deliver output into a load of R
L
= 50 W 4 .
n = 3 and the output is sinusoidal. The power supply voltage should be at least 2 V more than the
peak amplitude of the sinusoid. The diode current should be at least 1 mA. V
A1
, and
Q1
= 50. Find
the power supply requirement and the value of I
BIAS
. Determine the efficiency of your design and the
power dissipation ratings of the transistors.
6.28. In the circuit of Fig. 6.4.4, R
1
= R
2
= 1 k, V
CC
= 15 V, and R
L
= 100 . V
BE3
= 0.6 V @ I
C3
= 1 mA.
Similarly, V
BE1
= 0.6 V @ I
C1
= 100 mA.
Q1
= 100. Q
1
and Q
2
are matched. What is the minimum
value of I
BIAS
for a maximum output signal?
D6.29. In the circuit of Fig. 6.4.6, R
1
=R
2
=1 k, V
CC
= 15 V, I
BIAS
= 4 mA, and R
L
= The transistors, 100 .
Q
3
, Q
4
, and Q
5
have . In these transistors, V
BE
= 0.6 V @ I
C
= 1 mA. The output transistors Q
1
and Q
2
have = 100. If the load current exceeds 150 mA, the power transistors Q
1
and Q
2
should shut
down. Find the required values for R
3
and R
4
. Verify your design using PSPICE simulation.
526
Fig. P6.30.
v
i
+
-
i
o
v
o
(r
o1
r
o2
)
+
-
1v
i
1
g
m1
+

g
m2
+
-
R
o
1
g
mb1
+

g
mb2
R
L
Fig. P6.24.
i
L
i
D2
R
L
+v
O
-V
SS
+V
DD
M
1
M
2
+v
I
SECTION 6.5
D6.30. Assuming the diode-connected MOSFETs to be short-circuits in the circuit of Fig. 6.5.1, show that
the small-signal equivalent circuit of Fig. P6.30 can be used to find the primary parameters, such as
the voltage gain, of this Class-AB amplifier. Find the voltage gain and the output resistance in the
design Example 6.7.
6.31. The n-channel MOSFETs in the circuit of Fig. 6.5.1 have KP = 50 A/V
2
, V
t
= 1 V,
n
= 0.025 V
-1
,
and
n
= 0.5 V
1/2
. The parameters of the p-channel MOSFETs are: KP = 17 A/V
2
, V
t
= -1 V,
p
=
0.03 V
-1
, and
n
= 0.6 V
1/2
. (2
f
) = 0.7 V in both cases. While all MOSFETs have the same length,
M
1
and M
2
have 20-times the width of M
3
and M
4
respectively. R
L
= 1 k. It is desired to establish
I
DQ1
= I
DQ2
= 4 mA. R
o
should be less than 100 for small signals. What should be the value of I
BIAS
?
Find the aspect ratios of the transistors. Verify your design using PSPICE simulation.

Chapter 6: Power Amplifiers and Output Stages: Microelectronics: Analysis and Design© January 9, 2003 Sundaram Natarajan

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is the cut-in voltage, and

if the op amp is not used. Let us now relate

is the cut-in voltage of the base-emitter junctions of Q

(about 0.5 V), and therefore, Q

= 0.7 V. Find the amplitude of the fundamental component and the

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