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Introduction to VHDL
Code Structure

One important way of representing a digital logic circuit is through the use of a hardware description language.
A hardware description language allows you to describe the desired behavior of your circuit using text, and then
simulate the operation of your circuit.

Although lines in a hardware description language look similar to lines of code written in a programming
language (such as C++or J ava), there is a critical distinction: lines of code in a programming language are
executed line by line sequentially without any reference to a time axis. Hardware description languages, on the
other hand, attempt to model actual circuit operation, which may be very much time dependent. Specifically,
lines of code in VHDL can execute concurrently or sequentially, depending on the scenario (as we will see).
For this reason, we will normally say Look at this VHDL code instead of Look at this VHDL program.

By looking at simulation results based on our hardware description, we can spot design flaws before
implementing hardware (or even drawing a schematic).

It is important to emphasize again that for all but the simplest designs, you always want to

Simulate a circuit before building it. After verifying your design through simulation, then you build the
physical circuit.

The two major hardware description languages in use today are both IEEE standards:

Verilog (developed by Gateway, now owned by Cadence Design)
VHDL (developed by the Department of Defense)

Verilog has the reputation for being somewhat easier to learn. Thus, guess which one we are going to use?

VHDL (welcome to the DoD!)

VHDL stands for Very high-speed integrated circuit Hardware Description Language. The language has a
formal syntax that must be followed.
VHDL code has three main sections:

From Pedroni, Circuit Design with VHDL, MIT Press, 2004

A template for a vhdl file is shown below (not a working file).

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The library declarations: This section lists the libraries of code that others have already written that you would
like to use in your own code. We will have this section read:

LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;

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This looks cryptic, but basically it makes available to you a set of code that you can freely use in your own
design. For now, just consider this an opening stamp that you place on your code.

Note the semicolons in the two lines above. They are not optional.

The semicolon indicates the end of a statement.

As we write VHDL, we may want to include comments on our codebasically notes to ourselves that we do
not want to be viewed as part of the intrinsic design. We can add comment to our code by using a double-dash.
For example, the following library declaration will be treated exactly the same as the one above:

LI BRARY i eee;
USE i eee. st d_l ogi c_1164. al l ;
- - Thi s i s exci t i ng st uf f !

Comments can be placed in the same line as code, such as:

LI BRARY i eee; - - EC262 = Fun Ti mes
USE i eee. st d_l ogi c_1164. al l ;

The entity section: This section specifies the name of our design, and all of its inputs and outputs. What the
design actually does to the inputs to arrive at the output is NOT of interest in this section.

The basic format for the entity section using just input bits and output bits is:

ENTI TY entity_name I S
PORT(
i nput _1, i nput _2, , i nput _n: I N BI T;

out put _1, out put _2, , out put _m: OUT BI T
) ;
END entity_name ;


After the word ent i t y is the entity name that you pick. Can you pick any name?

Entity names (in fact, all names that you choose to represent items in your code) must begin with a
letter, and then can consist of letters, numbers, or the underscore character.

Example. Which of the following are valid names that I can choose in VHDL?

1. EC262
2. Sl i pper y_f i sh
3. Pr oj ect _25
4. Buf f _chi cks
5. 2bae_sur pr i se_qui z
6. _bae_sur pr i se_qui z
7. bae_sur pr i se_qui z_
8. bae__sur pr i se_qui z
9. di sconnect
10. ec262 (if I am already using number 1 above)

1, 2, 3 and 4 are okay.

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5 is bad: cant start with a number.

6 is bad: cant start with an underscore.

7 is bad did I mention that it cant end with an underscore

8 is bad did I mention that it cant have more than one underscore consecutively

9 is bad did I mention that there are about 100 words that have special meaning in VHDL and cannot
be used as names for your choosing.

10 is potentially bad did I mention that VHDL is not case sensitive, so EC242 and ec242 will refer to
the same thing.

Appendix E in your text lists all the VHDL reserved words.

Between the open and close parenthesis we list all of our inputs and outputs.

Look at the line of code:

i nput _1, i nput _2, , i nput _n: I N BI T;

Consider this line to be two sections, divided at the colon. Everything to the left of the colon is a list of names,
and everything to the right of the colon describes what those names are to function as. So, if we were to have
the line:

a, b : I N BI T ;

that would mean that my entity is to have two ports named a and b that are to function as input bits.

Note that BIT is a data type. Other data types are listed in the table below.


From Pedroni, Circuit Design with VHDL, MIT Press, 2004


The architecture section: This section tells how the entity that you named above actually carries out what you
intended it to do. How the outputs are derived from the inputs is detailed in this section.
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The basic format for the architecture section is:

ARCHI TECTURE arch_name OF entity_name I S
BEGI N

the statements that define the behavior ;

END arch_name ;
Example

To ground this in an actual example, lets write VHDL code to implement lab 1. Recall that you designed and
implemented a circuit for the following logic function,
F(A,B,C) = AB + A'BC' + BC

The circuit diagram for this function is:



Library declaration:




Entity section:

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Note again that the entity section is just a description of the inputs and outputsthe pins of the circuit.
Architecture section:




Notice that strange symbol: a less than sign, followed by an equal sign, with no space in between: <=. That
symbol is the assignment operator. So, the statement

F <= ( A AND B) OR ( NOT A AND B AND NOT C) OR ( B AND C) ;

should be read:

Compute the value of (AB + A'BC' + BC ) and then assign that result to F.

Other operators that can be used in the architecture section are shown in the table below.


From Pedroni, Circuit Design with VHDL, MIT Press, 2004
Note: syntax for ;

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A complete vhdl file for the example above:




Example (from text)

To ground this in another example, suppose we wanted to implement a full adder using VHDL. Recall the full
adder, which you designed about a year or so ago, had two input bits and a carry-in bit, and produced a sum bit
and a carry-out bit, using the logic below:

The Boolean expression for the carry-out bit is AC AB BC + + and the logic circuit for the carry-out bit is:
A
B
C
Carry


Entity name
Architecture
name
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The sum bit can be implemented by two XORs.
A
B
C

So, lets complete the three sections of our VHDL code: The library declarations, the entity section and the
architecture section.







Solution:









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Note again that the architecture section describes how the circuit is supposed to function.

Save your VHDL code in a file named full_adder.vhd.



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Representing Values in VHDL

Representing Decimal (Base-10) Values in VHDL

Integers are represented in the usual way. For instance, the integer fifty seven is represented by:

57

and the integer negative five is represented by

- 5

We can also use exponential notation if desired. For instance, the number 7000 can be represented as

7E3

Question: Could 7000 be represented by 7e3?

Yes, VHDL is not case sensitive.

Representing Bits in VHDL

A bit is surrounded by single quotes, with the two options being 0 and 1

Representing Multi-Bit Quantities in VHDL

Multi-bit quantities are surrounded by double quotes. A collection of bits is called a bit vector. For example, in
VHDL, the term 011010 is

26

while the term 011010 would represent

eleven thousand and ten

Representing Hexadecimal Quantities in VHDL

To represent a hexadecimal quantity, place the number in quotes and precede it with an X. For example, the
term X1F would represent the decimal value of

31

Using VHDL, how would you represent the base-10 number 14 in hexadecimal.

XE

VHDL Standard Data Types

When we want to use a signal x (an input to a circuit) or when we want to use a variable x, we have to tell
VHDL what the signal or variable is.


Is x a single bit?
Or is x a group of two bits (to be applied as the control signals for a 2-4 multiplexer)?
Or is x a group of four bits (to be applied as the input to a 4-16 decoder)?



The point: We have to tell VHDL what x is supposed to be.

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Put another way, we have to tell VHDL xs type.

The STD_LOGI C ( or BI T) type A signal of this type will be just a bit, which can take on the values of 0
or 1. Examples:

a , b: I N STD_LOGI C;
x : OUT STD_LOGI C_VECTOR;

What operations can we perform on bits?

NOT, AND, OR
NAND, NOR, XOR
assignment ( <=)
Comparison: =, /= , > , <

Examples (using a, b and x from above):

Write a VHDL statement that assigns a the value of 1.

a <= 1 ;

Write a VHDL statement that assigns b a value equal to the negation of a.

b <= NOT a ;

The STD_LOGIC_VECTOR (or BIT_VECTOR) type This is a vector, or a collection, of bits. Examples:

d_out : OUT BI T_VECTOR ( 7 DOWNTO 0 ) ;

e_i n , x_i n : I N STD_LOGI C_VECTOR ( 7 DOWNTO 0) ;

In the above statements, d_out , e_i n and x_i n are all eight-bit quantities.
What operations can we perform on bit vectors?

NOT, AND, OR
NAND, NOR, XOR
assignment ( <=)
Comparison: =, /= , > , <
Shifting operations:
SLL (shift left filling in a 0 on the right)
SRL (shift right filling in a 0 on the left)
SLA (shift left replicating the right-most bit)
SRL (shift right filling replicating the left-most bit)
ROL (circular shift to the left)
ROR (circular shift to the right)
Concatenation: &

Example: Using d_out , e_i n and x_i n from above)

Assign e_i n the value 11000001

e_i n <= 11000001 ;

Assign d_out the value of the exclusive-or of e_i n and x_i n

d_out <= e_i n XOR x_i n ;

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Example We can select individual bits from a vector by using parenthesis. For example, a multiplexer with four
inputs (x0, x1, x2, x3) and a two-bit selector can be implemented as follows:

LI BRARY i eee ;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ENTI TY mux I S
PORT(
x0, x1 , x2, x3 : I N STD_LOGI C ;
sel : I N STD_LOGI C_VECTOR ( 1 DOWNTO 0 ) ;
y : OUT STD_LOGI C
) ;
END mux;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ARCHI TECTURE mux_oper at i on OF mux I S
BEGI N
Y <= ( NOT sel ( 1) AND NOT sel ( 0) AND x0 )

OR

( NOT sel ( 1) AND sel ( 0) AND x1 )

OR

( sel ( 1) AND NOT sel ( 0) AND x2 )

OR

( sel ( 1) AND sel ( 0) AND x3 )

END mux_oper at i on;


The INTEGER type A signal of this type will be an integer. Examples:

a, b : I N I NTEGER RANGE 0 TO 15 ;
c : I N I NTEGER RANGE - 31 TO 31 ;
d : OUT I NTEGER RANGE 0 TO 31 ;

How many bits are used to represent the ports a, b,, c and d above?

4, 4, 6 and 5, respectively

What operations can we perform on integers?

Comparison: =, /= , > , <
Arithmetic: +, - , *, /, **


Example The inputs to the circuit shown below are two values a and b that each may take on any integer
between 0 and 7 (inclusive). The output sum should be the addition of a and b. Write VHDL code to
implement this circuit.


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LI BRARY i eee ;
USE i eee. st d_l ogi c_1164. al l ;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

ENTI TY my_ci r cui t I S
PORT(
a, b : I N I NTEGER RANGE 0 TO 7 ;
sum: OUT I NTEGER RANGE 0 TO 15
) ;
END my_ci r cui t ;

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

ARCHI TECTURE ci r cui t OF my_ci r cui t I S
BEGI N
sum<= a + b ;
END ci r cui t ;


Signed and Unsigned Types

Type Value Range Notes
UNSI GNED 0 t o 2
N
- 1
UNSI GNED - 2
N- 1
t o 2
N- 1
- 1 2 s compl ement number

Example:
SI GNAL a: UNSI GNED ( 3 downt o 0) ; - - a 4- bi t unsi gned number
SI GNAL b: SI GNED ( 3 downt o 0) ; - - a 4- bi t si gned number
SI GNAL c: STD_LOGI C_VECTOR ( 3 downt o 0) ; - - a 4- bi t unsi gned number

a <= 1111; - - 15 i n deci mal
b <= 1111; - - - 1 i n deci mal
A <= 1111; - - 15 i n deci mal

We can declare values to be unsigned or signed. Signed numbers use the normal twos complement notation.
For signed numbers, we must include the library ieee.numeric_std.all or ieee.std_logic_arith.all, but
not both.

Example: The program below implements a multiplier. If the decimal value of a is 13 and the decimal value of
b is 2, what will be the value of y (as 8 bits) after this section of code executes?

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(13)(2) =26, so y will be 00011010




If the decimal value of a is -3 and the decimal value of b is 2, what will be the value of y (as 8 bits) after this
section of code executes?

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Now a has the value of - 3. So y will have the value of - 6.
In eight bits, - 6 is 11111010