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Solid-state Semiconductor Physics

Diode Circuit Analysis and Design


Dr.-Ing. Wilfred Mwema
University of Nairobi
March 2012
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 1 / 102
The DC loadline
Consider the diode circuit of Fig. DCdiodcct
V
DC
V
o
V
d
R
L
I
Fig. DCdiodcct DC diode circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 2 / 102
The DC loadline
By KVL, we can write
V
DC
V
d
IR
L
= 0
or
I =
V
DC
V
d
R
L
=
V
DC
R
L

V
d
R
L
For V
d
= 0,
I = I
max
=
V
DC
R
L
and for V
d
= V
DC
, I = I
min
= 0
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 3 / 102
The DC loadline
We can plot I against V
d
to obtain a straight line with a slope
1/R
L
and passing through I
max
and V
d
= V
DC
This line is referred to as the circuit loadline and indicates the current
through the circuit as the voltage across the diode is varied
Diodes are non-linear devices however with a static (DC) I-V
characteristic given by the Shockley ideal diode equation which we
modify for practical devices
I = I
s
_
exp
_
q
kT
V
d
_
1
_
where we have assumed V
d
drops entirely across the junction, i.e.
voltage drop across the neutral regions of the diode is negligible
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 4 / 102
The DC loadline
The DC loadline of the simple circuit is shown in Fig. DClline
V
d
V
DC
V
Q
I
max
I
Q
I
Q
loadline
static characteristic
Fig. DClline DC diode circuit loadline
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 5 / 102
The DC loadline
The point of intersection between the loadline and the static diode
I-V characteristic indicates the current owing through the circuit
This point is referred to as the quiescent operating point (Q-point) of
the circuit
This is the direct current that would ow when no time-varying
signals are impressed on the circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 6 / 102
Diode series connection - voltage sharing
When the diode is required to block a reverse voltage larger than its
rated reverse breakdown voltage, two or more diodes can be
connected in series to share this voltage
The voltage sharing will not be identical since no two diodes have
exactly the same static I-V characteristics
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 7 / 102
Diode series connection - voltage sharing
Equal sharing can be enforced by connected large resistors in parallel
with each diode as shown in Fig. Serdiod
V
DC
V
o
V
Q2
V
Q1
R
L
R
2
R
1
I
I
1
I
2
D
1
D
2
Fig. Serdiod Diode series connection for enhanced reverse blocking
capability
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 8 / 102
Diode series connection - voltage sharing
Let the static I-V charactersitics of the two diodes be as shown in Fig.
Serdiodchara
V
d
V
Q1
V
Q2
I
max
I
Q
I
D
1
D
2
Fig. Serdiodchara DC I-V characterstics for diode series connection
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 9 / 102
Diode series connection - voltage sharing
The current owing through the diodes without the resistors R
1
and
R
2
is the same so that we can write
I
Q
= I
s1
_
exp
_
q

1
kT
V
Q1
_
1
_
= I
s2
_
exp
_
q

2
kT
V
Q2
_
1
_
If
1
,=
2
and I
s1
,= I
s2
, V
Q1
and V
Q2
cannot be equal for the
current through the two diodes to be equal
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 10 / 102
Diode series connection - voltage sharing
The diodes will not share the reverse bias voltage equally therefore
Connecting large resistors R
1
and R
2
will correct the sharing since,
with the resistors in circuit, we have
I = I
s1
_
exp
_
q

1
kT
V
Q1
_
1
_
+
V
Q1
R
1
= I
s2
_
exp
_
q

2
kT
V
Q2
_
1
_
+
V
Q2
R
2
or
I
D1
+
V
Q1
R
1
= I
D2
+
V
Q2
R
2
=
V
Q1
R
1

V
Q2
R
2
= I
D1
I
D2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 11 / 102
Diode series connection - voltage sharing
We have
V
Q1
= IR
1
I
D1
R
1
V
Q2
= IR
2
I
D2
R
2
Hence
V
Q1
V
Q2
= V = I (R
1
R
2
) I
D1
R
2
+I
D2
R
2
A careful choice of the resistors R
1
and R
2
will make V ~ 0 and the
diodes will be forced to share the voltage drop equally
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 12 / 102
Diode parallel connection - current sharing
In some applications, the load current required may be higher the
maximum rated diode current I
max
In such cases, two or more diodes can be connected in parallel to
share the load current
For practictical diodes, the current sharing will not be equal due to
dierences in the diode I-V characteristics
We have
I = I
Q1
+I
Q2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 13 / 102
Diode parallel connection - current sharing
Equal current sharing can be enforced by connecting small resistors in
series with each diode as shown in in Fig. Paradiod
V
DC
V
o
V
Q2
V
Q1
R
L
R
2
R
1
I
I
Q2
I
Q1
D
1
D
2
Fig. Paradiod Diode parallel conection for enhanced current handling
capability
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 14 / 102
Diode parallel connection - current sharing
With the resistors short-circuited, the diodes are forced to operated at
the same quiescent voltage as shown in Fig. Paradiodchara
V
d
V
Q
I
Q1
I
Q2
I
D
1
D
2
Fig. Paradiodchara I-V characteristics for parallel diode connection
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 15 / 102
Diode parallel connection - current sharing
The circuit current is thus
I = I
s1
_
exp
_
q

1
kT
V
Q
_
1
_
+I
s2
_
exp
_
q

2
kT
V
Q
_
1
_
= I
Q1
+I
Q2
In general, I
Q1
,= I
Q2
with the diode requiring a smaller V
Q
carrying
most of the current
To correct the current sharing, the small resistors R
1
and R
2
force the
diodes to operate at dieren junction voltages
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 16 / 102
Diode parallel connection - current sharing
We can therefore write

1
kT
q
ln
I
Q1
I
s1

2
kT
q
ln
I
Q2
I
s2
= I
Q2
R
2
I
Q1
R
1
The correct choice of R
1
and R
2
will force I
Q1
= I
D2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 17 / 102
The dynamic loadline
If the we impress a time-varying voltage on the diode circuit, the
current through the diode will obey a dierent I-V characteristic from
the static one
This is due to the nite time required by the excess charge prole to
readjust to the new voltage across the junction
The instantaneous value of the diode current is determined by
plotting the I-V values at each value of the bias voltage to obtain the
dynamic I-V characteristic
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 18 / 102
The dynamic loadline
Fig. AClline shows a typical dynamic characteristic of a diode
V
d
V
Q
I
Q
I
static curve
dynamic curve
Fig. AClline The dynamic loadline of a diode
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 19 / 102
The dynamic loadline
If the bias voltage changes by V, the current through the diode
adjusts to
I
Q
+I = I
s
_
exp
_
q
kT
(V
Q
+V)
_
1
_
~ I
s
exp
_
q
kT
(V
Q
+V)
_
when V
Q
>> kT/q
This can be rewritten as
I
Q
+I ~ I
s
exp
_
q
kT
V
Q
_
exp
_
q
kT
V
_
= I
Q
exp
_
q
kT
V
_
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 20 / 102
The dynamic loadline
If V << kT/q we can expand the exponential in a McClaurins
series as
I
Q
+I ~ I
Q
_
1 +
q
kT
V +
1
2!
_
q
kT
V
_
2
+ . . .
_
or
I
Q
+I ~ I
Q
+
q
kT
I
Q
V
where assumption that V << kT/q allows us to keep only the
linear terms of the expansion
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 21 / 102
The dynamic loadline
Hence
I ~
q
kT
I
Q
V =
I
V

=
1
r
f
=
q
kT
I
Q
the reciprocal of the forward bias dynamic resistance of the diode
Another important characteristic is one relating the output current or
voltage to the input voltage impressed across the diode
This is referred to as the transfer function of the diode and since
v
o
(t) = i (t) R
L
the transfer function has the same shape as the dynamic characteristic
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 22 / 102
Half-wave rectier
Consider the AC circuit shown in Fig. HFrect
Fig. HFrect A half-wave diode rectier circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 23 / 102
Half-wave rectier
Let the secondary voltage applied to the diode be given by
v
s
(t) = V
m
sin t = V
m
sin
where = t
When v
s
(t) > V

, the diode can be replaced by its forward bias


dynamic resistance r
f
assuming a piece-wise linear diode model
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 24 / 102
Half-wave rectier
Fig. Pwiselin shows the piece-wise linear model of the rectier
v
o
v
s
v
d
R
L
r
f
i
Fig. Pwiselin Piece-wise linear equivalent circuit of a half-wave
rectier
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 25 / 102
Half-wave rectier
The current through the load resistance is thus
i (t) =
V
m
sin V

R
L
+r
f
, v
s
(t) > V

= I
s
~ 0, v
s
(t) < V

where we have assumed the reverse bias dynamic resistance r


r

Because of a non-zero V

, the is a time delay before the signicant


forward current starts to ow
This is represented by an angle

referred to as the cut-in angle


Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 26 / 102
Half-wave rectier
Fig. HFW illustrates the waveform of the load current as time evolves
i(t)
I
m
-I
s
t

Fig. HFW Load current waveformin a half-wave rectier


Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 27 / 102
Half-wave rectier
At the cut-in angle,
i (t) =
V
m
sin

R
L
r
f
= 0
Hence, the cut-in angle is given by

= sin
1
V

V
m
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 28 / 102
Half-wave rectier
In power rectier applications, V

<< V
m
, hence

~
V

V
m
0
We can therefore approximate the load current as
i (t) =
V
m
sin
R
L
+r
f
, 0 _ _
~ 0, _ _ 2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 29 / 102
Half-wave rectier
The average (DC) current through the load is given by
I
DC
=
1
T
T
_
0
i (t) dt =
1
2
2
_
0
i () d
or
I
DC
=
1
2
V
m
R
L
+r
f

_
0
sin d =
1
R
L
+r
f
V
m

=
I
m

where
I
m
=
V
m
R
L
+r
f
The DC voltage across the load is hence
V
DC
= I
DC
R
L
=
I
m

R
L
=
R
L
R
L
+r
f
V
m

Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 30 / 102
Half-wave rectier
Thus V
m
/ can be regarded as the open-circuit voltage of a
Thevenins source and r
f
its source resistance as shown in Fig.
HFWM
v
d
R
L
r
f
i
V
DC
V /
m

ig. HFWM Thevenins equivalent source representation of a half-wave
rectier
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 31 / 102
Half-wave rectier
Since V
DC
< V
m
/ when R
L
< , V
DC
decreases with increasing
I
DC
This is known as voltage supply regulation and dened as
regulation =
V
DC,no load
V
DC,load
V
DC,load
The load carries an AC current with an rms value given by
I
rms
=

_
1
2
I
2
m

_
0
sin
2
d =

_
1
2
I
2
m

_
0
_
1
2

1
2
cos 2
_
d
or
I
rms
=
_
1
2
I
2
m

2
=
I
m
2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 32 / 102
Half-wave rectier
The ratio I
rms
/I
DC
for a rectier circuit is known as the form factor of
the waveform
For the half-wave rectier, the form factor is given by
I
rms
I
DC
=

2
~ 1, 57
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 33 / 102
Half-wave rectier
The voltage across the diode is given by
v
d
(t) = I
m
r
f
sin , 0 _ _
= V
m
sin , _ _ 2
Hence, the DC voltage across the diode is
V
D
=
1
2
_
_
_
I
m
r
f

_
0
sin d +V
m
2
_

sin d
_
_
_
or
V
D
=
1
2
_
I
m
r
f
[cos ]

0
+V
m
[cos ]
2

_
=
1
2
2I
m
r
f
2V
m

Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 34 / 102
Half-wave rectier
Hence
V
D
=
I
m

r
f

V
m

=
I
m

r
f
(R
L
+r
f
) =
I
m

R
L
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 35 / 102
Half-wave rectier
The rms voltage across the diode is given by
V
d
=

_
1
2
(I
m
r
f
)
2

_
0
sin
2
d +
1
2
V
2
m
2
_

sin
2
d
or
V
d
=
_
(I
m
r
f
)
2
4
+
V
2
m
4
=
I
m
2
_
r
2
f
+ (R
L
+r
f
)
2
=
I
m
2
R
L
_
_
1 +
r
f
R
L
_
2
+
_
r
f
R
L
_
2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 36 / 102
Half-wave rectier
Or
V
d
= I
rms
R
L
_
_
1 +
r
f
R
L
_
2
+
_
r
f
R
L
_
2
The half-wave rectier has a large rms current and is wasteful since
only half the cycle does not ow through the load
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 37 / 102
Full-wave rectier
This can be corrected using a full-wave rectier circuits shown Fig.
FWR
R
L
R
L
i
L
i
L
V
m
V
m
V
m
v
L
v
L
n:1
n:1
n:1
n:1
Mains
Mains
i
1
D
2
D
4
i
2
D
2
DOUBLE HALF-WAVE FULL-WAVE RECTIFIER DIODE BRIDGE FULL-WAVE RECTIFIER
Fig. FWR Full-wave rectier circuits
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 38 / 102
Full-wave rectier
The full-wave rectier is a true mathematical rectication and we have
I
DC
=
I
m

_
0
sin d = 2
I
m

where as before
I
m
=
V
m
R
L
+r
f
and
I
m
=
V
m
R
L
+ 2r
f
in the double half-wave and rectier bridge full-wave rectiers resp.
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 39 / 102
Full-wave rectier
In both circuits, the rms load current is given by

_
1

I
2
m

_
0
sin
2
d =
I
m
_
2
and the form factor by
I
rms
I
DC
=
I
m
_
2
1
2I
m
/
=

2
_
2
~ 1, 11
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 40 / 102
Full-wave rectier
The double half-wave rectier places stringent requirements on the
peak reverse voltage the diodes must withstand which in this case is
2V
m
In a given application, the diodes must have a reverse breakdown
voltage
V
B
_ 2V
m
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 41 / 102
Full-wave rectier
Note that for the bridge circuit, the peak reverse voltage on each
diode is V
m
and hence V
B
_ V
m
The voltage regulation is slightly worse for the bridge circuit since the
source resistance is r
f
and 2r
f
in the double half-wave and bridge
full-wave rectiers resp.
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 42 / 102
Filtering
The rms component in the output voltage causes signicant ripple
In many applications such as radio and TV receivers and ampliers,
the ripple is not desirable and is usually removed (ltered out)
This ltering can be acomplished using a capacitor in shunt with the
load or in some cases, including a series inductor when load current is
expected to be high
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 43 / 102
Filtering
Consider the half-wave rectier circuit of Fig. CFLT driving a
capacitor C in parallel with the load resistor R
L
Fig. CFLT Half-wave rectier circuit with capacitor lter
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 44 / 102
Filtering
If we ignore the diode forward drop (~ 0, 6 V) for Si diodes, the
secondary voltage is impressed directly on the load so that
v
o
(t) = V
m
sin t, 0 _ t _
The capacitor thus charges to V
m
in the positive half-cycle
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 45 / 102
Filtering
When the diode turns of as v
s
(t) goes below the capacitor voltage,
capacitor starts to discharge through the load until the next positive
half cycle
The discharge rate is rated to the product R
L
C known as the time
constant of the circuit
The point at which the diode starts to conduct is referred to as the
cut-in point and where it stops conduction is the cut-out point
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 46 / 102
Filtering
Fig. CIO shows the waveform of the load voltage in the presence of a
shunt capacitor
Fig. CIO Diode current waveform in a ltered half-wave rectier
circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 47 / 102
Filtering
When the diode conducts
v
o
(t) = V
m
sin t
and
i (t) = i
C
(t) +i
o
(t)
where i
C
(t) and i
o
(t) are the currents through the capacitor and
load resp.
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 48 / 102
Filtering
We can therefore write
i (t) =
v
o
(t)
R
L
+C
dv
o
(t)
dt
=
V
m
R
L
sin t +CV
m
cos t
= I
m
sin (t +)
where
I
m
=
V
m
R
L
_
1 + (CR
L
)
2
and
= tan
1
CR
L
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 49 / 102
Filtering
At the cut-out point, t
CO
, i (t
CO
) = 0, hence
t
CO
=
in the rst half cycle
The peak current I
m
through the diode increases with increasing
capacitance
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 50 / 102
Filtering
The diode conducts for shorter periods with larger capacitance such
that the area under the current curve remains constant
When the diode turns o, the load current is supplied by the
capacitor which discharges through R
L
with a time-constant = CR
L
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 51 / 102
Filtering
The voltage on the capacitor is hence
v
o
(t) = V
cm
exp
_

_
Since v
o
(t
CO
) = v
s
(t
CO
) = V
m
sin t
CO
, then
v
o
(t) = V
m
sin t
CO
exp
_

_
For the full-wave rectier, the current waveform with a capacitive
load is similar but ripples at twice the frequency of the half-wave one
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 52 / 102
Filtering
The current waveform is then of the form shown in Fig. FWC
Fig. FWC Output voltage waveform in a ltered full-wave rectier
circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 53 / 102
Filtering
Assuming the ripple voltage can be approximated by a saw-tooth
waveform, then for CR
L
>> 1,
I
m
=
V
m
R
L
_
1 + (CR
L
)
2
CV
m
and
= tan
1
CR
L


2
with v
o
V
m
at t
CO
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 54 / 102
Filtering
For a large capacitor, the exponential term can be expanded as
exp
_

t t
CO
R
L
C
_
~ 1
t t
CO
R
L
C
+
1
2!
_
t t
CO
R
L
C
_
2
+ . . .
~ 1
t t
CO
R
L
C
That is,
v
o
(t) ~ V
m
sin t
CO
_
1
t t
CO
R
L
C
_
i.e. falls linearly from the value at t = t
CO
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 55 / 102
Filtering
If V is the total drop in capacitor voltage as it discharges through
the resistor, the average (DC) output voltage is given by
V
DC
= V
m

V
2
V is referred to as the ripple voltage amplitude
Let T
2
represent the discharge time
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 56 / 102
Filtering
Then with the capacitor discharging at constant rate, the amount of
charge lost would be I
DC
T
2
and the change in capacitor voltage hence
V =
I
DC
T
2
C
As the ltering is improved, the time T
1
the diode conducts becomes
shorter and T
2
approaches half period, i.e.
T
2

1
2f
where f = /2 is the fundamental frequency of the input waveform
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 57 / 102
Filtering
Thus
V =
I
DC
2fC
and
V
DC
= V
m

I
DC
4fC
This is a Thevenins source with an open-circuit voltage V
m
and a
source resistance
R
o
=
1
4fC
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 58 / 102
Filtering
The ripple amplitude is a function of I
DC
and the lter capacitance C
The lter can be improved by adding a series inductor which tends to
keep the current constant since current cannot change
instantaneously in an inductor
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 59 / 102
Voltage doubler
Diode pumps used when the required voltage in some part of a circuit
is higher than the available transforemr peak voltage
These however can drive only light loads - low load currents
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 60 / 102
Voltage doubler
Consider the circuit of Fig. DDP
R
L
V
m
V
m
v
L
n:1
mains
+ -
C
1
C
2
D
1
D
2
Fig. DDP Voltage doubler
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 61 / 102
Voltage doubler
On the negative half-cycle of the secondary voltage, D
1
is o while
D
2
is on
C
1
thus charges to the peak value V
m
through D
2
When the waveform turns positive, D
2
turns of while D
1
turns on
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 62 / 102
Voltage doubler
C
1
can now discharge into the load through D
1
while dumping charge
onto C
2
Thus,C
2
charges to 2V
m
= V
C1
+V
m
C
2
plays the role of smoothening the load voltage
Note that the output voltage is stable at 2V
m
after 2 half-cycles of
the input waveform
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 63 / 102
Voltage tripler
This idea is extended to the voltage trippler circuit of Fig. TDP
R
L
V
m
V
m
V
L
2V
m
n:1
Mains
D
1
D
3
D
2
C
1
C
2
C
3
+
+
+
-
-
-
3V
m
Fig. TDP The voltage tripler
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 64 / 102
Voltage tripler
We start on a positive half-cycle of the input waveform where D
1
is
on and the other diodes are o
C
1
thus charges to V
m
through D
1
On the following negative half-cycle, D
1
turns o while D
2
turns on
and C
2
can now charge to 2V
m
through D
2
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 65 / 102
Voltage tripler
On the next positive half-cycle D
3
turns on and C
3
charges to 3V
m
through D
3
Thus
V
L
= V
C2
+V
m
= 3V
m
The output voltage is stable at 3V
m
after 3 half-cycles
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 66 / 102
Voltage quadrupler
Extending still further, we have the quadrupler circuit of Fig. QDP
R
L
V
m
V
m
v
L
n:1
Mains
+
+
+
+
-
-
-
-
C
1
C
3
C
4
C
2
D
1
D
3
D
4
D
2
2V
m
3V
m
4V
m
Fig. QDP The quadrupler circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 67 / 102
Voltage quadrupler
On the rst negative half cycle, C
1
charges to V
m
through D
1
On the following positive half-cycle, C
2
charges to 2V
m
through D
2
C
3
then charges to 3V
m
through D
3
on the next negative half-cycle
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 68 / 102
Voltage quadrupler
Finally, C
4
charges to 4V
m
on the following positive half-cycle and the
output voltage thus stabilises
The output voltage is stable at 4V
m
after 4 half-cycles of the input
waveform
Note that for V
o
= nV
m
where n is an integer, we require n
half-cycles, n diodes and n capacitors
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 69 / 102
Clipping or limiter circuit
The forward bias voltage drop across a Si diode cannot rise above
V

~ 0, 6 V
Thus, diodes can be used to limit or slice o parts of an input signal
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 70 / 102
Clipping or limiter circuit
Consider the shunt and series limiting circuits of Fig. LMT
R
R v
i
v
i
v
o
v
o
V
ref
V
ref
D
D
AS SHUNT ELEMENT
AS SERIES ELEMENT
Fig. LMT Limiting circuit example
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 71 / 102
Clipping or limiter circuit
In the circuit where the diode is in shunt with the output, we have
v
o
(t) ~ v
i
(t) , v
i
(t) < V
ref
+V

~ V
ref
+V

, v
i
(t) _ V
ref
+V

If V
ref
>> V

so that
v
o
(t) ~~ V
ref
, v
i
(t) _ V
ref
+V

and constant
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 72 / 102
Clipping or limiter circuit
In the series element conguration, we have
v
o
(t) ~ v
i
(t) , v
i
(t) +V

< V
ref
~ V
ref
, v
i
(t) +V

_ V
ref
These circuits therefore slice o portions of the positive half-cycles of
the input waveform
Let V
ref
= V
m
/2 >> V

and v
i
(t) = V
m
sin t
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 73 / 102
Clipping or limiter circuit
The output waveform will thus have the waveform shown in Fig. CLIP
t
v (t)
i
v (t)
o
Fig. CLIP Limiter waveform
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 74 / 102
Clipping or limiter circuit
To slice o on both half-cycles, we use two diodes and two reference
voltages as shown in Fig. DCLP
R
v
i
v
o
V
ref1
V
ref2
D
1
D
2
V > V
ref2 ref1
Fig. DCLP A two-sided limiter circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 75 / 102
Clipping or limiter circuit
The output voltage is then given by
v
o
(t) ~ v
i
(t) , V
ref 2
+V

> v
i
(t) > V
ref 1
V

~ V
ref 2
+V

, V
ref 2
+V

< v
i
(t)
~ V
ref 1
V

, v
i
(t) < V
ref 1
V

We note that the half-wave rectier is a clipping circuit with V


ref
= 0
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 76 / 102
Clipping or limiter circuit
Fig. DCLPW shows the waveform of a two sided limiter
t
v (t)
i
v (t)
o
Fig. DCLPW Two-sided clipped waveform
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 77 / 102
Clamping or catcher circuit
Fig. CLMP shows an application of the clamping circuit in an
uninterruptable power supply (UPS)
D
1
D
2
+ -
12 V Accu
15 V dc supply
(filtered)
+
-
Mains
12 - 15 V
Electronic
circuit
Fig. CLMP An application of the claming circuit in a UPS
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 78 / 102
Clamping or catcher circuit
The circuit to be driven is assumed to operate within 12 - 15 V
In this circuit, a 12 V accumulator is used as the reference voltage
and kicks in immediately there is a mains supply outage
For this to happen, we require that
V
DC
V
2
> V
ref
V
1
when the mains supply is live, where V
DC
is the ltered rectier
output voltage
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 79 / 102
Clamping or catcher circuit
Another application of the clamping circuit is when a diode is
connected in shunt with inductive loads such as relays and DC electric
motors
Since an inductor will oppose any changes in the current owing
through them, they generate a high back emf when current ow is
interrupted
This voltage can damage the switching device unless a path is
provided through which the stored magnetic energy can be dissipated
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 80 / 102
Clamping or catcher circuit
The diode connected in this way is usually referred to as a
free-wheeling diode, see Fig. FWD
D
t=0 R
V
DC
motor
Fig. FWD Free-wheeling diode as a clamp circuit
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 81 / 102
Sampling gate or transmission gate
Ideally, the output of the sampling gate must reproduce the some
portion of the input waveform exactly
The time interval is selected through a control or gating (sampling)
signal usually of a rectangular waveform
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 82 / 102
Sampling gate or transmission gate
Consider the diode bridge of Fig. SMPL
Fig. SMPL The diode bridge sampling gate
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 83 / 102
Sampling gate or transmission gate
We assume the control signals v
C1
(t) and v
C2
(t) have the waveform
of Fig. CNTRL
T
H
T
L
t
t
v (t)
C1
v (t)
C2
V
H
V
L
Fig. CNTRL Control voltages in the diode sampling gate
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 84 / 102
Sampling gate or transmission gate
We assume that the diodes are identical and ideal, i.e. V

~ 0,
r
f
~ 0, r
r
~ and also v
C1
(t) = v
C2
(t) = v
C
(t) and given by
v
C1
(t) = V
H
, T
H
= V
L
, T
L
v
C2
(t) = V
H
, T
H
= V
L
, T
L
The input waveform is assumed sinusoidal such that
v
s
(t) = V
m
sin t
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 85 / 102
Sampling gate or transmission gate
Thus, during a time T
L
, all the diodes will be o and the reverse bias
voltages on the diodes are
V
H
on D
2
V
L
on D
3
v
s
(t) (V
H
) on D
4
D
1
has a forward bias of v
s
(t) V
L
during T
L
however
The nodes P
1
and P
2
in Fig. 1 are therefore isolated and the output
voltage v
o
(t) = 0
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 86 / 102
Sampling gate or transmission gate
The minimum value of V
L
required to keep D
1
in the o state is then
V
L,min
= V
m
the peak signal amplitude
Thus,
v
D1,rev
= v
s
(t) V
L,min
= 0
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 87 / 102
Sampling gate or transmission gate
During T
H
, all diodes can be expected to be on with diode currents
consisting of
A component due to v
C1
(t) = v
C2
(t) = v
C
(t)
A component due to v
s
(t)
We use superposition to obtain the total diode current
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 88 / 102
Sampling gate or transmission gate
For v
C
(t) alone, the circuit can be simplied as shown in Fig. SMPW
Fig. SMPW Diode current component due to control voltage
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 89 / 102
Sampling gate or transmission gate
We have V
P1
= V
P2
= V
P
= 0
Hence
I
/
C
=
V
P
+V
H
R
C
=
V
H
R
C
I
C
=
V
H
V
H
R
C
=
V
H
R
C
so that I
/
C
= I
C
Hence
I
1
+I
2
= I
3
+I
4
= I
C
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 90 / 102
Sampling gate or transmission gate
Since the branches are assumed identical,
I
1
= I
2
= I
3
= I
4
=
I
C
2
=
V
H
2R
C
I
o
= I
s
since v
o
(t) = 0
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 91 / 102
Sampling gate or transmission gate
The circuit with v
s
(t) alone is shown in Fig. VSC
Fig. VSC Diode current component due to input signal
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 92 / 102
Sampling gate or transmission gate
We have
I
/
o
= I
/
2
+I
/
3
I
/
2
= I
/
3
=
V
m
2R
C
I
/
1
= I
/
C
+I
/
2
=
V
m
R
C
+
V
m
2R
L
= I
/
4
Thus, the net current through D
4
is given by
I
4,net
= I
4
I
/
4
=
V
H
2R
C

_
V
m
R
C
+
V
m
2R
L
_
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 93 / 102
Sampling gate or transmission gate
Or
I
4,net
= I
4
I
/
4
=
V
H
2R
C

V
m
2R
C
_
2 +
R
C
R
L
_
I
4,net
= 0 if
V
H,min
= V
m
_
2 +
R
C
R
L
_
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 94 / 102
Sampling gate or transmission gate
Since D
4
experiences reverse biasing due to v
s
(t), V
H,min
must be set
properly to keep D
4
on during T
H
Practical gates are complicatedd by diodes being other than ideal, i.e.
V

,= 0, r
f
,= 0
This unbalances the diode bridge especially with non-identical diodes
Nodes P
1
and P
2
will then be at dierent potentials during T
H
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 95 / 102
Sampling gate or transmission gate
In this case, a portion of the control voltage appears across the load
The sampled portion of v
s
(t) is hence raised above ground by an
amount equal to the clock feed-through
v
o
(t) is thus said to be sitting on a pedestal
Even with identical diodes, a similar situation can arise if the control
(clock) signals are asymmetric
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 96 / 102
Sampling gate or transmission gate
Fig. SMWF shows a typical sampled signal
t
v (t)
i
v (t)
o
Fig. SMWF Sampled output from a diode sampling gate
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 97 / 102
Diode SPICE model
In the SPICE model, the reverse saturation current is replaced by the
transport saturation current, I
S
whereby
I
S
T
XTI
exp
_

qEG
kT
_
XTI depends on
n
2
i
_
D
p

p
, N
a
>> N
d
and
XTI ~ 3
in Si devices
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 98 / 102
Diode SPICE model
XTI models the saturation current temperature dependence and is
known as the reverse saturation current temperature exponent
EG is the width of the energy bandgap in eV and is known as the
activation energy
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 99 / 102
Diode SPICE model
Further parameters include
KF, AF associated with the 1/f or icker noise in the diode arising
from carrier trapping
BV, IBV are the reverse breakdown voltage and current at breakdown
resp.
FC is a factor used to make the expression of the transition
capacitance per unit area C
t
continuous for forward bias voltages since
C
t
=
C
j 0
_
1
V

0
_
m
where
0
= V
0
in our designation
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 100 / 102
Diode SPICE model
For Si diodes therefore, SPICE gives the following
Parameter Denition Dt val Typ val
IS, (I
S
) rev. sat. curr in A 10
14
10
14
RS, (R
n
) blk & cont. res. in 0 10
N, () emiss. coe 1, 0 1, 0
TT, (
D
,
p
,
n
) trans. time/lf-tim in s 0 0, 1 10
9
CJO, (C
j 0
) zero bias junct. cap. 0 2 10
12
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 101 / 102
Diode SPICE model
Parameter Denition Default val Typ val
VJ, (V
0
,
0
) contact potential in V 1, 0 0, 8
EG, (E
g
) b-gap width in eV 1, 11 1, 11
M, (m) junct. grad. factor 0, 5 0, 5
XTI , (XTI ) sat. curr. temp. exp. 3 3
KF, (K
f
) icker noise coe 0 2 10
12
Parameter Denition Default val Typ val
AF, (A
f
) icker noise exp. 1
FC, (FC) Coe of fwd bias trans. cap. 0, 5
BV, (V
B
) rev. brk dwn voltage in V 40, 0
IBV, (I
B
) curr. at rev. brk dwn in A 1 10
3
Dr.-Ing. Wilfred Mwema (UoN) Diode Circuit Analysis and Design 03/12 102 / 102

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