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analog to digital convertoe basics

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An analogtodigital converter (ADC) acts as a bridge between the analog and digital worlds. It is

a necessary component whenever data from the analog domain, through sensors or transducers,

should be digitally processed or when transmitting data between chips through either longrange

wireless radio links or highspeed transmission between chips on the same printed circuit board

(PCB).

The AnalogToDigital ConverterThe conversion of an analog signal to digital quantizes the input in both time and amplitude. Quantization

in time (referred to as sampling) is performed either by an explicit sampleandhold circuit, as is done in

most ADC architectures, or distributed across several comparators as is done in flash ADCs. The

amplitude quantization (referred to just as quantization) approximates the input signal given a set of fixed

reference levels. The number of possible quantization levels determines the resolution of the ADC, which

is typically described with the number of binary bits, n, needed to represent the quantization level.

Nyquist Rate:

The sampling of an input signal with bandwidth fb with a sample rate of fs of twice the signal bandwidth

is referred to as Nyquist sampling and given fixed and equidistant sampling instances this process does

not introduce any error as the signal can be ideally reconstructed.

CHARACTERISTICS:

1. QUANTIZATION ERROR:

In contrast to sampling, the quantization introduces errors which cannot be removed. Figure below how a

normalized input between 0 and 1 is mapped to the corresponding output codes using the midriser

convention given in, where the first transition occurs qs above Vmin. Here, qs correspond to the

quantization step size and Vmin is the lower end of the input range. qs = VFS/2n

Where VFS is the fullscale input range and is defined as:

VFS = Vmax Vmin

If the analog input signal is approximated with a corresponding analog output, Vout where Dout is the

decimal value of the output code then the quantization error, , is described by .

Vout=

= Vout Vin

Ideally, the quantization error is then bound between qs/2 and qs/2 and varies

with the input signal.

2. RESOLUTION:

The resolution of the converter indicates the number of discrete values it can produce over the range of

analog values. The resolution determines the magnitude of the quantization error and therefore determines

the maximum possible average signal to noise ratio for an ideal ADC without the use of oversampling.

The values are usually stored electronically in binary form, so the resolution is usually expressed in bits.

In consequence, the number of discrete values available, or "levels", is assumed to be a power of two. For

example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels,

since 28 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer) or from 128 to

127 (i.e. signed integer), depending on the application.

Resolution can also be defined electrically, and expressed in volts. The minimum change in voltage

required to guarantee a change in the output code level is called the least significant bit (LSB) voltage.

The resolution Q of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its

overall voltage measurement range divided by the number of discrete values:where M is the ADC's

resolution in bits and EFSR is the full scale voltage range (also called 'span'). EFSR is given

bywhere VRefHi and VRefLow are the upper and lower extremes, respectively, of the voltages that can be

coded.Normally, the number of voltage intervals is given bywhere M is the ADC's resolution in bits.[1]

That is, one voltage interval is assigned in between two consecutive code levels.

Example:

..

.

There is a wide variety of different ADC architectures available depending on The requirements

of the application. They can range from highspeed, low Resolution flash converters to the

highresolution, lowspeed oversampled Noiseshaping sigmadelta converters. This deals mainly

with the design Highspeed Nyquist rate converters. The architectures which are considered

highspeed in this context are:

Flash ADCs The most parallel converter architecture. The entire conversion is complete

within one clock cycle.

Folding and Interpolating ADCs These are closely related to flash ADCs but using a

multistep implementation. The conversion is often finished within one clock cycle.

Pipeline ADCs Several algorithmic stages are pipelined to form the pipeline ADC

architecture. The latency is the same as for the algorithmic architecture but the

throughput is increased at the cost of additional area.

Flash ADCs:

The flash ADC architecture offers the highest potential sample rate of all the different architectures . The

correct quantization level is decided through the parallel comparison of the input signal to all 2n1

reference levels. The reference levels are typically generated through a resistor ladder where 2n equally

sized resistor are used to generate the reference voltages. Each comparator will then decide whether the

input signal is larger than this reference level, generating a 1 on the output if this is case and a 0

otherwise. The output from the comparator array will then be thermometer coded, named from the

analogy with the mercury level in a classical thermometer. In the thermometer code, the transition from

1s to 0s is indicating the best approximation of the input signal. A decoder is then used in order to

convert the thermometer code to an nbit digital output word. The flash ADC is most suitable for low

resolutions as the hardware needed doubles for a resolution increase of 1 bit, whereas the power

dissipation increases by more than a factor of two. The flash architecture often results in a high input

capacitance, in comparison with other architectures, due to the high parallelism.

Interpolation and folding are two techniques which are often used together to increase the linearity and

reduce the hardware of flash ADCs. The goal is to design fast converters with higher resolution than full

flash ADCs, without the expensive powerresolution tradeoff that comes with the flash architecture.

Interpolation is used to reduce the number of required comparator preamplifiers. This is done by

interpolating the output of the preamplifiers in order to generate additional zerocrossing points which

can be detected by the comparators. This is valid as long as the both theadjacent preamplifiers are still

operating in their linear region. Depending on the output impedance of the preamplifiers, there is also a

certain amount of averaging between all the preamplifiers. This has the benefits ofsuppressing the

preamplifier offsets while it also generates significant distortion near the edges of the input region

reducing the useful input range to about 70% . In order to compensate for this, additional preamplifiers

needs to be added to restore the input range. Also different values for the interpolation resistances can be

used, but this makes the ADC more susceptibleto process variations because matching is best for resistors

of equal physical dimensions.

Folding is another technique to reduce the hardware needed to achieve a certain resolution at the cost of

increased conversion time. In order to achieve a resolution of n+m bits the work is divided into two parts.

A course quantizer decides the most significant n bits. In parallel with this, a folding circuit folds the

input range according to the Figure, shown for n = 2. The fine quantizer, which has fixed reference levels,

decide the least significant m bits. In Figure 3.4 the ideal folding function is indicated by the dashed line,

the real implementations of the folding circuits will result in smoothing of the folding signal near the

edges indicated by the solid line. This smoothing will decrease the linearity and limits the achievable

resolution. The folding and interpolating ADC finish the conversion within one clock cycle, therefore

there is, as was the case for flash ADCs, no need to include a frontend sampleandhold. Another

potential bandwidth limitation, besides those seen in full flash ADCs, is that the signal delay through the

folding circuit must be handled by the ADC in order to prevent the coarse and fine ADCs to process

different sets of data.

Pipeline ADCs

The pipeline ADC architecture combines the benefits of high throughput and an input capacitance bound

by noise constraints. This is at the cost of extra hardware, power dissipation and the same high latency

associated with the SAR ADCs. The architecture is shown in Figure 3.6. Each stage samples the

inputsignal and generates ak additional bits of information of the input. An output residue is sent to the

succeeding stages with the last stage typically implemented as a flash ADC. Each stage, known as a

multiplying DAC (MDAC), is based on the same principle as the algorithmic ADC and is shown in

Figure. The input signal is sampled and quantized by an abit subADC, this is converted back to analog

and subtracted from the input signal, resulting in the subADC quantization error. This is amplified to

cover the full input range which has the advantage that all pipeline stages can be designed identically,

simplifying the implementation.

As with SAR ADCs, redundancy can be utilized in order to remove the effect of comparator offset and

noise. A common scheme is to use 1.5 bit stages withsignal and generates ak additional bits of information

of the input. An output residue is sent to the succeeding stages with the last stage typically implemented

as a flash ADC. Each stage, known as a multiplying DAC (MDAC), is based on the same principle as the

algorithmic ADC and is shown in Figure. The input signal is sampled and quantized by an abit subADC,

this is converted back to analog and subtracted from the input signal, resulting in the subADC

quantization error. This is amplified to cover the full input range which has the advantage that all pipeline

stages can be designed identically, simplifying the implementation. As with SAR ADCs, redundancy can

be utilized in order to remove the effect of comparator offset and noise. A common scheme is to use 1.5

bit stages withtwo comparators and a gain of two in the multiplier. With this, the architecture is immune

to comparator noise and offsets within a magnitude of VFS/8.

intepolating ADC:

Advantages:

It has less no. of comparators or amplifiers connected to the input.

It has less capacitance on the input.

It enhances the analog input signal bandwidth.

Disadvantages:

Voltage Interpolation is that the delay from the amplifier output to

each comparator can be different due to different resistance.

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