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WW .100Y.
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WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
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W
W
M
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00
M
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WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .T
W.1 Y.COM W
W
W
W
W
.T
00
W
W.1 Y.COM
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
.T
WW .100Y
.100
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100
M
.
W
M
O
W
O
W
WW
WW .100Y.C M.TW
WW .100Y.C M.TW
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O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
iii
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
W
WW .100Y.C M.TW
T
.
M
O
W
.CO .TW
Y
WW .100Y.C M.TW
0
0
1
M
.
O
W
O
W
1. GENERAL DESCRIPTION................................................................................................................................................1
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
WW .100Y.C M.TW
2. FEATURES...........................................................................................................................................................................1
W
WW .100Y.C M.TW
T
.
M
WW 00Y.CO .TW
WW 00Y.CO .TW
.C3.O BLOCK
W
DIAGRAM.............................................................................................................................................................2
W
Y
W
0
T
.
0
W.1 Y.COM W
W.1 Y.COM W
W
W.1 Y.4.COM
W
W
.T
PIN.T
ASSIGNMENTS
W
00
W ...........................................................................................................................................................3
.T
.100
W.1 Y.COM W
M
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
W
.T
00
EAD (PB)-FREE
Y. 4.1. .TLW
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M.T ................................................................................................................3
.10I0DENTIFICATION
W.1 Y.COM W
M
.100
O
W
O
W
W
C
.
W
W
Y
W
.T
W..........................................................................................................................................................4
DESCRIPTIONS
WW .1005.Y.CPIN M
.100
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M.T
.100
OM
W
O
W
C
.
O
W
W
C
W
Y
W
Y.C
WW .100Y.
MII
INTERFACE ............................................................................................................................................................4
.TW
WW .1005.1.
M.T
.100
.TW
M
O
W
M
O
W
C
.
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W
SNI (SW
ERIAL NETWORK
OW
NLY ....................................................................................................5
WINTERFACE
Y).C10MBPS.T
WW .100Y
0Y.C CM
WW .105.3.
M.T
.T INTERFACEW
100
M
.
O
W
LOCK
.......................................................................................................................................................5
O
W
C
W
W
.C
W
.CO BPS
WW .100Y.
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/100MBPS NW
ETWORK .I1
NTERFACE
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WW .15.4.
M.T
.TW
00Y 10M
M
O
W
M
O
W
W
.C
DEVICE CW
ONFIGURATION
INTERFACE
...........................................................................................................................6
.CO
WW .100Y.C M.TW
0Y
WW
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0ONFIGURATION
WW .5.5.
.T
1
00Y LEDMINTERFACE
M
.
1
5.6.
/PHY
A
DDRESS
C
.......................................................................................................6
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
.CPOWER
W
W
Y
W
0
WW 5.7.
T
AND
G
ROUND
P
INS
..........................................................................................................................................7
.
W.1 Y.COM W
.10
W.1 Y.COM W
OMAND OTHER PINS ...............................................................................................................................................7
W
W
W
C
5.8.
R
ESET
.
W
W
W
.T
W
M.T
.100
.TW
100
00Y
M
.
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1
W
M
.
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W
C
.
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.CODESCRIPTIONS
............................................................................................................................................8
WW .100Y
WWREGISTER
WW .100Y.C M.TW
W6.
M.T
.TW
00Y
O
1
W
M
.
O
W
C
W
.C
.CO 0 B.TASIC
WW .100Y.
6.1.
R
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.TW
W MODE CONTROL
WW R.EGISTER
.TW
00Y ............................................................................................................8
0Y
WW
M
1
0
M
O
1
W
M
.
O
6.2.W REGISTER
EGISTER ...............................................................................................................9
O 1 BASIC MODE STATUSWRW
.C
WW .100Y.C M.TW
W
WEGISTER.1....................................................................................................................9
.TW
00Y
0Y.C 2M
W6.3.
.TW
1
0EGISTER
R
PHY
IDENTIFIER R
M
1
.
WW 00Y.CO .TW
.CO .TW
WW 2....................................................................................................................9
.CO3 PHY
Y
W
WW REGISTER
6.4.
I
DENTIFIER REGISTER
W
0
Y
W
0
0
W
T
.
0
M (ANAR) ....................................................................10
1EGISTER
W.1 Y.COM W
W.1 Y.CRO
6.5.WW.R
4OAM
UTO-NEGOTIATION ADVERTISEMENT
EGISTER W
W
W
C
.
W
.T
W
00
Y
.T
W
6.6.
R.EGISTER
UTO
-NEGOTIATIONW
LINK PW
ARTNER
.100 ABILITY
100 5 A
W.1 Y.COM W
M.T
OMREGISTER (ANLPAR)......................................................10
O
W
W
C
.
W
C
W
Y
W
.T
6.7.WW REGISTER
EGOTIATION
EW
XPANSION R0EGISTER
(ANER)
W
00
Y. 6 AUTO-N
M.T .............................................................................11
.1 0
W.1 Y.COM W
MAY.TSETUP REGISTER (NSR).............................................................................................................12
.100 16 NW
O
W
O
W
WEGISTER
6.8. WR
C
.
W
.T
W
Y.C
WW E.1RROR
.TW (LBREMR)
00Y MASKM
.100
6.9. W REGISTER
REGISTER
.................................................12
OM
W
M.T , BYPASS, RECEIVER
.100 17 LOOPBACK
O
W
C
.
O
W
W
C
W
Y
W
Y.
W
W
Y.C
W.....................................................................................................................13
6.10. WW
REGISTER
RX_ER .CTOUNTER
(REC)
.TW
M.T
.100
100
0018
M
.
O
1
W
M
.
O
W
C
.
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W
W 19YSNR
6.11.
RW
EGISTER
DISPLAY
REGISTER .......................................................................................................................13
W
Y
W
WW .100Y.C M.TW
0 T.C
M.T
.100
.TW .....................................................................................................................................13
025
O
1
6.12. WREGISTER
EST REGISTER
W
M
.
O
W
C
W
W
.CO .TW
WW .100Y.
WW .100Y.C M.TW
WW .1DESCRIPTION.......................................................................................................................................14
M.T
00Y
O
W
7. FUNCTIONAL
M
O
W
W
.CO .TW
WW .100Y.C M.TW
WW .100Y.C M.TW
WW M.1ANAGEMENT
00Y
O
W
M
7.1.
MII ANDW
I
NTERFACE
..........................................................................................................................14
WW 00Y.CO .TW
.CO .TW
WW .100Y.C M.TW
W Transition.....................................................................................................................................................14
Y
W
7.1.1. W
Data
0
M
.1
O
W
M
.10
WW 00Y.CO .TW
7.1.2.
Serial
Management...............................................................................................................................................15
.CO .TW
WW .100Y.C M.TW
WW
Y
W
0
W
0
M
.1
7.2.
AUTO-NEGOTIATION
ARALLEL DETECTION ......................................................................................................16
OPM
WW 00Y.CO .TW
W.1 YAND
WW 00Y.CO .TW
C
.
W
W
W
W
W the Medium
7.2.1.
Setting
and.TInterface Mode to MAC.........................................................................................16
M
.1
M
.1
.100 Type
OM ...............................................................................................................................16
WW 00Y.CO .TW
WW 00Y.CO .TW
C
7.2.2.
UTPW
Mode
Interface
.
W
WWand 0MII
W
Y
W
0
M
.1
.T
.1 SNI
7.2.3.
UTP ModeW
and
Interface
W.1 Y.COM W
OM ...............................................................................................................................17
WW 00Y.CO .TW
W
C
.
W
W
W
W
.T
00
.T
7.2.4.
FiberW
Mode and.1MII
00YInterface..............................................................................................................................17
W.1 Y.COM W
W.1 Y.COM W
OM
W
W
W
C
.
7.3.
FLOW CONTROL
S
UPPORTY..........................................................................................................................................17
W
W
W
.T
W
M.T
.100
.TW
100
00 ANDM
M
.
O
1
W
.
O
W
C
7.4.
HARDWARE CONFIGURATION
A
UTO
-N
EGOTIATION
............................................................................................18
.
O
W
W
.C
WW .100Y
WW .100Y.C M.TW
WW
M.T
.TW................................................................................................................19
7.5.
LED AND PHY
ADDRESS
00CYONFIGURATION
O
1
W
M
.
O
W
C
W
W
.CO .TW
WW .100Y.
7.6.
SERIAL NETWORK
WW .100Y.C M.TW
WWINTERFACE
M.T
00Y....................................................................................................................................20
O
1
W
M
.
O
W
7.7.
POWER DOWN, LINK
DOWN, POWER
, AND ISOLATION
MODES ......................................................................20
W
.CO SAVING
WW .100Y.C M.TW
WW .100Y.C M.TW
WW.....................................................................................................................................................20
.TW
00Y
7.8.
MEDIA INTERFACE
O
1
W
M
.
O
W
O
W
WW .100Y.C M.T
7.8.1.
100Base-TX ..........................................................................................................................................................20
WW .100Y.C M.TW
WW .100Y.C M.TW
O
7.8.2.
100Base-FX FiberWMode
WW 00Y.CO
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WW 00Y.CO .TW
C
.
W
W
Y
W
0
W...................................................................................................................................................21
.1
7.8.3.
10Base-T TX/RX
W.1
M.T
.10
OM
W
O
W
W
C
.
W
C
W
Y
W
W .....................................................................................................................................22
W
7.9.
REPEATER MODE OW
PERATION
Y.
W
M.T
.100
M.T
.100
O
W
O
W......................................................................................................................................22
C
7.10.
RESET, AND TRANSMIT BW
IAS
.
W
W
Y
W
Y.C
W
W
M.T
.100
M.T
.100
O
W
O
W
C
.
Single-Chip/Port 10/100 Fast Ethernet
iv
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
WW PHYceiver
M.T
.100
W
O
W
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

Table of Contents

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W .......................................................................................22
7.11.
3.3V POWER SUPPLY AND VOLTAGE
CIRCUIT
W
Y.C
WCONVERSION
0
WW
0
T
.
1
M.T
.
M
O
7.12.
FAR END FAULT INDICATION
......................................................................................................................................22
W
O
C
W
.C
W
WW .100Y.
00Y
M.T
M.T
.1.......................................................................................................................................................23
O
W
8. CHARACTERISTICS
O
W
C
WW .100Y.
.TW
WW .100Y.C M.TW
M
O
W
8.1.
DC CHARACTERISTICS
...............................................................................................................................................23
O
W
Y.C ..................................................................................................................................23
WW .100Y.C M.TW
WW
.TW
8.1.1.
Maximum
00Ratings
.TW Absolute
1
M
.
M
W
WW 00Y.CO .TW
.CO .TW
W
Operating
Conditions
...........................................................................................................................................23
.CO 8.1.2.
Y
W
W
0
Y
W
0
0
T
.
0
W.1 Y.COM W
8.1.3.
Power Dissipation
OM
W.1................................................................................................................................................23
W
W.1 Y.COM
C
.
W
W
Y
W
.T
W
00
W Vcc ................................................................................................................................................23
8.1.4.
M.T
.100
W.1 Y.COM W
M.T Input Voltage:W
.100
O
W
O
W
W
C
.
C
...............................................................................................................................................24
W
Y
W
W
.T
WCHARACTERISTICS
00
Y. 8.2. .TAC
W
M.T
.100Timing............................................................................................................................24
W.1 Y.COM W
M MII Transmission
.100
O
8.2.1.
Cycle
W
O
W
W
C
.
W
W
Y
W
.T
WCycle
WW .100Y.C8.2.2.M.TW
.100
MII Reception
Timing
M.T
.100 .................................................................................................................................25
OM
W
O
W
C
.
O
W
W
C
W
.
Y
C
W
W Transmission
WWCycle.1Timing............................................................................................................................27
.TW
00Y
WW .100Y.8.2.3.
M.T
.100
.TSNI
M
O
W
M
O
W
C
8.2.4.
SNI
Reception
Cycle
Timing
.................................................................................................................................28
.
O
W
W
.C
WW .100Y
WW .100Y.C M.TW
WW .100Y8.2.5.
M.T
.TW
MDC/MDIO
Timing..............................................................................................................................................29
O
W
M
O
W
C
O
W
W
.C
WW .100Y.
WW ......................................................................................................................................30
.TW
00Y
0Y.C CRYSTAL
WW .18.3.
M.T
.TWCHARACTERISTICS
1
0
M
.
O
W
M
O
W
TRANSFORMER CHARACTERISTICS
............................................................................................................................30
O
W 8.4.
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
9. MECHANICAL
DIMENSIONS
.......................................................................................................................................31
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W ............................................................................................................................32
O
WW 00Y.CO .TW
W
9.1.
M
ECHANICAL
DIMENSIONS N
.CO .TW
WOTES
C
.
Y
W
W
W
0
Y
W
0
0
W
T
0
.1
W.1 Y.COM W
M.INFORMATION......................................................................................................................................33
.1ORDERING
OM
W
O
W
W
C
10.
.
W
C
W
Y
W
.T
W
00
W
WW .100Y.
M.T
.100
W.1 Y.COM W
M.T
O
W
O
W
W
C
.
W
W
Y
W
.T
00
W
WW .100Y.C M.TW
M.T
.100
W.1 Y.COM W
O
W
O
W
W
C
.
W
W
.T
WW .100Y
WW .100Y.C M.TW
.100
M.T
OM
W
O
W
C
.
O
W
W
C
W
Y
W
WW .100Y.
.TW
WW .100Y.C M.TW
M.T
.100
M
O
W
O
W
C
.
O
W
W
WW .100Y
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
O
W
O
W
C
O
WW .100Y.
WWMII 0Interface..................................................................................................................................4
.TW
WW .100Y.C M.TW
0Y.C M.TW
W1.
Table
M
O
1
W
.
O
W (Serial
WW 0Only
.CO .TW Interface)
WW .100Y.C M.TW
TableW
2.WSNI
0Y.C ..............................................................................5
W10Mbps
.TW
1
00Y Network
M
.
1
M
.
WW 00Y.CO .TW
W Interface
WW 00Y.CO .TW
Table 3. W
Clock
.CO ..............................................................................................................................5
W
W
Y
W
0
W
T
W.1 Y.COM W
M. Network Interface............................................................................................6
.10
W.1 Y.COM W
Table 4. 10Mbps/100Mbps
O
W
W
W
C
.
W
W
.T
W
.T
.100
.TW
100
00Y
M
.
OM
1
W
Table 5.WDevice
Configuration
Interface
.....................................................................................................6
M
.
O
W
C
.
O
W
W
C
W
.
Y
W
C
.
Y
W
W Interface/PHY
W
.TW
TW
M.T
.100
.Address
Table 6. W
LED
Configuration..................................................................................7
100
00Y
M
.
O
1
W
M
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
Table 7. Power
.................................................................................................................7
0Y.C Pins
WW and
.TW
0Ground
1
M
.
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
Table 8. Reset
.CPins......................................................................................................................7
W
W
Y
W
0
WWand .Other
T
.
0
W.1 Y.COM W
W.1 Y.COM W
OM Control RegisterW
W
W0 1BasicY.Mode
Table 9. Register
.......................................................................................8
C
W
W
W
.T
W 1 Basic
M.T
.100
.TW Register..........................................................................................9
100
00 ModeMStatus
M
.
O
1
W
.
Table 10. Register
O
W
C
.
O
W
W
WW .100Y
W
Y.C
WW .100Y.C M.TW
WW2 PHY
M.T
.T
00Identifier
Table 11. Register
Register
1.............................................................................................9
O
1
W
M
.
O
W
C
O
W
WW .100Y.
.TW
WW .100Y.C M.TW
Table 12. Register
3 PHY
2.............................................................................................9
0Y.C MRegister
WW
M
.TW
0Identifier
O
1
W
.
O
W
W
.C
.CO .T
WW .100Y.C M.TW
Table 13. Register
Advertisement
Register
(ANAR)..................................................10
W
WW
.TW
00Y
W4WAuto-Negotiation
1
00Y
M
.
1
M
.
WW 00Y.CO .TW
W
.CO(ANLPAR)
Table 14. Register 5 W
Auto-Negotiation
Partner Ability
....................................10
WW Register
W
.CO Link
Y
W
W
0
Y
W
T
.
0
0
W
T
.
.1
W.1 Y.COM W
MExpansion
.10
OM
W
Table 15. Register 6 Auto-Negotiation
Register
(ANER)
.........................................................11
O
W
W
C
.
W
C
W
.
Y
W
.T
W
00
W
.T
WW
00Y Register
.100
Table 16. Register 16
NWay
W.1 Y.COM W
M.T (NSR)....................................................................................12
.1Setup
OM
W
O
W
W
C
.
W
C
W
Y (LBREMR)
W
W
.T
00
Y.
WMask .Register
Table 17. Register 17WLoopback,
Error
..............................12
.TW
100
M.T
W.1 Y.COM W
MReceiver
.100 Bypass,
O
W
O
W
W
C
.
W
W
W
.T
W
Y.C (REC)............................................................................................13
WW .100Y
Table 18. Register 18 W
RX_ER
Counter
.100
M.T
OM
W
M.T
.100
O
W
C
.
O
W
W
C
Y
Table 19. Register 19 SNR
Register
..............................................................................................13
W
.C
W
WW .100Y.
WWDisplay
M.T
.100
.TW
00Y
M.T
O
W
O
W
C
.
Table 20. Register 25 Test W
Register.............................................................................................................13
W
W.1 Y.COM W
Y
W
WW .100Y.C M.TW
W ......................................................................................................................15
.100
.T
00
1
W
M
.
Table 21. Serial Management
O
W
O
W
WW
WW .100Y.C M.TW
0Y.C
WWType
.TW
0and
Table 22. Setting the Medium
Interface
Mode
to
MAC..............................................................16
1
M
.
O
W
O
W
WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C
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List of Tables

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
Table 23. UTP Mode and MII Interface
W ......................................................................................................16
WW .100Y.C M.TW
T
.
O
W
OM
Table 24. UTP Mode and SNI
.CInterface......................................................................................................17
Y
WW .100Y.C M.TW
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1
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.
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Table 25. Fiber Mode
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.....................................................................................................17
O
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W
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WW .100Y.C M.TW
WW .100Mode
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.
Table 26. Auto-Negotiation
Pin
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..........................................................................................18
O
W
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WW .100Y.C M.TW
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0Y.C M.TW
WW .1..........................................................................................................................19
Table.T27.
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OM 28. Power Saving
WW 00Y.CO .TW
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WW
W
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................................................................................................20
Y
W
W
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W.1 Ratings........................................................................................................23
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W
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W
C
W
Y
W
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W
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Conditions...................................................................................................................23
W
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W
W
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W
C
W
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W
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M.TPower Dissipation........................................................................................................................23
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W
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WW .100Y
WW .100Table
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M.T Voltage: Vcc.......................................................................................................................23
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W
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WW .100Y
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WW .100Y.
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WW .100Y.C M.TW
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......................................................................................................28
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW Table
37. MDC/MDIO
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WW 00Y.CO .TW
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W
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Table
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WW .100Y
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.
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WW .100Y.C M.TW
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...................................................29
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C
W
WW

List of Figures

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
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W.1
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1.

2.

General Description

Features

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.CO ID: JATR-1076-21 Rev. 1.24
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2
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3.

Block Diagram

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW 00Y.CO .TW
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WW 00Y.CO .TW
WW .100Y.C M.TW
24. RXER
O
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WW .100Y.C M.TW
WW .100Y.C37. ANE
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WW .100Y.C M.TW
M.T
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38.
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23. CRS
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WW .100Y
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WW .100Y.C M.TW
WW .100Y.C M.TW
M
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.
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WW .100Y.C M.TRTL8201CL
WW 42..RESETB
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M
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y.C M.TW
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00
M
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WW 00Y.CO .TW
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W
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.
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4.1. Lead (Pb)-Free
Package
Y
W
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M.T
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.
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3
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WW .100Y.C
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36. AVDD33

35. AGND

34. TPTX+

33. TPTX-

32. PWFBOUT

31. TPRX+

30. TPRX-

29. AGND

28. RTSET

27. NC

26. MDIO

25. MDC

2. TXEN

3. TXD3

4. TXD2

5. TXD1

6. TXD0

7. TXC

8. PWFBIN

9. LED0/
PHYAD0

10. LED1/
PHYAD1

11. DGND

12. LED2/
PHYAD2

Pin Assignments

1. COL

4.

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
W
WW .100Y.C M.TW
T
.
M
O
W
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Y
WW .100Y.C M.TW
0
0
1
M
.
O
W
O
W Power
LI: Latched Input
during
I: Input
W
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WW O: .Output
0
0
WW
1
0
1
M
.
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W
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100
M
.
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1
M
.
O
W
M
O
W
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W
Y.C
WW .100Y.C M.TW
0
T
.
0
1
OM
WW 00Y.CO .TW
W.
WW 00Y.CO .TW
C
.
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W
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WW 00Y.CO .TW
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WW 00Y.CO .TW
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W
W W 00Y
W
W
T
M
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WW 00Y.CO .TW
W.1 Y.COM W
W
W
1.
MII
Interface
W
W
W
.T
00
W
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00
W.1 Y.COM W
OM
W.1 Y
OM
Type
Pin
No.
Description
W
W.1 Y.Name
C
.
W
C
W
W
W
W
.T
W
M.T
.100
100 Transmit
00 TXC M.TWO
M
.
O
1
7
Clock.
W
.
O
W
C
.
O
W
W
Y
Y.Cpin provides
WW
WW .100This
clock .as
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WW .100Y.C M.TW
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M
W
O
W
C
O
W
W
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WW .100Y.
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WW .1TXEN.
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WW .100TXEN
M.T
.TIW
M
O
W
M
2
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O
W
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O
W
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W
WW of.1valid
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WW .The
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1
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W internal
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W
C
W
.
Y
W
C
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W
.
0
Y
W
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W
.
W
Y
W
W
M
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O
W
MI.T
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O
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3,
4,
5,
6
Transmit
W
C
.
O
W
W
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W
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WW The.1MAC
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M
O
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O
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C
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W
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W pull highWresistor
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WW .100Y.C M.TW
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W
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W
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O
W
WW .100Y.
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WWThis pin
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0provides
WW .100Y.C M.TW
M
1
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O
W
O
O
W
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WW RXC
WWand 2.5Mhz
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Wsignals.
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WW .100Y.C M.TW
M
.
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M
.
O
W
O
W
C
.
O
W
W
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C
W
Y
W
Y.
W
W
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WW .100Y.C M.TW
M.T
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100 high when
M
.
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a. collision is detected on the
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O
W
O
C
.
O
W
W
Y at which
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WW to determine
WW power
During
WW .100Y.C M.TW
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100on reset,
M
.
O
W
O
W
C
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modeW
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WW .100Y.
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W to operate:
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WW .100Y.C M.TW
M
1
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.
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O
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W
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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.
W
W
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W
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WW CL.LED
0
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WW weak.1pull
.
1
0
WW .100Y.C M.TW
MT
M
O
W
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resistor
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O
W
C
.
O
W
W
W
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Y
W
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O
W
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W
WW at normal
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.
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WW .100Y.C M.TW
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WW on0the
W
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W
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W
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W
0
W
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W
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WW .100Y
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C
O Receive Data.
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WW .100Y.
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WW
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W
M
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O
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WW .100Y.C M
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W
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
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WW 00Y.CO .TW
W
W
W
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M
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WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
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00
W
M
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WW 00Y.CO .T
W.1 Y.COM W
W
W
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O
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.
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WW .100Y
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M
.
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y.C M.TW
W
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WW 00Y
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4
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Y
W
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W.1
WW
WW .100Y.C M.TW
O
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WW .100Y.C M.TW
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W
WW .100Y.C
W
WW

5.

Pin Descriptions

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
Name
Type
Pin No.
Description
W
WW .100Y.C M.TW
T
.
O
RXER/
O/LI
24.COM Receive Error. WW
W
Y.C
00such
0
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1
0 Y
M.T /J/K/, invalid /T/R/, or invalid
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FXEN
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as
invalid
1
M
.
O
W
O
W
C
Y.
WWgo high.
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WW .100Y.C Msymbol,
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100
M
.
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O
W
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O
W
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WW .100Y.C M.TW
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WW sets0this
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W
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WW .100YAfter power
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WW .100Y.C M.TW
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W
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W
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W
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WW .100Y.MDC
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W
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W
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W
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W
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O
W
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y
WW 00Y.CO .TW
WW .100Y.C M.TW
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W
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.
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O
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WW .100Y.
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WW .100Y.C M.TW
WW .100Y.C M.TW
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W
O
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W
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WW(Serial
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WW .100Y.C M.TW
W
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1
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M
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.
O
W
O
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WW .100Y.C M.TW
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WWCOL.100Y.CO M.TW1
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WW 00Y.CO .TW
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WWSerial
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W
W
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W CRS .100 O M.T 23
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WW 00Y.CO .TW
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WW 00Y.CO .TW
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W
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Wby
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W
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.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
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O
WInterface
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00Y.CO .TW
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WW Interface
C
.
Y
W
W
W
0
Y
W
0 No. MDescription
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M
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M
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Name
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
WO
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W.1 Y.COM W
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Wwhen
W.1 Y.COM
C
.
W
W
Y
W
W
This
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25MHz
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must
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left
open
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W
00
W
W
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OM
W
M.T 25MHz oscillator
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W
W
WW .100Y.
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.
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W
C
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W
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W
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the 25MHz
a 25MHz
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WW .100Y.CThisM
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W
W
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Wfor clock
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W
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WW(see 8.3
.TW
WW .100Y.C
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100
M
.
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W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.T
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00Y.CO
W
WW 00Y.CO .TW
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.
W
W
W
Y
W
0
W
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W
O
W
W
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.
W
C
W
Y
W
W
W
WW .100Y.
M.T
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M.T
O
W
O
W
C
.
W
W
Y
W
WW .100Y.C M.TW
M.T
.100
O
W
O
W
C
.
Single-Chip/Port 10/100 Fast Ethernet
5
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
WW PHYceiver
M.T
.100
W
O
W
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
T
.
5.4. 10Mbps/100Mbps
W.1 Y.COM W
OM NetworkWInterface
C
.
W
.TW
100
00Y Table
M.T
Interface
O
W.Network
OM 4. 10Mbps/100Mbps
W.1 Y.C
C
.
W
Y
W
W
.TW
W
Name
Type
Pin
Description
.TW
100
00No.
M
.
1
M
.
O
W
O
W
.C
W
.C
TPTX+
O
WW .134
.TWOutput. W W.100Y OM.TW
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TW
.TPTXM
M
O WW 33
Differential transmit output
pair shared
100Base-FX and
O
O
Y.Cby 100Base-TX,
WW
.TW output is an MLT-3 encoded
W
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Y.C
W
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0
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configured
100Base-TX,
M
.
.
1
0
M
.
O
1
W
O
W
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W.
W
When configured
WW as 100Base-FX,
W
00Y
Y.C
WW .100Y.Cwaveform.
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.
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.
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M
O
1
W
M
.
O
W
C
RTSET
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28
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W
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Y.
TW to define driving
WW 00Y.CO .TW
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WW .100YThis
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W
M
.
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W
O
W
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WW
current
The resistance
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WW .100Y
TWtransmit DAC.
100 value
WW .100Y.C M.TW
M
.
M
O
W
O
W
onYexperimental
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O
W
W
W
WRTL8201CL.
W I
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0 .C Input.
WW
TW
.
1
0
WW .100Y.C
T
M.T
.
.
1
TPRX+
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M
.
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W
M
O
W
C
.
O
W
W
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.C
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receive
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W30W .1Differential
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00Y
WW .100YTPRXM100Base-FX,
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M
O
W
M
O
W
C
.
O
W
W
10Base-T
modes.
C
W
.
Y
W
C
W
Y
W
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W
00
W
WW .100Y.
M.T
.100
W.1 Y.COM W
M.T
O
W
O
W
W
C
.
W
W
Y
W
.T
W
Y.C
W
WW 5.5.
.100
M.T
.100
Interface
OM
W
M.T Configuration
.100 Device
O
W
C
.
O
W
W
C
W
Y
W
WW .100Y.
.TW
WW .100Y.C M.TW
M.T
.100
MConfiguration
O
W
Table
5.
Device
Interface
O
W
C
.
O
W
W
W
Y
W
.C
Y.C
W
.TW
WW .1Name
M.T
.100
.TW Pin No.W Description
100
00Y
Type
M
.
O
W
M
O
W
C
.
W
W
W
.CO I .TW 43 WW
0Y also isolate
Y.C the RTL8201CL
WMAC.
Set high
This
.TW from the
00isolate
WW ISOLATE
M.Tthe MDC/MDIO
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1to
00Y
M
.
O
1
W
M
.
O
W
C
O
W
interface.
mode, the power
consumption
W pin can be
.C In this
Yis. minimum..TThis
W
WW
Wmanagement
.TorW
100
00Y to GND
WW .100Y.C M.TW
M
.
1
M
.
O
directly
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W
O
C
W
.C
WW
.CO
0Y.pin
WWmode.
TW
0Ythe
W
.TW into repeater
Set high .to10put
RTL8201CL
can
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10This
WW RPTR
M
.
00Y I M.TW 40
M
O
1
W
.
O
W
O
W
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WW .100Y.C M.TW
W
0Y.orCVCC.M.TW
Y.C
WW to.1GND
0
0
WW
T
.
0
O
1
SPEED
LIOM
39
This pin
is latched .to
input during a power on W
or W
reset condition.
to put
W.
CO
Y.C Set .high
WW
C
W
.
0
Y
W
TWto GND
W
W
0
0
Y
W
T
.
1
0
0
W
T
the
RTL8201CL
into
100Mbps
operation.
This
pin
can
be
directly
connected
M
.
.
1
0
M
.
O
W
O
W
OM
W.1
or VCC.
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
Wcondition.
O during a power on or reset
DUPLEX
LI O
38
This pinW
is W
latched to input
W
Y.CSet high.TtoW
W
0VCC.
Y.Cpin can
WW
0
0
T
.
1
0
WW .100Y.C M.TW
.
enableWfull duplex.
This
be
directly
connected
to
GND
or
OM
W.1 Y.COM W
.C
WW
W LIY.CO 37 W This pin isWlatched
Y
0
W
TW
W
ANE
to
input
during
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power
on
or
reset
condition.
Set
high
W
.T
W
M.to
.10
.T
100
00
M
.
O
1
W
M
.
O
W
C
.
enable
Auto-negotiation
mode,
set
low
to
force
mode.
This
pin
can
be
directly
O
W
W
W
.C
Y
W
W
.TW
00Y
WW .100Y.C M.TW connectedW
M.T
.100
to GND
or.1VCC.
M
O
W
O
W
C
O
W
W
Y. connected
W
W mode. This
Y.C into.TLDPS
WW
LDPS
pin can.1be00
directly
WW .I100Y.C 41M.TWSet high toWput the RTL8201CL
M.T
100
M
.
O
W
O
W
C
O
W
to GND or VCC.W
See 7.7 Power
Link Down, Power
and
Y.Isolation
WWSaving,
.TW
0Y.CDown,
W
.TW
100
0information.
WW .100Y.C M.TW
M
.
1
M
.
Modes,
page
20,
for
more
O
W
O
W
.C
O
W
W
Y.C a power
.TW
W pin is latched
00Yhigh to M
WW to input
MII/SNIBWWLI/O 00Y.C
44
condition..1Pull
.TWon or reset W
00during
.TThis
1
M
.
O set
1
W
M
.
O
W
C
.
O
W
W
C
the
Set low for SNI
pin can be .TW
W MII mode
W mode..1This
WRTL8201CL
00Y
0Y. operation.
Winto
.TW
WW .100Y.C M.T
10VCC.
M
.
OM
W
directly
connected
to
GND
or
O
W
O
W
W
W
.C
Y.C
W
C
W
.
0
Y
W
W
W
0
0
Y
W
T
.
W
M.T
.1
.T
10
00
M
.
O
1
W
M
.
O
W
C
O
W
WW .100Y.
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
.C
WW .100Y.C M.TW
WW 00Y.CO .TWAddress
WWConfiguration
.TW
5.6. LED WInterface/PHY
00Y
1
M
.
1
M
.
WW 00Y.CO .TW
W
WW 00Y.CO .TW
CO
.
W
W
W
Y
W
0
W
T
M
.1 address
These five pins are latched
RTL8201CL
during W
power
up O
reset
PHY
.
M to configure the
.1
W
M
.10into the
CO
O
W
W
C
W
.
Y.used
W
C
W
.
0
Y
W
W
W
[0:4] used for the MII
management
register
interface.
In
normal
operation,
after
initial
reset,
they
are
0
0
Y
W
T
.
W
M.T
.1
.T
10
00
M
.
O
1
W
M
.
O
W
C
W
W
Y. by
CO The
as driving pins for status
driving polarity,
is W
determined
W high, W
.LEDs.
Y.Clow or.Tactive
WW .active
WWindicator
M.T
.100
.TW
100
00Y
M
O
1
W
M
.
O
W
O [4:0] during power-up
each latched status of the
PHY
reset. If the latched status W
is W
High, then
it
W address
0Y.C
.TW
Y.C
WW .100Y.C M.TW
10PHY
WW
M
.
.TW then it will
00status
O
1
W
M
.
will be active low. If the
latched
is
Low,
be
active
high.
See
section
7.5
LED
and
O
W
WW .100Y.C M.T
WW 00Y.CO .TW
WW .100Y.C M.TW
Address Configuration,W
page 19,.1for
more information.
OM
WW 00Y.CO
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
0
W
.1
W.1
M.T
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OM
W
O
W
W
C
.
W
C
W
Y
W
W
W
WW .100Y.
M.T
.100
M.T
O
W
O
W
C
.
W
W
Y
W
WW .100Y.C M.TW
M.T
.100
O
W
O
W
C
.
Single-Chip/Port 10/100 Fast Ethernet
6
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
WW PHYceiver
M.T
.100
W
O
W
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
Table 6. LED
W
Y.C Configuration
W Interface/PHY
0
WW Address
0
T
.
1
M.T
.
MDescription
O
W
Name
Type
Pin No.
O
C
W
Y.C
WW .100Y.
.TW
M.T
PHYAD0/
LI/O
PHY
Address [0].
M
.1009
O
W
O
W
C
W
WW .100Y.
LED0
.TW
WW .100Y.C Link
.TLED.
M
M
O
W
O
W
linked.
W
.C Lit when
Y.C
.TW
WW .110
TW [1]. W
.Address
100
00Y PHY
M
.
.TW
PHYAD1/
LI/O
M
O
W
M
O
W
.C
O
W
W
LED1
Duplex
W
00Y
Y.C
WW .100Y.C FullM
TW LED. W
.
1
0
T
M.T
.
.
0
O
1
W
M
.
O
W
C
.
O
W
W
Lit when inWFull DuplexWoperation.
W
Y
.C
WW 12.100Y.CPHY M
.T [2].
M.T
.100
.TW
00Y PHYAD2/
LI/O
Address
O
1
W
M
.
O
W
C
W
.C LED Mode:
Y.
WW 00Y.COLED2
.TW
WW .100YCL
LED
.TW 10 ACT W
100
M
.
.TW
M
O
1
W
M
.
O
W
O
W
Blinking
when
data.
.C
Y.C
WorWreceiving
.TW
WW .100Y
.TWtransmitting
100
WW .100Y.C M.TW
M
.
M
O
W
BL
LED
Mode:
Link
10
/
ACT
LED
O
W
.C
O
W
W in 10Base-T
0Yblinking
WWmode,
.TW transmitting or
0Y.C when
WW .10Active
.T
linked
10and
WW .100Y.C M.TW
Mwhen
.
M
O
W
O
W
C
.
O
W
W
.C data..TW
.C
WW .100Y
WW .1receiving
00Y Address
WW .100Y
M.T
.TWLI/O
M
O
W
M
PHYAD3/
13
PHY
[3].
O
W
C
W
W
W
Y.
W
.CO .TW
Y.C
WW .CL
.T
WW .100YLED3
100 ACT LEDW
M.T
.100
100LED Mode:
M
O
W
M
O
W
O
W
.C
Y.C
transmitting
or receiving
WW data.
.TW
WW Blinking
.TW
100
00Y whenM
WW .100Y.C M.TW
M
.
1
.
O
W
100 / ACT LEDW
WBL LEDYMode:
.C
O
W
W
.CO Link
00Y when
WW Active
.TinW100Base-T W
00when linked
WW .100Y.C M.TW
M.T
mode, W
and.1blinking
transmitting or
1
M
.
O
O
W
C
.
O
W
W
W
.C
Y
W
WWreceiving
00Ydata. M.TW
WW .100Y.C M.TW
M.T
.100
1Address
.
O
W
O
W
C
PHYAD4/
LI/O
15
PHY
[4].
.
W
W
W
.CO .TW
Y.C
WW .100Y
WW
WW LED4
M.T
100LED. OM.T
00Y
Collision
.
O
1
W
M
.
W
C
O
W
.C
W when
WW .100Y.
.TW
WBlinks
TW
.occur.
00Ycollisions
WW .100Y.C M.TW
M
1
M
.
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W
Oand GroundWPins
5.7.
WW 00Y.CO .TW
WPower
.CO .TW
C
.
Y
W
W
W
0
Y
W
0
W
M
.1
.T
00
OMGround Pins
W.1Power
WW 00Y.CO .TW
W.1 Y.COM W
.C
Table
and
W7.
W
Y
W
W
0
W
T
.
0
0
W
M
.1
.T
W.1 Y.COM W
NameW.10 TypeCOM Pin No.
Description
WW 00Y.CO .TW
W
.
W
W
W
W Analog.1Power
.T
00 Input.
W
.T36
00PY
AVDD33
3.3V
W.1 Y.COM W
OM
W
W
W.1 Y.COM W
C
.
W
W
Y
W
W
3.3V
Wpower supply
.Tcircuit; should be wellWdecoupled.
W
M.T
.100
.T
100 for analog
00
M
.
O
1
M
.
O
W
C
.
O
W
AGNDWW P
Analog W
Ground. Y.C
W
Y
W
.C 29,.35
W
Wbe
.TGND
W
TW
M.T
.100
100 to a O
00Y
M
.
Should
connected
larger
plane.
O
1
W
M
.
W
C
O
W
W
W
Y.C
WW .100Y.
WW Power
DVDD33
WW .P100Y.C 14,M48
M.T
.TW 3.3V Digital
100Input. OM.T
.
O
W
W
O
W
.C circuit.
3.3V power
digital
WW .100Y.C M.TW
WWsupply.1for
.TW
00Y
WW P.100Y.C
.TW Digital Ground.
M
O
W
M
DGND
11,
17,
45
O
W
WW 00Y.CO .TW
WW .100Y.C M.TW
WW .100Y.C M.TW Should beW
connected
to
a
larger
GND
plane.
O
W
OM
W.1
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
00
M
.1
OM Pins
WW 00Y.CO .TW
W.1 Other
WW 00Y.CO .TW
C
5.8. Reset
and
.
W
W
W
Y
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM Table
W
W
W
8.
Reset
and
Other
Pins
W
W
.T
00
W
.T
100
W.1 Y.COM W
W.1 Y.COM W
OMDescription
W
Name
Type WW. Pin No.
W
C
.
W
W
.T
W
M.T
.100
.TW
100
0420Y
M
.
O
1
W
M
.
RESETB
I
RESETB.
O
W
C
.
O
W
W
W
W
0Y
0Y.C reset,
.TW
WW .100Y.C Set
TWto reset theW
chip. For.1a0complete
this pin mustW
be asserted
M.T
.10low
.low
M
O
W
M
O
W
C
O
W
W
WW .100Y.
W 10ms. WW .100Y.C M.TW
WW .100Y.C forMat.Tleast
M.T
O
W
O
W
PWFBOUT
O
Power
Feedback Output.W
.C
O
W32
W
Y.C
WW .1and
.TW
00Y
W tantalum
.Tfrequency
00capacitor
WW .100Y.CBe sure
M
.TtoWconnect a 22uF
for
compensation
1
M
.
O
W
M
O
W
O
W
WW a .100Y.C M.T
a 0.1uF .capacitor
for noise
de-coupling.
Then connect
W
0Y.C
WW
TW this pin through
.
0
WW .100Y.C
T
1
M
.
O
W
ferrite
is outlinedWinW
section
OMbead to PWFBIN (pin8).
W
.CO method
Y.C
WWThe connection
C
W
.
0
Y
W
W
0
0
Y
W
T
.
1
0
0
W
.T
0 7.11 3.3V
Voltage
OMCircuit, page 22. WW.
W.1 Conversion
OM Power Supply andW
W.1 Power
.Cdescription
C
W
.
Y
W
W
W
PWFBIN
I
8
Feedback
Input.
See
the
PWFBOUT
0
Y
W
W
M.T above.
.10
100Not Connected.
M.T
O
W
O
C
NC
27WW.
.
W
W
Y
W
Y.C
W
W
M.T
.100
M.T
.100
O
W
O
W
C
.
Single-Chip/Port 10/100 Fast Ethernet
7
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
WW PHYceiver
M.T
.100
W
O
W
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
W
WW .100Y.C M.TW
T
.
M
O
W
.CO .TW
Y
WW .100Y.C M.TW
0
0
1
M
.
W
O and usage of the W
This section describes
registers
available
the RTL8201CL.
Wthe functions
.CO .in
W
TW
00Y
WW .100Y.C M.TW
1
M
.
O
In this section the following
abbreviations
are used: WW
W
.CO .TW
W
W
00Y
WW .100Y.C M.TW
1
T
M
.
.
W
O
RO:
.CO .TW
OM Read Only WW
W
C
.
Y
C
W
.
0
Y
W
0
W
.T
.TW
100
00Y
W.1 Y.COM W
OM
OM Read/Write WW.
W
W.1 Y.RW:
C
.
C
W
Y
W
.T
W
00
W
.T
.100
W.1 Y.COM W
M.T
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
W
.T
00
Y.
W0 Basic
TW
M.T Control Register
.100 Mode
W.1 Y.COM W
.100 6.1.OM.Register
O
W
W
W
C
.
W
Y
W
.T
WW Table
WW .100Y.C M.TW
.100Register
M.T 0 Basic Mode W
.1009. Register
Control
OM
W
O
W
C
.
O
W
C
W
Y
W
.C
Y.
W
W
.TW
Description
Mode
Default
WW .100YAddress
M.T
.100
.TWName
100
M
.
O
W
M
O
W
C
.
O
W
W
C
W
.
Y
W
C
0:15
Reset
This
bit
sets
the
status
and
control
registers
of
the
PHY
in
a
default
RW
0
W
.
0
Y
W
W
.T
WW .100Y
M.T
.10
.TW
100is self-clearing.
M
.
O
W
M
O
state.
This
bit
W
C
O
W
W
W
Y.C
WW .100Y.
.TW
WW .100Y.C M.TW
M.T
1: W
Software .reset
100
M
O
W
O
W
O
W
.C
0: Normal
WW .100Y.C M.TW
WW operation
.TW
00Y
WW .100Y.C M.TW
1
M
.
W
O
W loopback
enables
TXD3:0
to
0
.CO .TWRW
W 0:14 O Loopback This bit W
W data nibbles
0Ythe
Y.C of transmit
WW
0
0
W
T
.
1
0
WW .100Y.C M.TW
M
.
1
receive data W
path.
M
.
O
W
O
W
.CO .TW
WW .100Y.C M.TW
loopback
WW
00Y
WW .100Y.C M.TW 1: Enable
1
M
.
O
0: Normal operation
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T This bit sets theW
M
.1
0:13
Spd_Set
network
speed.
0
.100
OM
WW 00Y.CO RW
W
.CO .TW
W
C
.
Y
W
TW
W
.
W
0
Y
W
1:
100Mbps
1
0
0
W
T
M
.
.
1
0
.
O
W
OM
OM
W.1
0: 10Mbps WW
W
Y.C
WW .100Y.C M.TW
0
W
T
.
0
WW .100Y.C M.TW
O
After completing auto
this bit will reflect theW
Speed
W status.
OM
W.1negotiation,
O
W
W
Y.C
0
W
W100Base-TWW .100Y.C M.TW
0
1
WW .100Y.C M.T1:
M.T
.
O
W
O
W
C
.
O
W
W
0:W
10Base-T) WW
W
Y.C
WW .100Y
.Tbit=1
WW .100Y.C M.T
M.T
1is00enabled,Othis
M
.
O
W
When
100Base-FX
mode
and
is
read
only.
W
C
O
WW .100Y. RWM.TW 1
WW 00Auto
0Y.C auto-negotiation
Y.C
WW the
.TW
0NWay
0:12
This
function.
W
.TWbit enables/disables
1
M
.
O
1
W
M
.
O
W
WW bits
auto-negotiation;
0:13
W be ignored.
.CO 1: .Enable
Y.C and 0:8.Twill
WW .100Y.C M.TW
W
0
Y
W
0
0
WW Negotiation
T
0
.1
O
W
OM0:8 will determine theWlink
0: Disable auto-negotiation;
W.1Enable OM
W
.Cand
Y.C
WW bits000:13
W
0
Y
W
W
0
W
T
.
1
WW .100Y.C speed
T
and
the
data
transfer
mode,
respectively.
M.T
.
.
1
M
.
O
W
M
O
W
C
.
O
W
W
C bit=0 Tand
W
Y
mode
W
W
0Y.this
WWis enabled,
. Wis read only.
WW .100Y.C When
M.T
.100
.T100Base-FX
10the
M
.
O
W
M
O
W
C
0:11
Power
Down
This
bit
turns
down
the
power
of
PHY
chip,
including
the
internal
RW
0
O
W
W
W
W
0Y.
Y.C
WW
WThe
.Talive
WW .100Y.Ccrystal
TW
M.T
.oscillator
circuit.
MDC,
isM
still
for accessing W.10
100MDIO O
.
O
M
W
W
COMAC.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.the
.
M
1: Power
O down
WW 00Y.CO .TW
W
WW 00Y.CO .TW
W
W
W
WW .100Y0:.CNormal
T
.
W.1 Y.COM W
W.1 Y.COM W
OM operation
W
W
W
C
.
W
W
0:10
Reserved 00Y
W
.T
W
M.T
.100
.TW
100
M
.
O
1
W
M
.
O
W
C
.
O allows the NWay auto-negotiation
W This.C
0:9
Restart
Auto
bits
to be
reset.
.C
WW RW.100Y 0 M.TW
WW .100Yfunction
.TW
WW .101:0Y
.TW
M
O
Negotiation
Re-start
auto-negotiation
W
M
O
W
O
W
WW .100Y.C M.TW
W
Y.C operation
WW .100Y.C M.TW
WW .10:00Normal
T
.
O
W
OM
WW 00Y.C
0:8
Duplex
bit
the duplex
mode ifW
auto-negotiation
isO
disabled
RW
W
.Csets
0Y.0C M.TW
WW
WW This
W
0
Y
T
.
1
0
W
T
.
.
M
.1
.10 0:12=0).OM
Mode W(bit
WW 00Y.CO .TW
WW 00Y.CO .TW
.C
W
W
Y
W
0
duplex
WW 1:.Full
T
10
W.1 Y.COM W
M.
W.1 Y.COM W
O
W
W
W
C
0:
Half
duplex
.
W
.T
00
0
W
.T
0Y
WW After
.TW
.10reflect
W.1 Y.COM W
M
.10completing
auto-negotiation,
thisW
bitW
will
the
duplex
OM
O
W
W
C
.
C
W
Y
W
.T
W
00
W
WWstatus..100Y.
M.T
.100
W.1 Y.COM W
M.T
O
W
O
W
W
C
.
1: Full duplex
W
.C
W
.T
W
WW .100Y
WW
.100
00Y
M.T
OM
W
M.T
.1duplex
O
W
0: Half
C
.
O
W
W
C
Y
W
W
W
W
Y.C
WW .100Y.
M.T
.100
0:7:0
Reserved W
M.T
O
W
M.T
.100
O
W
C
.
O
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
.100
W
O
W
O
W
WW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
8
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

6.

Register Descriptions

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
T
.
1
6.2. Register 1 Basic
OM
W.Register
OM Mode Status
W
C
.
Y.C
W
0
Y
W
.TW
0
0
T
.
M
.1 Status
Mode
Register
M10. Register 1 Basic
.10 Table
O
W
O
W
C
.C
W
WW .100Y.
.TW
WName
Address
Mode
Default
.TW
00Y Description
M
1
M
.
O
W
O
W
.C
W
C
W
.
Y
W
1:15
100Base-T4
1:
Enable
100Base-T4
support
RO
0
W
0
Y
W
T
.
W
W
.10
M.T100Base-T4 support
.100 0: Suppress
OM
W
M.T
O
W
C
.
O
W
C
W
Y
.C 1:14
Y.Enable 100Base-TX
W
WW FD.1001:
.TW
M.T
.100
full duplexW
support
RO
1
.TW 100Base_TX_
00Y
M
O
1
M
.
O
W
C
.
O
W support
W
W
.C
Y
W
C
W
.
0:
Suppress
100Base-TX
full
duplex
0
Y
W
T
.
W
0
0
Y
W
T
.
0
M
.1
M.T
.100
OM
W.1 1: Enable
half duplex
support0Y.CO
RO
1
WW
W
Y.C 100Base-TX
W
WW 00Y.CO1:13 .TW100BASE_TX_HD
.TW
0
WW .10:00Suppress
T
.
1
M
.
100Base-TX
half
duplex
support
M
O
1
W
M
.
O
W
.C
O
W
W
.TW
support .100Y
RO
1
0Y.C 10Base-T
WW .1:10Enable
.TWfull duplexW
WW .100Y.C1:12M.TW10Base_T_FD
M
M
O
W
O
W
C
.
O
W
W
0:
Suppress
10Base-T
full
duplex
support
C
W
.
Y
W
WW 1:.1Enable
.TW
00Y 10Base-T
WW .100Y.C
M.T
.100
.TW
M
1:11
10_Base_T_HD
half
duplex
support
RO
1
O
W
M
O
W
C
.
O
W
W
W
.C10Base-T
Y
W 0: Suppress
C
W
.
0
Y
W
T
W
.
W
0
0
Y
W
T
half
duplex
support
.
W
M
.1
.T
00
M
.10
OM
WW 00Y.CO .TW
W.1 1:10~7
.CO .TW
Reserved WWW
C
.
Y
W
W
W
0
Y
W
M
.T
00
.10
W.1 with
The
will accept management
1
OM
WRTL8201CL
.CO .TW RO
OM MF Preamble
Wframes
W.1 1:6
C
.
Y
W
C
W
.
0
Y
W
W
W
0
0
Y
W
T
.
1
0
0
W
T
Suppression
preamble
suppressed.
M
.
.
0
O
W
OM
W.1 Y
OM
W.1
Y.CSMI .TW
of.C
32 preamble
Wbits are required
0first
WW for .the
0
0
WAWminimum
T
.
1
0
WW .100Y.C M.TW
M
Wrequired
OMafter reset. One idle bit
read/write
is
W.1 transaction
.CO .TW
O
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
Y
W
.T transactions as per
W
between any
.10 802.3u
.100two management
OM
WIEEE
M.T
.100
OM
W
O
W
W
C
W
.
Y.C
W
C
W
.
specifications.
0
Y
W
W
W
0
0
Y
W
T
.
0
0
W
M.T
.1
.T
1
0
M
.
O
1
W
M
.
O
W
C
Auto
process completed
RO
0
O Negotiation 1: Auto-negotiation
W
W1:5
Y.
.TW
WW .100Y.C
TWcompleted W
.not
100
WW .100Y.C Complete
M
.
.TW
0: Auto-negotiation
process
M
O
W
M
O
W
.C
O
W
W
.TW
Remote .Fault
1: Remote
0
0Y.C detected
WW fault
.TW (cleared onWread)W.100Y OMRO
0condition
WW 1:4 .100Y.C
TW
1
M
.
M
O
W
C
.
O
0:
No
remote
fault
condition
detected
W
W
C
W
Y
W
Y.
W
.TW
WW .100Y.C M.TW WhenWin 100Base-FX
M.T
.100
100
mode,
this bit means anWin-band
M
.
O
O
W
C
.
O
W
W
has been
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WW0 .100Y
WW .100Y.C
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WW .100Y.C M.TW signal Far-End-Fault
M.T
M
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page
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W
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WW .100Y. ROM.TW 1
WW Auto
WW
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00Y failM
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WW .100Y.C M.TW
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0
WW 00Y.CO .TW
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WW .100Y.RO
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Y
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M
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
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1
WW 00Y.CO
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W
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W
W
W
Y
W
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W
M
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00
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OM
OM 11. Register 2 PHY
WW 00Y.CO .TW
W.1 Y.CTable
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WWIdentifier
W
1
Y
W
W
W
0
W
T
.
0
W
M
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00
W.1 Y.COM W
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OM
Address
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WW 0Default
W.1 Y.Description
Y
W
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0
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W
W
W
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W
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W.1 0000
2:15~0
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RO
OMRTL8201CL
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OM
W
W.1 Y
Y
W
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W
.
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W
W
0
W
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W
W.1 Y.COM W
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W.1 Y.COM W
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W
W
W
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W
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W
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W
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W
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W
Y
W
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W
00
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6.4. RegisterW3W PHY
Register
M.T
.1020
W.1 Y.COM W
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O
W
O
W
W
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W
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W
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WW .1Register
00Y
WW .1Table
.100
2 M.T
00Y 12. Register
OM
W
M.T 3 PHY Identifier
O
W
C
.
O
W
W
C
Y
W
Address
NameWW Description
ModeW Default
Y.C
WW .100Y.
M.T
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M.T
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100
W
M
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O
W
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WW .100Y.
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W
W
Y
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WW .100Y.C M.TW
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.
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9
Track ID: JATR-1076-21 Rev. 1.24
W
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WW .100Y
WW PHYceiver
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W
O
W
WW
WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C
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0
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OM
W.1
WW .100Y.C M.TW
WW 00Y.CO .TW
W
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6.5. Register 4 Auto-Negotiation
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Register (ANAR)
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OM
W
OM
W
C
W
.
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W
0
Y
W
T
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.
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This register containsWthe
device
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OM abilities of this W
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W
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WW .100Y.C M.TW
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W.1 Y.COM W
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W
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Table 13.
4 Auto-Negotiation
Advertisement
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(ANAR)
.100
M
.10Register
OM
W
M.T
O
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O
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W
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W
C
Address
Name
Description
Mode
Default
W
.
0
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W
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W
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M.
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100
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M
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RO
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WW .100Y
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W
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WW 00Y.CO .TW
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WW .100Y.5 Auto-Negotiation
6.6. Register
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M
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OM
W.1 Register
M.T
O
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.
O
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W
C
.
Y
W
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100
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WW .100Y.C M.TW
M
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(ANLPAR)
O
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O
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y
WW 00Y.CO .TW
WW .100Y.C M.TW
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14.
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Register (ANLPAR)
.1 RegisterO5MAuto-Negotiation W
O
W
C
.
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WWMode.100Y
W
.TW
W
.TW
00Y
WName
M
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Default
.TW
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M
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1
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M
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WW 00Next
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Y
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RO
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W
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WW .100Y.C M.TW
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O
W
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W
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WW
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WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
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10
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Y
W
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WW .100Y.C M.TW
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WW .100Y.C
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O
W
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0
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.
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Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
Address
Name
Description
Mode
Default
W
WW .100Y.C M.TW
T
.
Mflow control is supported
O
W
O
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5:10
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1:
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W
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WW by
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WW
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1
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W
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W
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W
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W
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W
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WW
10link
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W
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C
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Ypartner .TW
W
W
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0
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W
T
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1
0
0
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.
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M
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RO
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WW 1:0100Base-TX
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Y
0
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W
M.T
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1 100Base-TX
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M
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M
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W
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W
C
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W
O
W
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WW0: 10Base-T
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1
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WW .100Y.C M.TW
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M
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1
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O
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WW .100Y.C M.TW RO
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WW .100Y.C
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W
WW is.1established
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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W 5:4~0 O Selector
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WW
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0
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W
T
.
1
0
WW .100Y.C M.TW
M
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1
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M
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O
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O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
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00
M
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OM
WW
W.1 Register
Y
WW 00Y.CO Expansion
C
W
.
0
W
W
6.7.
6
Auto-Negotiation
Register
(ANER)
W
0
Y
W
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W
M.
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W.1 Y.COM W
M.T
.100
O
W
O
W
W
C
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W
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Y
W
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WWfor .NWay
This
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WWregister
.100
100 auto-negotiation.
M.T
OM
W
M.T
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O
W
C
.
O
W
W
C
W
Y
W
Y.
W
WW
.TExpansion
Table
6 Auto-Negotiation
Register
100
WW .100Y.C M
M.T
.(ANER)
.TW15. Register
100
M
.
O
W
O
W
C
.
O
W
Address
Name TWDescription
WW .100Y Mode
WW 00Y.C
WW .100Y.C M.TW
W
M.T Default
.
O
1
W
M
.
O
W
C
6:15~5
This bit is permanently
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CO
W
WW .100Y.
WW 00Reserved
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Y.MLF
WW a multiple
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W6:4
M
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M
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RO
0
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1
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M
.
O
W
O
W
WW .100Y.C M.TW
WFault occurred
WW .100Y.C M.TW
WW .100Y.C M.T1:
O
W
O
W
0:W
No fault occurred
WW .100Y.C M.TW
WW 00Y.CO .T
WW .100Y.C M.TW
W
6:3
link partner supports Next Page negotiation.
RO
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OM Indicates whether the
WW 00Y
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WW 00Y.CO .TW
C
.
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W
W
Y
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1:
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1
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M
.
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1
00
WW 00Y.CO .TW
W.1 Y.COM0: NotWsupported WW. 0Y.COM W
W
W
W
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W
M
.1
.T bit indicates whetherWthe
M. to send additional
.10local node
.100
6:2
NP_ABLE
This
.CO 0.TW
OM
WW RO
W
.CO is able
Y
W
C
W
.
0
Y
W
W
W
0
0
Y
W
.T
W
Next
00
.10
W.1 Y.COM W
M.TPages. Internal useWonly.
OM
W
W
W.1 Y.COThis
C
.
W
6:1
PAGE_RX
bit
is
set
when
a
new
Link
Code
Word
Page
has
been
0 .T
Y
W
W
W
W
.T
100
W
.RO
Mauto-negotiation
.100 whenOthe
OM
W
M.T It is automatically
.100
W
received.
cleared
C
.
O
W
W
C
W
Y
Y. read .by
W
WW (register
TW
WW .100Y.Clink M
M.T
.100
.TW ability register
partners
management.
100 5) is O
M
.
O
W
W
C
.
W
W auto-negotiation.
CO
Y.C
WW RO.100Y 0 M.TW
6:0
LP_NW_ABLE
Link partner
NWay
.TW
WW .100Y.1:
.TW supportsW
100
M
.
O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
00
M
.1
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .T
W.1 Y.COM W
W
W
W
W
.T
00
W
W.1 Y.COM
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
.T
WW .100Y
.100
.TW
100
M
.
W
M
O
W
O
W
WW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
11
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
T
.
6.8. Register 16 NWay
M
W.1 Y(NSR)
OM Setup Register
.CO .TW
W
C
.
W
0
Y
W
0
0
T
.
0 Table M
M
.1 Register
16. Register 16 NWayW
Setup
W.1 Y
.CO (NSR)
W
CO
.
Y
W
W
0
W
.TW
0
0
W
T
Address
Name .10 Description
Mode
Default
.
1
M
.
M
O
W
O
W
.C
W
C
W
.
Y
W
16:15~12
Reserved
W
0
Y
W
T
.
W
00
M
.10
.TW
M.T
OPin
ENNWLE
indicates linkpulse WW
RW
0
W.1 1: LED4
.CO .TW
OM16:11
C
.
Y
W
C
W
.
0
Y
W
W
0
0Auto-negotiation
Y
W
T speeds up internal timer
.
1
0
0
T
M
.
.
16:10
Testfun
1:
RW
0
1
0
M
.
O
1
W
W
.C
OM
W.
W
.CO to .loopback
Set
modeWW
RW
0
W NWLPBK
00Y
0YNWay
Y.C 16:9
WW .1:
TW
1
0
0
T
M.T
.
.
1
0
M
O
1
W
M
.
O
W
C
.
O
16:8~3
Reserved
W
W
C
W
.
Y
W
C
W
W
W
Y. 16:2.TW FLAGABD
W
00Y
.100state OM.T
M.T experienced ability
1:.1Auto-negotiation
detect
RO
0
W
M
.100
O
W
.C
O
W
W
C
.
W
0Y
Y
W detection
TW
.
0
0
WW 1: Auto-negotiation
T
experienced
parallel
fault
state
RO
0
.
1
0
WW .100Y.C 16:1M.TW FLAGPDF
M
.
.1
O
W
OM experienced link status
WAuto-negotiation
O
W
W
Y.C
16:0
FLAGLSCWW1:
state
RO
0
W
0
Y.C
WW check
0
0
T
.
1
0
WW .100Y.C M.TW
M.T
.
1
M
.
O
W
O
W
C
.
O
W
W
WW .100Y
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
O
W
O
W
C
W
W
.CO .TW
WW .100Y.
WW .100Y.C M.TW
WW 6.9.
M.TMask
00Y Register
O
1
W
M
.
17
Loopback,
Bypass,
Receiver
Error
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
Register
(LBREMR)
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
WMask
W
W
.C
Y.C (LBREMR)
C
Table 17.
Register W
17W
Loopback,
Bypass,.TReceiver
Error
Register
W
.
0
Y
W
W
W
0
0
Y
1
0
0
W
M.T
.
.T
1
0
M
.
O
1
W
M
.
O
W
C
Address
Name
Description
Mode
Default
.
O
W
W
W
Y.C
WW .100Y
.TW
W
0
Y.C
W
T
.
0
0
WW 17:15
T
M
.
1
0
M
.
RPTR
Set to 1 to put
into repeater mode. W
0
O RW
W the RTL8201CL
W.1 Y.COM
.CO .TW of the 4B/5B
0Y.C MRW
WW& 5B/4B
TW
.
W
0
0Y
WWof this.1bit
BP_4B5B
Assertion
allows bypassing
0
1
0
0
WW 17:14
T
.
.
0
O
W
OM
W
OM
W.1
WW .100Y.C M.TW
W encoder.
WW .100Y.C M.TW
WW17:13.100Y.CBP_SCR
T
.
O RW
W
Assertion of this
of the
0
O
W bit allows bypassing
OM
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW scrambler/descrambler.
O
WW 00Y.CORW .TW 0
W
.COPower.TSaving
WWLink00Down
C
17:12
LDPS
Set
to
1
to
enable
mode.
W
.
Y
W
W
W
Y
W
0
W
M
.1
.T Set to 1 to powerW
M
.1
17:11W.10 AnalogOFF
function
of transmitter and
RW
OM
WW 00Y.CO
.CO
W down 0analog
C
W
.
Y
W
TW 0
W
.
W
0
Y
W
T
.
1
0
W
T
M
.
.
receiver.
1
0
O
W
OM
W.
W.1 Y.COM Reserved.
WW .100Y.C M.TW
17:10
W
WW .100Y.C M.TW
WW .100Reserve
T
.
WLoopback.
.CO .TW
17:9 WW
LB.COM Set to 1 to enableW
DSP
0
WW 00YRW
.CO .TW
Y
W
W
0
Y
W
1
0
0
W
T
M
.
.
1
0
M
.
17:8
F_Link_10
Used
to
logic
force
good
link
in
10Mbps
for
diagnostic
purposes.
RW
1
O
1
W
W
OM
W.
W
.CO .T
Y.C
WW .100RW
Wto logic force
0inY100Mbps
Y.C
WW
17:7WW F_Link_100
Used
good link
forWdiagnostic purposes.
0
0
T
M.T1
.
1
0
M
.
O
1
W
M
.
O
W
C
C 10Base-T.
.in
17:6 WW JBEN
Jabber
1W
W Function
.CO Set.TtoW1 to enable W
0Y.
WW .10RW
.TW
00Y error detection
W
M.0T
1code
00Y
M
.
O
1
W
M
.
17:5
CODE_err
Assertion
of
this
bit
causes
a
to
be
reported.
RW
O
W
.C
W
W
.C
W
.CO Assertion
TW
00Y
TW detection W
.error
00Y
M
17:4 WW PME_err
causes a .pre-mature
end
to be W.1RW
0.
.TW of this bitW
1
00Y
M
O
1
M
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C reported.
.TW
M
17:3
LINK_err
of this bit causes
toW
be reported. WWRW Y.CO0
O
W
CO
.detection
WaWlink error
.CAssertion
Y
W
W
.TW
W
0
Y
W
T
.
0
0
W
T
.100
. of this bit causes a detection
1
0
17:2
PKT_err
Assertion
of packet
errors due to
RW
0M
M
.
O
1
W
M
.
O
W
C
.
W
W
CO ms time-out
WW .100Y
WW .100Y.C M.TW
WW .100Y.722
M.T
.TW to be reported.
O
W
M
O
W
C
W
17:1
FXMODE
This
whether Fiber
.C
W Mode00isYEnabled.
.CObit indicates
WWRO .100Y. 0 M.TW
.TW
WW .100YThis
.TW whetherW
1
M
.
17:0
RMIIMODE
bit
indicates
RMII
mode
is
Enabled.
RO
0 O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
00
M
.1
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .T
W.1 Y.COM W
W
W
W
W
.T
00
W
W.1 Y.COM
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
.T
WW .100Y
.100
.TW
100
M
.
W
M
O
W
O
W
WW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
12
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
T
.
6.10. Register 18 RX_ER
Counter
.1
OM
W(REC)
OM
W
C
.
Y.C
W
0
Y
W
.TW
0
0
T
.
M
.1 Counter
Table
(REC)
M 18. Register 18 RX_ER
.10
O
W
O
W
C
.C
W
WW .100Y.
.TW
W
Address
Name
Description
Mode
Default
.TW
00Y
M
1
M
.
O
W
O
W
.C
W
C
W
.
Y
W
18:15~0
RXERCNT
This
16-bit
counter
increments
by
1
for
each
invalid
packet
RO
H[0000]
W
0
Y
W
T
.
W
00
M
.10
.TW
M.Tvalue is valid while
aW
link is established.
OThe
W.1 received.
.CO .TW
OM
W
C
.
Y
W
C
W
.
0
Y
W
0
W
.T
00
.TW
00Y
W.1 Y.COM W
W.1 Y.COM W
W
W.1 Y.COM W
W
W
.T
00
W
.T
.100
W.1 Y.COM W
M.T
.100
OM
W
O
W
W
C
.
W
C
W Register
Y
W
W
.T
00
Y.
W19 SNR
TW
M.T
.100 Display
W.1 Y.COM W
M.Register
.100 6.11.
O
W
O
W
W
C
.
W
W
.T
00
WW .1Table
00Y 19. Register
WW .100Y.C M.TW
.1Register
M.T
19 SNR Display
OM
W
O
W
C
.
O
W
W
C
W Mode Default
Y
W
.C
Y.
W
.TW
WW .100YAddress
M.T
.100
.TW Name W Description
100
M
.
O
W
M
O
W
C
.
O
W
W
C Internal
W
Y
Reserved WW
Realtek 0
Test
Y.Mode
Wchange
Y.C
.TW use. Do not
100field without
WW .10019:15~4
M.T
.this
.TW
1 0approval.
M
.
O
W
M
O
Realteks
W
C
O
W
W
Y.
W
Y.C the Signal
WW value.
Y.C
WThese
.TW to Noise Ratio
WW .10019:3~0
M.T
.100
.TWSNR
4-bits
RW
0000
100 show O
M
.
O
W
M
W
.C
O
W
W
C
W
.
Y
W
C
W
.
0
Y
W
T
W
.
W
0
0
Y
W
.T
0
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
W.1 Y.COM W
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
Register
W Register
.T
W 6.12.
M.T
.100
.TW 25 Test
100
00Y
M
.
O
1
W
M
.
O
W
C
.
O
W
W
.C
WTest Register
WW .100Y
0YRegister
WWTable
.T25
WW .100Y.C M.TW
M.T
1020.
M
.
O
W
O
W
C
O
W
Description
Mode
WW .100Y.
.TW Default
WW .100Y.C M.TW
0Y.C Name
WWAddress
M
.TW
0
O
1
W
M
.
O
25:15~12
for
internal testing.
RW W
W
.C
WW
.COTest.TW Reserved
WW .100Y.C M
.T
.TbyWexternal PHY
00Y defined
WW
1
00Y PHYAD[4:0]
25:11~7
ReflectsW
the PHY
address
address
RO
00001
M
.
O
1
W
M
.
O
W
C
.
O
W
W
C
W
Y
W
0
W
T
.
0
WWpins..100Y.
T
.
1
WW .100Y.C M.TW configuration
M
.
M
W testing.
O
WW 00Y.CORO .TW
W
25:6~2
Test
Reserved for W
internal
.CO .TW
C
.
Y
W
W
W
0
Y
W
0
W25:1 .100 LINK10
M
.1
.T 1: 10Base-T link established
RO
0
W.1 Y.COM W
OM
WW 00Y.CO
W
W
C
.
W
TW
W
.
W
0
Y
W
T
0: No 10Base-T link established
.
1
0
0
W
T
M
.
.
1
0
O
W
OM
W.
OM 1: 100Base-FX or
W.1 LINK100
W100Base-TX
25:0
W
Y.Clink established
WW .100Y.CRO M.TW0
0
T
.
0
WW .100Y.C M.T0:WNo 100BaseWlink established
O
W
OM
W.1
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
.1
W.1 Y.COM W
M.T
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
.T
W
00
W
WW .100Y.
M.T
.100
W.1 Y.COM W
M.T
O
W
O
W
W
C
.
W
W
Y
W
.T
W
WW .100Y.C M.TW
.100
M.T
.100
OM
W
O
W
C
.
O
W
W
C
Y
W
W
.TW
WW .100Y.
WW .100Y.C M.TW
.100
M.T
OM
W
O
W
C
.
O
W
W
C
W
Y
W
WW .100Y.
.TW
WW .100Y.C M.TW
M.T
.100
M
O
W
O
W
C
.
O
W
W
WW .100Y
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
O
W
O
W
C
O
W
WW .100Y.
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
00
M
.1
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .T
W.1 Y.COM W
W
W
W
W
.T
00
W
W.1 Y.COM
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
.T
WW .100Y
.100
.TW
100
M
.
W
M
O
W
O
W
WW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
13
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW

W
M.T
RTL8201CL
O
W
Y.C
0
T
.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
O
W
W
WW .100Y.C M.TW
T
.
M
O
W
.CO .TW
Y
WW .100Y.C M.TW
0
0
1
M
.
O 10Base-T and
W
The RTL8201CL PHYceiver
that integrates
.CaOphysical
WW 00Yis
W layer device
WW .100Y.C M.TW
W
T
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Single-Chip/Port 10/100 Fast Ethernet
14
Track ID: JATR-1076-21 Rev. 1.24
W
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7.

Functional Description

W
M.T
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W.1
WW .100Y.C M.TW
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W
W
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W
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Idle Condition.
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W
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.
Single-Chip/Port 10/100 Fast Ethernet
15
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
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W
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W
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W
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W
W.1 100Mbps
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WW .100Y.C M.TW
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100
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W
W
W
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WW .100Y.
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WW .100Y
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W
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W
C
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.
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WW .100Y.
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.
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C Table
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WW .100Y
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.
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7.4. Hardware Configuration
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M
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Name
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WW .100Y.C M.TW
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W.1
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100TPTX+T
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WW .100Y.C M.TW
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W
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Figure
Cycle Timing-2
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W.1 Y.COM W
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W
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M.T
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Reception
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W
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WW .100Y
WW .100Y.C M.TW
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Table
Reception
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W Timing
Y.
W
WW 34. .MII
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WW .100Y.C M.TW
M.T Unit
.100Maximum
100
M
O
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Symbol
Description
Minimum
Typical
W
C
.
O
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W
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20
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W
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WW .100260
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200
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M
1
M
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W
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W
W
W
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width
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ns
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M
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10Mbps00Y.
140 .TW
200 W
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WW .100Y.C M.TW
M.Tns
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1
M
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ns W
Y
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WW .100Y.C M.TW
W
M.T
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1
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M
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C
10Mbps
400
ns W
WW .100Y.
WW 00Y.CO .TW
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WW .100Y.C M.TW
W
M
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t4
RXER,
setup
100Mbps
10O
W
M
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W
C
.
O
W
W
C
.
Y
W
W
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Y.C edge.TW
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to RXCLK
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00Y 6 M.TW
WW
M
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10Mbps
ns
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1
W
M
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W
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t5
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M
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after
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risingOedge
WW .100Y.C ns M.TW
WW .100Y
10Mbps
6
WW .100Y.C M.TW
M
Ohigh
WW 00Y.CnsO .TW
W
WW 00Y.CO .TW
C
t6
Receive
frame toYCRS
100Mbps
130
.
W
W
W
W
W
M
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1
00
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WW 00Yns
W.1 Y.COM W 10Mbps WW. 0Y.COM W
2000
W
W
W
T
.
W
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10
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End of receive
240 WW
OM
OM low 100Mbps WW.
W.1frame
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Y.C
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1
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WW .10ns
WW to sampled
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0
1
.
OM
WW 00Y.CO .TW
WW 00Y.CO .TW
C
.
W
RXDV WWW
W
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3200
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M
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OM 100Mbps
W
WW 00Y.CO .TW 120 WW ns
C
.
W
t9
End of receive
frame
to
sampled
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W
00
Y
W
W
00
M
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W.1 Y.COM W
M.T
O
W
edge of RXDV W.1
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W
C
.
10Mbps
ns 00
W 1000 W
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W
WW .100Y
WW .100Y.C M.T
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M.T
OM
W
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M.T
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WW .100Y.C M.TW
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW .100Y.C M.TW
W
.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
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Single-Chip/Port 10/100 Fast Ethernet
25
Track
Y
W
0
WW PHYceiver
0
W.1
OM
W.1
WW
WW .100Y.C M.TW
O
W
WW .100Y.C M.TW
O
W
WW .100Y.C
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M.T
RTL8201CL
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0
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.
0
Datasheet
OM
W.1
WW .100Y.C M.TW
W
.CO on.Tthe
W MII interface.
YMAC
Figure 8 shows an example of a packet
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1
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W
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W
Y.C
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WW .100Y.C M.TW
M
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RXCLK WWW
IH(min)
WW .100Y.C M.TW
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1
M
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W
M
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C
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V
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W
WW .100Y.
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M.T
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M
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M
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C
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.
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00
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W
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OM
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W.1 Y.COM W
W
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W
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W.1 Y.COM W
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W
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W
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W
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W
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W
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.CO ID: JATR-1076-21 Rev. 1.24
WW 00Y
.CO .TW
Single-Chip/Port 10/100 Fast Ethernet
26
Track
Y
W
0
WW PHYceiver
0
W.1
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W.1
WW
WW .100Y.C M.TW
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WW .100Y.C M.TW
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Table
Timing
OM
W.1 Cycle
W.1 Y.CO
C
.
W
W
Y
W
0
W
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Symbol W Description
Unit
10Minimum
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M
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W
C
W
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Y
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t
TXCLK
width
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W
0
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1
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W
W
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M.T
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OM
W
M.T
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C
W
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ns
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W
C
W
Y
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Y.
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M.T
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W.1 Y.COM 50 W
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W
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W
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an example ofWa.1packet.Ctransfer
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W
C
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W
WW .100Y.
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
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W
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WW .100Y.C M.TW
WW .100Y.C M.TW
O
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WW t 3.100Y.C M.TW
WW .100Y.C M.TW
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M
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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Single-Chip/Port 10/100 Fast Ethernet
27
Track ID: JATR-1076-21 Rev. 1.24
W
Y.C
WW .100Y
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10.

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