Hit or Miss
Block
11
16
21
13
64
48
19
11
10
22
11
12
27
13
14
11
15
Data at Address
Page 1
2) Like Problem 1, but now assume that the cache is direct-mapped, 4-word blocks, total 16
word capacity.
Address
Block Address
Hit or Miss
Block
11
16
21
Data at Block
13
64
48
19
11
3
22
4
27
6
11
Page 2
2-way SA H or M
Set
0
1
2
3
4
5
6
7
Data at Block
Address
2
3
11
16
21
13
64
48
19
11
3
22
4
27
6
11
FA H or M
Block
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Data at Block
Data at Block
Page 3
4) We are designing a new embedded processor with word addressing scheme (32-bit) used
for main memory and we are trying to decide what kind of L1 cache to include in our
existing memory hierarchy (the L2 and main memory have already been designed. We
indicate the miss rate for all accesses that enter a given level). Our layout team has given
us the three options shown below:
Level 1 Cache
Type
8KB Fully-Associative
16 KB 4-way SA
16KB Direct Mapped
Write Policy
Write-Back
Write-Through
Write-Back, FetchOn-Write-Miss
Block Size
128 Bytes
64 Bytes
32 Bytes
Miss Rate
10%
5%
8%
Access Time
1 clock cycle
1 clock cycle
1 clock cycle
Access Time
10 clock cycles
100 clock cycles
For each:
a) Draw a picture showing how many rows and columns the cache has. Indicate the width of
each field including data, tag, and any necessary valid or dirty bits.
b) Calculate the number of memory bits required to implement each cache.
c) Calculate the average memory access time for the whole system with each cache.
Page 4