Set No.

Code No: V3121/R07

III B.Tech I Semester Supplementary Examinations, May 2010

DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Design CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and
function table.
(b) Draw the resistive model of a CMOS inverter and explain its behavior for
LOW and HIGH outputs.
[8+8]
2. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to
TTL gate? Draw the interface circuit and explain the operation.
(b) Design a TTL three-state NAND gate and explain the operation with the help
of function table.
[8+8]
3. (a) Write a VHDL Entity and Architecture for the following function.
F (x) = (a + b) (c d)
Also draw the relevant logic diagram.
(b) Write a VHDL Entity and Architecture for a 3-bit ripple counter using FlipFlops?
[8+8]
4. (a) Write a process based VHDL program for the prime-number detector of 4-bit
input and explain the flow using logic circuit.
(b) Explain data-flow design elements of VHDL.

[10+6]

5. (a) Show the logic diagram of 74X283 binary adder. Explain the principle of
generating sum and carry at every stage using the logic diagram.
(b) Design a 24-bit group ripple adder using 74x283 ICs?

[8+8]

6. A simple floating-point encoder converts 16-bit fixed-point data using four high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program.
[16]
7. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit
counter in both modes and estimate the propagation delay.
(b) Design a modulo-88 counter using 74X163 Ics.

[8+8]

8. (a) Design an 8x4 diode ROM using 74X138 for the following data starting from
the first location.
1, 4, 9, B, A, 0, F, C
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Set No. 1

Code No: V3121/R07

(b) Draw the internal structure of synchronous SRAM and explain its operation?
[8+8]
?????

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Set No. 2

Code No: V3121/R07

III B.Tech I Semester Supplementary Examinations, May 2010

DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Explain how to estimate sinking current for low output and sourcing current
for high output of CMOS gate.
(b) Analyze the fall time of CMOS inverter output with RL = 100, VL = 2.5V and CL =
10P F . Assume VL as stable state voltage.
[8+8]
2. (a) Design a TTL three-state NAND gate and explain the operation with the help
of function table.
(b) Explain the following terms with reference to TTL gate.
i.
ii.
iii.
iv.

Voltage levels for logic 1 & logic 0

DC Noise margin
Low-state unit load
High-state fan-out

[8+8]

3. (a) Discuss the steps in VHDL design flow.

(b) Write a VHDL Entity and Architecture for the following function.
F(x) = (a+b)(c+d)(e+f)
Also draw the relevant logic diagram.

[8+8]

4. (a) Design a logic circuit to detect prime number of a 4-bit input? Write the
VHDL program for the above design?
(b) Design the logic circuit and write a data-flow style VHDL program for the
following function?
[8+8]
F (P ) = A,B,C,D (1, 5, 6, 7, 9, 13) + d (4, 15)
5. (a) Draw the digits created by 74x49 seven-segment decoder for non-decimal inputs 1010 through 1111.
(b) Realize the following expression using 74151 IC

[8+8]

f (X) = ABC + ABC + ABC

6. A simple floating-point encoder converts 16-bit fixed-point data using four high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program.
[16]

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Set No. 2

Code No: V3121/R07

7. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit
counter in both modes and estimate the propagation delay.
(b) Design a modulo-88 counter using 74X163 Ics.

[8+8]

8. (a) Explain the internal structure of 64K1 DRAM. With the help of timing
waveforms discuss DRAM access.
(b) Design an 84 diode ROM using 74138 for the following data starting from
the first location.
[8+8]
F, 2, 9, C, E, 1, F, A
?????

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Set No. 3

Code No: V3121/R07

III B.Tech I Semester Supplementary Examinations, May 2010

DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Design a 4-input CMOS OR-AND-INVERT gate. Explain the circuit with the
help of logic diagram and function table?
(b) Explain the following terms with reference to CMOS logic.
i.
ii.
iii.
iv.

Logic 0 and Logic 1

Noise margin
Power supply rails
Propagation delay

[10+6]

2. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three
parts with the help of functional operation.
(b) List out TTL families and compare them with reference to propagation delay,
power consumption, speed-power product and low level input current. [8+8]
3. (a) Write a VHDL Entity and Architecture for the following function?
F(x) = a b c
Also draw the relevant logic diagram.
(b) Explain the use of Packages Give the syntax and structure of a package in
VHDL
[8+8]
4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural
VHDL program for the same.
[16]
5. (a) Design a full subtractor with logic gates and write VHDL data flow program
for the implementation of the above subtractor.
(b) Using the above subtractor design a 8-bit ripple subtractor and write the
corresponding VHDL program in structural style of modeling.
[8+8]
6. (a) Design a barrel shifter for 8-bit using three control inputs? Write a VHDL
program for the same in data flow style.
(b) Write a behavioral VHDL program to compare 16-bit signed and unsigned
integers
[8+8]
7. (a) Design a switch debouncer circuit using 74109 IC. Explain the operation
using timing diagram.
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Set No. 3

Code No: V3121/R07

(b) Discuss the logic circuit of 74377 register. Write a VHDL program for the
same in structural style.
[8+8]
8. (a) With the help of timing waveforms, explain read and write operations of
SRAM.
(b) Explain the internal structure of 64K1 DRAM. With the help of timing
waveforms discuss DRAM access.
[8+8]
?????

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Set No. 4

Code No: V3121/R07

III B.Tech I Semester Supplementary Examinations, May 2010

DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Design a CMOS transistor circuit that has the functional behavior as
f (x) = (a + c). (b + c)
Also draw the relevant circuit diagram
(b) Design CMOS 4-input OR-AND-INVERT gate. Explain the circuit with the
help of logic diagram and function table?
[10+6]
2. (a) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation
with the help of function table.
(b) Compare CMOS, TTL and ECL with reference to logic levels, DC Noise margin, propagation delay and fan-out.
[8+8]
3. (a) What is importance of Entity and Architecture in VHDL? Explain with suitable examples.
(b) What are the different data objects supported by VHDL? Explain scalar types
with suitable examples.
[8+8]
4. (a) Explain data-flow design elements of VHDL.
(b) Design the logic circuit and write a data-flow style VHDL program for the
following function.
[8+8]
F (X) = A,B,C,D (1, 4, 5, 7, 12, 14, 15) + d (3, 11)
5. Explain the principle of carry look ahead Adder. Using this principle design a 6-bit
carry look ahead adder. Provide the logic diagram. Write the data flow VHDL
program for the same.
[16]
6. A simple floating-point encoder converts 16-bit fixed-point data using four high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program.
[16]
7. (a) Design an Excess-3 decimal counter using 74163 and explain the operation
with help of timing waveforms.
(b) It is necessary to generate 6 control lines in regular intervals sequentially.
Design the necessary circuit using 74163 and 74138.
[8+8]

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Set No. 4

Code No: V3121/R07

8. (a) Discuss how PROM, EPROM and EEPROM technologies differ from each
other.
(b) With the help of timing waveforms, explain read and write operations of
SRAM.
[8+8]
?????

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