SoC Embedded NS Embedded Systems 3 Jan 2014

Embedded (HW) SystemsPerformance Evaluation of
Communication
Vineet Sahula
sahula@ieee.org
Outline
Introduction
System-on-a-Chip (SoC)
Who enables Chip design
Electronic Design automation (EDA)
High level, Logic, Layout synthesis
FPGA based synthesis
ES/SoC Communication Modeling

Performance Evaluation techniques
Embedded SystemsPerformance Evaluation
NSRTES-2014 @ Balaji College
Generic SoC
Implementation
Computation
PEs
Communication
Bus based architecture
NoC architecture
?
Embedded Systems- Performance Evaluation
Generic SoC
Processor
Memory
No. of PEs
PE are verified, validated
CPU, DSP , IP , ASIC
Set-top-box, MPEG-2 decoder
Logic
Analog
PE are heterogeneous
Optimized HW/SW
Separable computation & communication
Diverse communication
Communication becomes critical
System Modeling
Models of Computation
Continuous Time Models
SIMULINK, VHDL-AMS
Discrete Timed Models

HDLs etc.
Synchronous Models
Untimed Models
Data Flow Process Networks
Synchronous Data Flow, Kahn Process
Networks
Rendezvous based
CSP, CCS, CRP
Chip Design: Who Enables?

Design Technology
Idea
Integrated circuit (Chip) design
Applications technologies
Wireless/Telecommunication
Computing
Internet
Consumer/medical electronics
Design
Fabrication
Enabling technologies
Fabrication
Software Engineering
Computer architecture
Internet
Packaging
Design Technology
Systems characteristics
Billion/Trillion transistors
Heterogeneous, portable, low power, low cost
Desired
Circa 2004, A single hand-held portable system which is
Computing, GPS enabled, multimedia/voice/data comm.,
wireless internet
Circa 2020, Similar system which is hands free, preferably

wearable and controlled by thoughts
VLSI Design
Synthesis based methodology
Synthesize & validate
VLSI Design
Methodology
Supported by CAD
Human expertise
centric
Increasing mismatch of
Synthesis models and
implemented circuit
First time correct
designs are rare/nearly
impossible
Idea
System specification
Architecture Synthesis
Components/gate synthesis
Chip Layout synthesis
Fabrication 1010 Tr.

Electronic Design Automation (EDA)

System specification
Synthesis
CAD tools
CAD tool writing

Fabrication
technology
dependent
Architecture Synthesis
Components/gate synthesis
Dream
Mature &
evolving
Fabrication
Mature &
Acceptable
Chip Layout synthesis

Achievable But Difficult To
adapt to Changes in
technology
9
Electronic Design Automation

Design automation using E-CAD
What ?
Specification
Automating the design process
How ?
Design Step 1
Design description
Abstraction, models
Simulation
BackSynthesis
annotation
Verification/simulation
Transformation between various
representations
Synthesis
Extraction/back-annotation
Design Step 2
Simulation
Chip layout
10
E-CAD
Why ?
Design size too large

Systems too complex
Huge design efforts
Problem definition dynamically changing
CAD is indispensable
11
Performance Evaluation
Models for System-on-Chip
Communication
Outline
Communication Architectures (CA)
Performance estimation
Statistical estimation
Analytical estimation
Proposal for performance evaluation

models
HCFG based approach
13
Communication architecture
CA is fabric to exchange
data & control signals.
It consist of
1.Logic components
2.Global bus lines.
3.Bus interfaces.
14
Bus based
Single shared bus.
Hierarchical buses
connected by
bridges.
15
Networks on Chip
Packets routed
via channels and
switches.
16
NoC Topologies
SPIN
Scalable Programmable
Integrated Network
CLICH.
Chip Level Integration of
communication
Heterogeneous Elements
17
Commercial Bus Architecture

IBM Core-Connect
ARM AMBA
Palmchip
CoreFrame
18
Performance Estimation
Statistical analysis
- CAG model
- Queueing theory
- Stochastic framework
Trace driven simulation
- System level tools (PTOLEMY)
Hybrid combination of both
19
Efficiency of Modeling Approaches

Models
Classification
FSM, Timed-Petri-nets, Markov chains,

Simulation
Kahn process networks ,Transaction Level
models
models, OSM
Synchronization graph, CAG, Queuing
model
Analytical
models
20
Significance of interface synthesis
Abstract Communication
Lahiri,2004
21
Alternate Comm. Architecture - A

Single Shared Bus is
used to map all
components.
Single Shared Bus

22
Alternate Comm. Architecture - B

C1,C2 & M1 are
mapped to Bus1
C3,C4 & M2 are
mapped to Bus2
Multiple Buses Case 1
23
Alternate mapping ( Arch-B) - C

C1,C3 & M1 are
mapped to Bus1.
C2,C4 & M2 are
mapped to Bus2.
Multiple Buses Case 2

24
Queueing model
Kim,IEEE
CAD,2005 [2]
25
Markov Model
26
Hierarchical bus modeling

Individual bus
Markovian process
Bus state
Past bus state
Past bridge state
Bridge state
Past buses states
27
Hierarchical bus modeling
S1
S2
Pi1
SG
28
Introduction
HCFG: An Overview
HCFG approach for evaluating GSMP model of SSB architecture
Results
Conclusions
Evaluating Generalized Semi Markov Process

Model of SoC Bus Architectures using HCFG
Ulhas Deshmukh1
1 Govt.
Vineet Sahula2
Polytechnic College, Dhule, India
2 Department of ECE
Malaviya National Institute of Technology, Jaipur, India
TENCON 2009, Singapore 23-26 November 2009
Ulhas Deshmukh, Vineet Sahula
GSMP model evaluation using HCFG
Introduction
HCFG: An Overview
Results
Conclusions
Outline
1
Introduction
Motivation
Previous work and Proposed work
HCFG: An Overview

SSB architecture
GSMP Model formulation
Model evaluation using HCFG approach
HBB architecture
GSMP model formulation

Results
Conclusions
Introduction
HCFG: An Overview
Results
Conclusions
Motivation
Outline
1
Introduction
Motivation
HCFG: An Overview

SSB architecture
HBB architecture

Results
Conclusions
Introduction
HCFG: An Overview
Results
Conclusions
Motivation
System level SoC architecture
SW
SW IP 1
SW Adaption
CPU
HW Adaption
HW IP 1
HW IP 2
HW Adaption
HW Adaption
On Chip Communication
HW Adaption
CPU
SW Adaption
SW
SW IP 2
SoC performs computation

and communication of
system functionality
System computationMapped to PEs/IPs
Pre-verified & optimized
Communication
architecture facilitates
communication among IPs
Introduction
HCFG: An Overview
Results
Conclusions
Motivation
Issue
Modern-day systems demand for higher performance and
more functions
Designer has to use a number of concurrent and
heterogeneous IPs
Communication among these IPs becomes intricate
Quick performance evaluation of communication
architecture is essential
Introduction
HCFG: An Overview
Results
Conclusions
Motivation
Outline
1
Introduction
Motivation
HCFG: An Overview

SSB architecture
HBB architecture

Results
Conclusions
Introduction
HCFG: An Overview
Results
Conclusions
Motivation
Related work & proposed approach

Classification
Analytical
Authors
P.Knudsen et al.[1]
S.Dey et al. [2]
T.Mudge et al. [3]
A.Ramani et al. [4]
Proposed work
Simulation
J.Rowson et al. [5]

X.Zhu et al. [6]
K.Lahiri et al.[7]
S.Kim et al.[8]
Hybrid
Approach
Delay estimation model
Synchronization graph
SMP model (multi-bus arch.)
SMP model (crossbar arch.)
GSMP model evaluation
using HCFG
Simulator (Cheetah)
Operating State Machine
Simulation + CAG
Queueing analysis + simulation
Introduction
HCFG: An Overview
Results
Conclusions
Hierarchical Concurrent Flow Graph (HCFG)

HCFG approach [9] [10]
An efficient analysis technique
Captures concurrency, hierarchy
Handles stochastic variation in task execution times
Quickly compute average values & distribution
Has been used for evaluation and improvement of process
completion time of VLSI design processes [9] [10]
[9] V.Sahula,C.P.Ravikumar,D. Nagchoudhuri,ASP-DAC 2002
[10] V.Sahula and C. P. Ravikumar, VLSI Design,2001
Introduction
HCFG: An Overview
Results
Conclusions
Communication concurrency in HCFG

TBCOMM
BCOMM
PE 1
PE2
PEN
PE 1
PE2
PEN
I/F
I/F
I/F
I/F
I/F
I/F
bridge
comm
B2COMM
Bus I/f
Bridge
Bus I/f
B1COMM
BUS1
I/F
I/F
MEM 1
Arbiter
Bus2
comm
Bus1
comm
BUS 2
I/F
I/F
MEM 2
Arbiter
Bridge
comm
Fork
TB2COMM
TB1COMM
Join
TBCOMM
BCOMM
AND concurrency
Communications over buses are concurrent
Communication across the bridge begins only when both
buses are free
E[TC ] = E[TB1B2COMM ]+E[Max{TB1 , TB2 }]+E[TB2B1COMM ]
Introduction
HCFG: An Overview
Results
Conclusions
Communication concurrency in HCFG

T
T
Source PE
P1
Path 1
P2
Path 2
P3
TP
Path 3
Dest. PE
Ttile, SSource, Ddestination
OR concurrency
Multiple communications path can be active
E[TC ] = E[Min{TP1 , TP2 , TP3 }]
TP
TP
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Outline
1
Introduction
Motivation
HCFG: An Overview

SSB architecture
HBB architecture

Results
Conclusions
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
SSB architecture
PE 1
PE2
PEN
I/F
I/F
I/F
BUS
I/F
MEM
I/F
Arbiter
Model formulation
Homogeneous Processing
Elements (PEs)
Model of a single PE
suffices
Actions of a PE are-
Computing
Accessing the MEM
Waiting for memory
For full accessing

time of any other
PE/PEs
For part of accessing
time of any other PE
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Model formulation
PE 1
PE 2
I/F
I/F
PE N
I/F
Computing action
The PE1 is computing
No request is generated
BUS
Modeled as computing state

(labeled as state 0)
I/F
I/F
MEM
Arbiter
Mean sojourn time is 0 = T
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Model formulation cont.
PE1
PE 2
PE N
I/F
I/F
I/F
Accessing action
PE1 generates a request
Bus and memory are idle

((1 BUSY )2)
Request wins arbitration (WIN)
BUS
PE1 accesses the memory

I/F
I/F
MEM
Arbiter
Modeled as accessing state

Mean sojourn time is 1 = C
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture

PE 1
PE 2
I/F
I/F
PE N Full
I/F
PE1 & PEk generate request

Bus and memory are idle
PE1 does not win arbitration
BUS
I/F
waiting action
PE1
FW
PEk
MEM
PCOMP, CCOMM
FWFull Waiting
PEk gets access to memory
PE1 has to wait for full accessing

time of PEk
Modeled as full waiting state
Mean sojourn time is C
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Residual waiting state

PE 1
PE 2
PE N
I/F
I/F
I/F
PEk is accessing memory

i.e. memory is busy
PE1 generates a request
BUS
RW
P
I/F
MEM
PE1
PEk
PCOMP, CCOMM
RWResidual Waiting
PE1 force to wait for

residual accessing time of
PEk
Modeled as residual
waiting state (labeled as
state 3)
Mean sojourn time is
(C 2 C)/(2(C 1)
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Model input parameters for i th PE

Parameters
N
Ti
Ci
Ci2
Description
number of processing elements
mean computing time
mean communication time
second moment of communication time
Terms used in model formulation

BUSY
WIN
k
probability that memory or bus busy

probability of wining arbitration
mean sojourn time of k th state
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
GSMP model of a PE in SSB
1
0
States of a PE
State 0-computing state
State 1-accessing state
State 2-full waiting state
State 3-residual waiting
state
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
HCFG based evaluation approach

Transformation of GSMP model to HCFG
Add extra node S for initial task
Draw directed edge (S, x), x is state of GSMP
x should have zero in-degree (minimum), p Sx = 1
Map j s of GSMP model to the Tj s of HCFG node,

j = 0, 1, 2, 3, Ts = 0
Map pij of GSMP model, to the weight pij of an edge (i, j) of

HCFG
Consider one state at a time as a final (F) state
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
HCFG based evaluation approach cont.

HCFG of a PE in SSB for N=2
p Z2
p Z2
31
22
p Z1
s3
ps3= 1.0
p32= 0.61
p 31= 0.39
p21= 0.39
p22= 0.61
p10= 1.0
p Z2
p Z2
32
p Z1
p Z2
03
p Z2
02
p01= 0.39
p02= 0.18
p03= 0.43
1
F
21
TS = 0
01
p Z1
10
T0 = 1
T1 = 2
T2 = 2
T3 = 1
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Computation of steady state probabilities

Describe HCFG in DFLOW tool
Execute DFLOW description to find steady state probability
of being in state F
Repeat for all other states and for varing number of PEs
Performance parameters are computed as follows:
BW
PU
N P1
P 0 + P1
N (P2 + P3 )
2 2 + 3 3
1
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Outline
1
Introduction
Motivation
HCFG: An Overview

SSB architecture
HBB architecture

Results
Conclusions
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
HBB architecture
PE2
PEN
PE 1
PE2
PEN
I/F
I/F
I/F
I/F
I/F
I/F
Bus I/f
Bridge
Bus I/f
PE 1
BUS1
I/F
I/F
MEM 1
Arbiter
BUS 2
I/F
I/F
MEM 2
Arbiter
Concurrent communication on BUS1 & BUS2

Each PE can access MEM1 & MEM2
Consider PE1 mapped to BUS1
MEM1 -local memory, MEM2 -global memory

Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
GSMP Model of a PE in HBB
1
2
1
1
1
6
6
State 1 through state 3

local MEM1
0
5
5
4
4
States of a PE
State 0 computing state
State 4 through state 6

global MEM2
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Model input parameters

N = number of Processing Elements (PEs)
T = Mean value of of think time
X ` = Probability of local request
X g = Probability of global request
C ` = Mean value of of local connection time
C g = Mean value of of global connection time
Cl2 /Cg2 = Second moment of local/global communication
time
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Model evaluation- HCFG approach

HCFG of a PE in HBB for X` =0.1.
p Z2
22
p Z2
32
p Z2
31
p Z2
04
p Z2
TS = 0
T0 = 1
02
03
T1 = 2
T2 = 2
T3 = 1
T4 = 2
p Z1
s0
p Z
T5 = 2
T6 = 1
01
p Z2
p Z1
06
10
65
p02 = 0.057
p31 = 0.27
p03 = 0.01
p04 = 0.16
05
p05 = 0.57
p Z1
p Z2
40
p Z2
p06 = 0.19
p32 = 0.73
04
p Z2
p22 = 0.73
p01 = 0.027
p Z1
pS0= 1.0
p Z2
54
p Z2
55
p21 = 0.27
p10 = 1.0
p65 = 0.82
p64 = 0.18
p54 = 0.18
p55 = 0.82
p40 = 1.0
p Z2
64
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Performance metrics of HBB architecture

Performance metrics
BW`
BWg
L`
Lg
W`
Wg
N P1
N P4
= N (P2 + P3 )
= N (P5 + P6 )
= 2 (2 + 3 1 )/1 + 3 3
= 5 (5 + 6 4 )/4 + 6 6
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
Validation of evaluation approach using HCFG
Validation against SystemC simulation
SystemC test bench

SystemC IP for AMBA bus
Configurable traffic generators in place of PEs
Communication time
Computation time
Probability of local request
Probability of global request
Validation against evaluation using AFOME [11] approach
Introduction
HCFG: An Overview
Results
Conclusions
SSB architecture
HBB architecture
SystemC simulation setup for HBB architecture

//bus1.cc
//BR1.cc
SC_MODULE(BR1)
{
//ports
sc_out<int> req_BR1;
sc_out<int>data_BR1;
sc_in_clk clock;
//other ports
void BR1_action()
{ while(true)
{ if(BR1_grant.read()==1)
}
//rest of the code;

}
}
}
}
SC_CTOR(bus2)
}
{
};
SC_CTOR(PE12)
{
};
//rest of the code;
}
//rest of the code;
}
}
}
SC_CTOR(bus2)
}
{
SC_CTOR(BR1)
{
SC_THREAD(BR1_action);
sensitive<< clock;
}
};
};
SC_CTOR(bus2)
{
};
PE 2
PE 1
I/F
I/F
MEM 1
PE 2
PE 1
I/F
I/F
BUS 1
//arbiter1.cc
Bus I/f
Bridge
Bus I/f
//PE11.cc
SC_MODULE(bus2)
//PE12.cc
{
SC_MODULE(PE12)
sc_in<int>data_PE1;
{
sc_in<int>data_BR12;
sc_inout<int>data_PE12;
//some other
ports
sc_out<int>req_PE12;
void bus2_action()
//some other ports
{ while(true)
void PE12_action()
{ if(PE_grant.read()==1)
{ while(true)
{
status_bus2.write(true);
{ if(PE12_grant.read()==1)
//rest of the code not shown;
{
}
SC_MODULE(bus2)
//bus2.cc
{
SC_MODULE(bus2)
sc_in<int>data_PE1;
{
sc_in<int>data_PE1;
//some other
ports
void bus2_action()
//some other ports
{ while(true)
void bus2_action()
{ while(true)
{
//rest of the code not shown;
{
}
I/F
Arbiter1
I/F
BUS 1
I/F
MEM 1
I/F
Arbiter1
SC_MODULE(arbiter2)
//arbiter2.cc
{
SC_MODULE(arbiter2)
sc_in<bool>bus2_status;
{
sc_in<int>req_PE1;
sc_in<bool>bus2_status;
//some ports
sc_in<int>req_PE1;
void arbiter2_action()
//some ports
{
void arbiter2_action()
while(true)
{ {
//restwhile(true)
of the code not shown
{
}
//rest of the code not shown
}
}
SC_CTOR(arbiter2)
}
{
SC_CTOR(arbiter2)
SC_THREAD(arbiter2_action);
{
}
SC_THREAD(arbiter2_action);
};
}
};
Introduction
HCFG: An Overview
Results
Conclusions
Results- SSB architecture
Model Input Parameters - C=2 Cycles, T =2 Cycles, C v =0.

1
Processor Utilization (PU)
Bandwidth
0.8
0.6
0.4
Simulation Approach
AFOME Approach
0.2
0
1
HCFG Approach
2
Number of PEs
0.8
Simulation Approach
AFOME Approach
0.6
HCFG Approach
PU for T=2,r=0.1
0.4
0.2
0
1
3
4
5
6
Number of PEs (N)
Introduction
HCFG: An Overview
Results
Conclusions
Results- HBB architecture

Model Input Parameters - N=2, T =2 Cycles, C ` =C g =2 Cycles,
Cv =0.
0.8
0.6
4.0
Simulation Approach
AFOME Approach
HCFG Approach
3.5
Local waiting time
Local bandwidth
0.4
0.2
0
3.0
2.5
2.0
1.5
1.0
0.5
0.2
0.4
0.6
0.8
Simulation Approach
AFOME Approach
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Introduction
HCFG: An Overview
Results
Conclusions
Results- HBB architecture

Model Input Parameters - N=2, T =2 Cycles, C ` =C g =2 Cycles,
Cv =0.
0.3
2.0
Simulation Approach
AFOME Approach
HCFG Approach
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Gloal queue length
Global bandwidth
0.4
1.5
Simulation Appro.
AFOME Approach
HCFG Approach
1.0
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Introduction
HCFG: An Overview
Results
Conclusions
Conclusions
Proposed analytical approach is time efficient, accurate
Besides, it gives stochastic properties quickly as that of
simulation
Introduction
HCFG: An Overview
Results
Conclusions
Bibliography
1
P. Knudsen and J. Madsen, Integrating communication protocol selection with partitioning in

hardware/software codesign in Proc. Int.Symp. Syst. Level Synthesis,1999,111-116.
S. Dey and S. Bommu, Performance analysis of a system of communicating processes, in ICCAD, 1997,
590-597.
T.N.Mudge and H.B.A.Sadoun, A Semi Markov Model for Performance of Multiple-Bus Systems, IEEE
Trans. On Computers, Vol C-34, No 10, Oct 1985.
A.K.Ramani, P.K.Chande and P.C.Sharma, A general model for performance investigations of priority
based multiprocessor system, IEEE Trans. on Computers, 1992, 747-754
J. A. Rowson and A. Sangiovanni-Vincentelli, Interface based design, Proc. Design Automation Conf.,
1997, 178-183.
X. Zhu, W. Qin, and S. Malik, Modeling operation and microarchitecture concurrency for communication
architectures with application to retargetable simulation, IEEE Trans. VLSI Syst., 14(7):707-716, July 2006.
K.Lahiri, A. Raghunathan and S. Dey, System-level performance analysis for designing on-chip
communication architecture, IEEE Tran. CAD, 20(6):768-783, June 2001.
S. Kim, C.Im and S. Ha, Schedule-Aware Performance Estimation of Communication Architecture for
Efficient Design Space Exploration, IEEE Trans. VLSI System Vol 13, No 5, Pages 539-552, may 2005.
V.Sahula, C. P. Ravikumar and D. Nagchoudhuri. Improvement of ASIC Design Processes. ASP-DAC,

2002, pages 105-112.
10 V.Sahula and C. P. Ravikumar, The hierarchical concurrent flow graph approach for modeling and analysis
of design processes, in Int. Conf. VLSI Design,2001,91-96.
11 U.Deshmukh and V. Sahula, Analytical performance estimation from GSMP model for hierarchical bus
bridge based SoC communication architecture, in Proceedings of 20th IEEE International Conference on
Microelectronics (ICM), Dec. 2008.
Introduction
HCFG: An Overview
Results
Conclusions
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Embedded (HW) SystemsPerformance Evaluation of

ES/SoC Communication Modeling

Embedded SystemsPerformance Evaluation

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

NSRTES-2014 @ Balaji College

Discrete Timed Models

NSRTES-2014 @ Balaji College

Chip Design: Who Enables?

Integrated circuit (Chip) design

Embedded SystemsPerformance Evaluation

NSRTES-2014 @ Balaji College

Circa 2020, Similar system which is hands free, preferably

NSRTES-2014 @ Balaji College

Chip Layout synthesis

Fabrication 1010 Tr.

Electronic Design Automation (EDA)

CAD tool writing

NSRTES-2014 @ Balaji College

Embedded SystemsPerformance Evaluation

Chip Layout synthesis

Electronic Design Automation

NSRTES-2014 @ Balaji College

Design size too large

NSRTES-2014 @ Balaji College

Proposal for performance evaluation

Embedded SystemsPerformance Evaluation

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Commercial Bus Architecture

Embedded SystemsPerformance Evaluation

NSRTES-2014 @ Balaji College

NSRTES-2014 @ Balaji College

Efficiency of Modeling Approaches

FSM, Timed-Petri-nets, Markov chains,

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Significance of interface synthesis

NSRTES-2014 @ Balaji College

Alternate Comm. Architecture - A

Single Shared Bus

NSRTES-2014 @ Balaji College

Alternate Comm. Architecture - B

Multiple Buses Case 1

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Alternate mapping ( Arch-B) - C

Multiple Buses Case 2

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Embedded Systems- Performance Evaluation

NSRTES-2014 @ Balaji College

Hierarchical bus modeling

Embedded SystemsPerformance Evaluation

NSRTES-2014 @ Balaji College

Hierarchical bus modeling