(USIC)
JVD COLLEGE OF SCIENCE AND TECHNOLOGY,
ANDHRA UNIVERSITY
DETAILED SYLLABUS
Semester 1
Semester 2
Symmetric and Anti symmetric FIR filters Linear phase FIR filters Design using
Frequency sampling technique Window design using Hamming, Hanning and
Blackmann Windows Concept of optimum equiripple approximation Realization
of FIR filters Transversal, Linear phase and Polyphase realization structures.
4. FINITE WORD LENGTH EFFECTS :
Quantization noise derivation for quantization noise power Fixed point and binary
floating point number representations Comparison Overflow error truncation
error coefficient quantization error limit cycle oscillations- signal scaling
analytical model of sample and hold operations.
5. SPECIAL TOPICS IN DSP:
Basic code structure of VHDL - Lexical elements of VHDL - Data objects - Data
types - Operators Attributes - Identifiers
3. BEHAVIORAL DESCRIPTION:
Concurrent Statements
5. MODELING COMBINATIONAL LOGIC CIRCUITS USING VHDL PACKAGE:
Design function using Verilog - Levels of synthesizing Verilog - Designing N/W using
Verilog - Simple design - wires - wire assignments
8. Test -Benches - Response capture - RTL Verilog, If - statement synthesis
Text Books
1. Ashenden The Designers Guide to VHDL Tata McGraw Hill Publications, 2nd
Edition.
2. Mohammed Ismail Analog VLSI Integrated Circuits, Prentice Hall of India.
3. Grey, Hurst Luwis, Mayer, Analysis and Design of Analog Integrated Circuits
John Willey Sons.
Network elements, Transient and sinusoidal steady state analysis using Laplace
Transformation, Network functions, Two port networks: Parameters and transfer
function, Interconnection of two ports.
2. Methods for Computer Aided Network Analysis
State Variable Method, Analytic & numerical solutions, Graph theoretic analysis for
large scale networks, Formulation and solution of network graph of simple networks,
State space representation, Analysis using PSPICE.
3. Elements of Network Synthesis
Controlled sources, Op-amp as a controlled sourse, Sallen & Key structure, Single
amplifier LP, HP, BP & BR Filters, Principle of design, Sensitivity.
Text Books:
Adders
Half- Adder
Full Adder
CLA
4. Multiplexer
4:1 Multiplexer
8:1 Multiplexer
5.
Decoder
6.
Encoder
7. ALU
8. Counters
4 bit binary up down counter
Mod N counter
Counter with Parallel Load and clear facility
9. Shift Registers
Serial in Serial Out
Serial in Parallel Out
Parallel in Serial Out
Parallel in Parallel Out
10. Mealy & Moore machines
11. RAM & ROM
12. Sequence detector
Semester 3
of Inequalities Retiming
3.UNFOLDING :
Introduction An algorithm for unfolding properties of unfolding Critical path, unfolding
and retiming- Application of unfolding.
4.SYSTOLIC ARCHITECTURE DESIGN:
Introduction - systolic Array Design Methodology FIR systolic Arrays- Selection of
scheduling vector- Matrix Multiplication and 2 D systolic array Design Systolic design for
space representations containing Delays.
5.FAST CONVOLUTION:
Introduction- Cook Toom algorithm- Winogard algorithm Iterated convolution cyclic
Convolution Design of fast convolution Algorithm by Instpection.
6.SCALING AND ROUNDOFF NOISE
Introduction Scaling and Round off noise- State variable Description of digital filtersScaling and Round off noise computation - Roundoff Noise in Piplined HR filter- Roundoff
Noise Computation Using State varianle description Slow down, retiming, and pipelining
REFERENCES:
Keshab.K. Parhi, VLSI Digital signal processing systems- Design and Implementations
wiley- Inter science, 1999.
Mohammed Ismail, Terri, Fiez, Analog VLSI signal and Information Processing, 1994
McGraw Hill.
Keshab K.Parhi, VLSI Digital signal processing systems Design. And Implementation
Wiley- Inter science, 1999.
Kung.S.Y. H.J. While house, T.Kailath, VLSI and Modern signal processing, Prentice hall,
1985.
Jose E. France, Yannis Tsividis Design of Analog- Digital VLSI circuits for
Telecommunications and signal processing- Prentice Hall, 1994.
Semester 4
Semester 5
Semester 6