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Table of Contents
Topic Name
Slide No.
Logical Operations
5-8
9 - 10
11
Principle of Duality
12
13 - 18
19
20 29
30 - 46
47 - 57
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Logical Operations :
Logical Function or Compound Statement
Logical Operators
Evaluation of Boolean Expression Using Truth Table
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Truth Table :
Truth Table is a table which represents all the possible values of logical variables/ statements along
with all the possible results of the given combinations of values.
For example, we have two logical variable x and y which can have either TRUE or False values.
Following is the all the possible combination of values these variable can have in tabular form :
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Truth Table :
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OR Operator :
Denotes operation called logical
addition.
+ symbol is used.
X + Y can be read as X OR Y.
Rules : 0 + 0 = 0
0+1=1
1+0=1
1+1=1
In Venn diagram shaded area
represents X + Y
AND Operator :
Denotes operation called
logical multiplication.
. symbol is used.
X . Y can be read as X AND Y.
Rules : 0 . 0 = 0
0.1=0
1.0=0
1.1=1
In Venn diagram shaded area
represents (X . Y).
Truth Table :
Truth Table :
X+Y
X+Y
X YZ
Y.Z
YZ
NOTE : While evaluating Boolean expression we always have to taken care of precedence. The order of evaluation of
logical operator is firstly NOT then AND and then OR. If there are parenthesis, then the expression in parenthesis is
evaluated first.
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F=X.Y
Symbol :
F=X.Y.Z
3. AND Gate :
The AND Gate can have two or more than two input and produce an output signal.
If any of the input signal is 0, the output signal is 0.
Symbol :
If all inputs are 0 then output is also 0.
Truth Table :
F=X.Y
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F=X.Y.Z
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11
Principle of Duality :
The principle of duality states that starting with a Boolean relation, another Boolean relation
can be derived by :
1 Changing each OR sign(+) to an AND sign(.).
2. Changing each AND sign(.) to an OR sign(+).
3. Replacing each 0 by 1 and each 1 by 0.
The derived relation using duality principle is called dual of original expression.
For example postulate II states
(a) 0 + 0 = 0 (b) 0 + 1 = 1 (c) 1 + 0 = 1 (d) 1 + 1 = 1
Now according to principle of duality we changed + to . and 0 to 1.
These become,
(i) 1 . 1 = 1 (ii) 1 . 0 = 0 (iii) 0 . 1 = 0 (iv) 0 . 0 = 0
which is same as postulate III.
So i, ii, iii, iv are duals of a, b, c, d.
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1.
2.
3.
4.
5.
6.
7.
8.
9.
Basic postulates of Boolean algebra are used to define basic theorems of Boolean algebra.
Provide all the tools necessary for manipulating Boolean expression.
Properties of 0 and 1
Indempotence Law
Involution
Complementarity Law
Commutative Law
Associative Law
Distributive law
Absorption Law
Some Other Rules of Boolean Algebra
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13
Truth Table
From Truth Table
w can see
that all four properties are
proved.
In (b) both the values (0 and 1)
ORed with 1 produce the output
as 1. So 1 + X = 1 is a tautology.
In (c) both the values (0 and 1)
ANDed with 0 produce the
output as 0. So 0 . X=0 is a
fallacy.
Here
we can observe that propertied b and c are duals of each other and properties a and d are
duals of each other.
2. Indempotence Law
Truth Table
Here, It is proved that (a) and (b) are duals of each other.
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Truth Table
)
X
(
4. Complementarity Law
Truth Table
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Truth Table
6 Associative Law
Truth Table
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Truth Table
8. Absorption Law
Truth Table
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Proof .
L.H.S. = X + X Y
= X . 1 + XY
= X(1 + Y) + X Y
= X + XY + X Y
= X + Y ( X X)
=X+Y.1
=X+Y
= R.H.S. Hence proved.
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(X . 1 = X property of 0 and 1 )
(1 + Y = 1 property of 0 and 1 )
( X + X = 1 complimentarily low)
(Y . 1 = Y property of 0 and 1)
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Demorgans Theorems :
A mathematician named Demorgan developed a pair of important rules which is the most
powerful identities used in Boolean algebra.
Demorgans First Theorem
It states that X Y X Y
Truth Table
X Y XY
Truth Table
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=4+0+0=4
3. Express as decimal subscript of m = m4
Thus
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X Y Z = m4
21
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( XY X Y )( Z Z ) X Y Z X Y Z
Z ( XY X Y ) Z ( XY X Y ) X Y Z X Y Z
XYZ X Y Z XY Z X Y Z X Y Z X Y Z
Continued
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XY Z XYZ XY Z XYZ
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Continued
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( Z .Z Z asX . X X )
X Y Y .Z (1 Y )
(1 Y 1)
X Y Y Z .1
XY Y Z
Rule 2. To convert into product of sums form, apply the Boolean algebra rule which states that
X + YZ = (X+Y)(X+Z)
Now applying this rule we get,
X Y Y Z ( X Y Y )( X Y Z )
(Y X Z )( Z X Y )
(Y X )(Y Y )( Z X )( Z Y )
( X Y )(Y )( X Z )(Y Z )
( X Y Y X )
Rule 3. After converting into product of sum terms, in a sum term for a missing variable add ( Y Y Y )
(missing variable . missing variable) such as, if variable Y is missing add Y Y .
i.e.,
Terms:
(X Y)(Y)(X Z)(Y Z)
1 2
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Continued
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X= 0, Y = 0, Z = 0
And Maxterm will be ( X + Y + Z )
(Complement the variable if input is 1 otherwise not)
Similarly, M1 means 0 0 1 X + Y + Z
As F = M0 . M1 . M4 . M5 . M7
X Y Z
X Y Z
\and
M0 = 0 0 0 X + Y + Z
M4 = 1 0 0
M7 = 1 1 1
M1 = 0 0 1 X Y Z
M5 = 1 0 1 X Y Z
F= ( X Y Z )( X Y Z )( X Y Z )( X Y Z )( X Y Z )
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Maxterm
Minterm
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( D D 1)
AC ( B B) AC.1 AC
( B B 1)
Example 2: Reduce X Y Z X Y Z X Y Z XY Z .
Solution : X Y Z X Y Z X Y Z XY Z X (Y Z Y Z ) X (Y Z Y Z )
X (Z (Y Y ) X (Z (Y Y ))
X (Z.1) X (Z.1)
(Y Y 1)
XZ XZ
Z(X X )
Z.1
Z
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(X X 1)
Continued
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(putting B B 0 )
(putting C.C =C )
(putting AC A C Demorgans 2nd theorem)
(rearranging the terms)
(putting A AB A B becauseX X Y X Y )
A C B A BC A C B B AC
A C B AC
(putting B B AC B AC because X X Y X Y )
A B C CA
A BC A
A A BC
1 B C
1
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(C CA C A)
(putting A A 1 )
(as 1 + X = 1 i.e., anything added to 1 results in 1)
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[ 0 ]Y
[0]X
XY
[1]X
XY
[1]Y
[ 0 ]Y
XY
XY
[0]X
[1]X
(a)`
[1]Y
0
(b)
YZ
X
[00 ]Y Z
[0]X
XY Z
[1]X
XY Z
0
4
YZ
[01]Y Z
[11]YZ
[10]Y Z
X YZ
X YZ
XY Z
X YZ
1
5
XYZ
3
7
XY Z
2
6
[00 ]Y Z
[0]X
[1]X
(a)`
[11]YZ
[01]Y Z
[10]Y Z
(b)
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WX
YZ
[00 ]Y Z
[00]W X W X Y Z
[01]W X
W XY Z
[11]WX WX Y Z
[10]W X
0
4
12
W XY Z
[11]YZ
[01]Y Z
W X YZ
W X YZ
W X YZ
W XYZ
[10]Y Z
W XY Z
WX
W XY Z
[00]W X
[01]W X
WX Y Z
13
WXYZ
15
WXY Z
14
[11]WX
W X YZ
W X YZ
W XY Z
[10]W X
11
10
[00 ]Y Z
[11]YZ
[01]Y Z
[10]Y Z
12
13
15
14
11
10
(a)`
(b)
See the binary numbers at the top of K-map which do not follow binary progression, instead
they differ by only one place when moving from lest to right : 00, 01, 11, 10.
It is done so that only one variable changes from complemented to uncomplemented form or
vice versa. See AB, AB, AB, AB.
This binary code 00, 01, 11, 10 is called Gray Code.
Gray Code is the binary code in which each successive number differs only in one place.
Continued
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[0]
[0]
[1]
[0]
[0]
[1]
[1]
(a)`
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[0]
[1]
[0]
[1]
[1]
1
(b)
(c)
Continued
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YZ
WX
[00]W X
[01]W X
[11]WX
[10]W X
[ 00 ]Y Z
[ 01 ]Y Z
[10 ]Y Z
[11]YZ
1
0
0
12
5
13
0
1
0
15
11
0
1
0
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14
10
( X X 1)
WYZ
Continued
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YZ
[ 00 ]Y Z
WX
[00]W X
[01]W X
[11]YZ
[10 ]Y Z
[ 01 ]Y Z
WX
[00]W X
[01]W X
6
[11]WX
[11]WX
12
13
15
[10]W X
8
[00]W X
[ 00 ]Y Z
11
12
13
15
YZ
WX [ 00 ]Y
1
[00]W X
1
(b)
Z
0
[11]YZ
10
[11]YZ
[10 ]Y Z
[10]W X
[10 ]Y Z
[ 01 ]Y Z
1
1
11
6
14
10
Quads
[ 01 ]Y Z
[11 ]YZ
[10 ]Y Z
[01]W X
[01]W X
[11]WX
[10]W X
[ 01 ]Y Z
14
(a )` Pairs
YZ
WX
[ 00 ]Y Z
12
13
15
14
(c) quad
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11
10
[11]WX
[10]W X
12
13
15
14
1
(d )
octet
11
10
Continued
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[11]WX
[10]W X
12
YZ
[11 ]YZ [10 ]Y Z
13
15
14
11
10
WX
[00]W X
[01]W X
[11]WX
[10]W X
12
15
14
11
10
13
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Continued
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m15
1111 WXYZ
[11]WX
12
[10]W X
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15
11
14
10
In above K-map two groups have been marked, one Pair and one Quad.
Pair is m7 + m15 and Quad is m0 + m2 + m8 + m20
Reduced expression for pair (m7 + m15) is XYZ as W is removed.
Reduced expression for quad (m0 + m2 + m8 + m10) is X Z as for
horizontal corners Y is removed and for vertical corners W is removed.
The final reduced expression is XYZ X Z .
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In P-O-S reduction each square of K-map represents a Maxterm of the given function.
Karnaugh map is just the same as that of used in S-O-P reduction.
For a function of n variables, there would be a map 2n squares, each representing a Maxterm.
For P-O-S reduction map is filled by placing 0s in squares whose Maxterm lead to output 0.
The numbers in the squares represents Maxterm subscripts.
Box with number 1 represents M1, number 6 box represents M6, and so on.
The box numbering scheme is the same as S-O-P i.e., 0, 1, 3, 2; 4, 5, 7, 6; 12, 13, 15, 14; 8, 9, 11, 10.
One more similarity in S-O-P K-map and P-O-S K-map is that they are binary progression in Gray
code only.
One major difference is that in P-O-S K-map, complemented letters represent 1s and
uncomplemented letters represent 0s whereas it is just the opposite in s-O-P k-map.
Following are 2, 3, 4 variable K-map for P-O-S reduction :
Y
X
[0] X
[1]X
[ 0 ]Y
[1]Y
0
X
1
(a)`
[0] X
[1]X
[1]Y
[ 0 ]Y
(X Y)
(X Y)
(X Y)
(X Y)
2
(b)
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Continued
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YZ
[00]Y Z [01]Y Z
X
[0] X
[1]X
[11]Y Z
[10]Y Z
[10]Y Z
[0] X
X Y Z
0
X Y Z
1
X Y Z
3
X Y Z
2
[1]X
X Y Z
X Y Z
X Y Z
X Y Z
(c)`
(d )
YZ
[00]
[01]
[11]
YZ
[10]
WX
[00]
[01]
[11]
[10]
[00]Y Z
[01]Y Z
[11]Y Z
[10]Y Z
WX
0
12
8
13
9
15
11
14
10
[00]Y Z
W X Y Z W X Y Z
0
1
W X Y Z W X Y Z
[01]Y Z
W X Y Z
W X Y Z
W X Y Z W X Y Z
[11]Y Z
[10]Y Z
W X Y Z
12
W X Y Z
8
W X Y Z
W X Y Z
15
14
W X Y Z
W X Y Z
11
10
(f)
W X Y Z W X Y Z
13
(e)`
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Continued
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Continued
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BC
[00]
[01]
[11]
[10]
[0]
[1]
Solution :
First of all, well have to encircle all possible groups of adjacent 0s.Encircling we get the following K-map.
BC
A [00]B C
[ 0] A
[1] A
0
0
[01]B C
0
1
[11]B C
[10]B C
Pair-1 = M0 . M1 ;
Pair-2 = M0 . M4 ;
Pair-3 = M1 . M3 .
There is one reduntant group which is Pair-1.
By removing this Pair-1, we have only two groups now.
Reduced P-O-S expression for Pair-2 is ( B + C ), as while moving across Pair-2, A changes its state
from A to A , thus A is removed.
Reduced P-O-S expression for Pair-3 is ( A C ), as while moving across Pair-3 B changes to B ,
hence eliminated.
Final P-O-S expression will be (B C).(AC)
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There are some more logic gates which are NOR, NAND, XOR, XNOR gates.
These gates are derived from three basic gates i.e., AND, OR and NOT and are widely used
in industry.
NOR Gate
NAND Gate
XOR Gate
XNOR Gate
NAND to NAND and NOR to NOR design
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F X Y
F X Y Z
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0 1 1, 1 0 1, 1 1 0,
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Continued
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(X X X )
Continued
53
Similarly, Y NAND Y Y
Therefore, (X NAND X) NAND (Y NAND Y)
X NAND Y
X .Y
X Y
X Y
Continued
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NOT X = X NAND X
Proof. X NAND X X . X X
NAND-to-NAND logic is best suited for Boolean expression
form.
(inXSum-of-Products
.X X )
Design rule for NAND-TO-NAND logic Network (only for 2 level circuit)
1. Derive simplified sum-of-products expression.
2. Draw a circuit diagram using AND, OR gates.
3. Replace all basic gates (AND, OR, NOT) with NAND gates.
Example : Draw the diagram of digital circuit for
F(a, b, c) = AB + BC + CD using NAND-to-NAND logic.
Solution: F(a, b, c) = AB + BC + CD
= ( A NAND B) NAND (B NAND C) NAND (C NAND D)
Continued
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AND operation
A . B = (A NOR A) NOR (B NOR B)
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Continued
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