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I. INTRODUCTION
Recent approaches for nano-scale semiconductor devices place a lot of emphasis on materials and structures [13]. The enhancement of carrier mobility in the
conduction channel needs high-mobility materials such
as Si1x Gex and strained-Si. However, a conventional
MOSFET with strained-Si channel has some disadvantages such as a limit of scaling, high-electric field in the
channel, and corresponding degradation of mobility. For
the solution of these problems, we propose and simulate a high-performance center-channel (CC) double-gate
(DG) structure incorporating the materials Si1x Gex
and strained-Si. To fulfill the numerical simulation of
nano-scale structures such as DG MOSFET, we need to
obtain a self-consistent solution of the coupled PoissonSchr
odinger equations. The CC-NMOS device exhibits
enhancement of current drive and switching speed caused
by a decrease of surface roughness scattering and mobility enhancement of the strained-Si channel. In this
paper, we report our self-consistent QM approach for
the analysis of CC-NMOS. The electrical performance of
CC-NMOS was carefully investigated in terms of channel
length (Lg ) (10 80 nm) and gate oxide thickness (Tox )
(2 nm). Device optimizations were performed in order to suppress the short-channel effects (SCE) through
some critical parameters such as subthreshold swing,
E-mail:
twon@hsel.inha.ac.kr;
Tel: +82-32-860-8686; Fax: +82-32-875-7436
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+
ND
(x, y) =
(4)
(5)
(9)
(10)
(11)
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For a model of carrier mobility, we employed a physicsbased and semi-empirical model which takes various scattering mechanisms into account by using the Mathiessen
rule [6]:
1
1
1
1
=
+
+
,
b
ac
sr
(12)
where b is the carrier mobility in the bulk, ac the carrier mobility from the surface acoustic phonon scattering,
and sr the carrier mobility from surface roughness.
The bulk mobility, b , uses the empirical model expressed by Masetti et al. [7], which depends on the impurity concentration and temperature:
1
max (T ) 0
,(13)
1 + (NA /Cr )
1 + (Cs /NA )
T
max (T ) = max
,
(14)
300
b (NA , T ) = 0 +
where E is the electric field perpendicular to the direction of current flow. Further, B and C are fitting parameters with initial values of Binit = 3.1 108 cm/s and
Cinit = 3.0 107 (V/cm)2/3 Kcm/s based on physical
quantities such as deformation potential, mass density of
silicon, and effective thickness of inversion layer [8].
At very high perpendicular electric field, surface
roughness scattering sr significantly affects the inversion layer mobility. This is described as follows [9]:
sr (E ) =
2 ,
E
(16)
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0.680
0.719
2.00
2.00
2.5
2.2
7
7
B
4.75 10
9.93 10
cm/s
C
1.74105 N0.125
8.84105 N0.125
NA in cm3
A
N
5.82 1014
2.05 1014
From Ref. 7
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Fig. 6. Comparison of electron density of CC and DGNMOS for Lg = 30 nm, Vd = 0.1 V, and Vg = 1.0 V.
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acteristics are demonstrated in Figure 11. From these results, we confirmed that both CC and DG-NMOS show
excellent subthreshold behaviors and successfully suppress the SCE.
IV. CONCLUSION
and DG-NMOS.
Figure 7 demonstrates a comparison of current-voltage
(Id -Vg ) characteristics of CC and DG-NMOS at the condition of Lg = 30 nm and Vd = 0.1 V. This simulation result shows enhancement of about 1.6x for current drive.
The transconductances (Gm ) of CC and DG-NMOS are
compared in Figure 8. The Gm of CC-NMOS increases
by about 60 % compared with that of DG-NMOS, showing Gm = 1428.3 S/m for CC-NMOS, and Gm = 891.3
S/m for DG-NMOS. This is due to enhancement of carrier mobility caused by the strained-Si and a decrease of
surface roughness scattering.
Finally, we estimated the SCE of CC and DG-NMOS
by performing a simulation with respect to Lg . Figure 9
shows the Id -Vg curves for CC-NMOS, produced under
the condition of Lg varying from 10 nm to 80 nm at Vd =
0.1 V. As Lg decreases, the short-channel behavior visibly comes in to sight. Therefore, we analyzed the SCE in
terms of subthreshold swing, threshold voltage (Vt ) rolloff, and drain-induced barrier lowering (DIBL). Figure
10 shows the subthreshold-swing of CC and DG-NMOS
in terms of Lg at Vd = 0.1 V. Vt roll-off and DIBL char-
In this paper, we report our two-dimensional numerical modeling and simulation results for center-channel
(CC) double-gate (DG) MOSFET in comparison with
those for conventional DG structure. CC operation of
CC-NMOS is confirmed by band lineups, lowest energy
wave function, and electron density. The simulation results also reveal that current drive and transconductance
are remarkably enhanced and short-channel effects are
appreciably suppressed. Our simulation results imply
that CC-NMOS structure is a promising candidate for
implementing sub-20 nm MOSFETs.
ACKNOWLEDGMENTS
This work was supported by the Research Program of
Inha University.
REFERENCES
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