Users Manual
Silvaco, Inc.
4701 Patrick Henry Drive, Bldg. 2
Santa Clara, CA 95054
Phone:
(408) 567-1000
Web:
www.silvaco.com
September 2, 2014
Notice
The information contained in this document is subject to change without notice.
Silvaco, Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY
OF FITNESS FOR A PARTICULAR PURPOSE.
Silvaco, Inc. shall not be held liable for errors contained herein or for incidental or
consequential damages in connection with the furnishing, performance, or use of this
material.
This document contains proprietary information, which is protected by copyright laws of the
United States. All rights are reserved. No part of this document may be photocopied,
reproduced, or translated into another language without the prior written consent of Silvaco
Inc.
AccuCell, AccuCore, Athena, Athena 1D, Atlas, Blaze, C-Interpreter, Catalyst AD, Catalyst
DA, Clarity RLC, Clever, Clever Interconnect, Custom IC CAD, DeckBuild, DevEdit,
DevEdit 3D, Device 3D, DRC Assist, Elite, Exact, Expert, Expert C++, Expert 200,
ExpertViews, Ferro, Gateway, Gateway 200, Giga, Giga 3D, Guardian, Guardian DRC,
Guardian LVS, Guardian NET, Harmony, Hipex, Hipex C, Hipex NET, Hipex RC,
HyperFault, Interconnect Modeling, IWorkBench, Laser, LED, LED 3D, Lisa, Luminous,
Luminous 3D, Magnetic, Magnetic 3D, MaskViews, MC Etch & Depo, MC Device, MC
Implant, Mercury, MixedMode, MixedMode XL, MultiCore, Noise, OLED, Optolith,
Organic Display, Organic Solar, OTFT, Quantum, Quantum 3D, Quest, RealTime DRC, REM
2D, REM 3D, SEdit, SMovie, S-Pisces, SSuprem 3, SSuprem 4, SDDL, SFLM, SIPC, SiC,
Silvaco, Silvaco Management Console, SMAN, Silvaco Relational Database, Silos,
Simulation Standard, SmartSpice, SmartSpice 200, SmartSpice API, SmartSpice Debugger,
SmartSpice Embedded, SmartSpice Interpreter, SmartSpice Optimizer, SmartSpice RadHard,
SmartSpice Reliability, SmartSpice Rubberband, SmartSpice RF, SmartView, SolverLib,
Spayn, SpiceServer, Spider, Stellar, TCAD Driven CAD, TCAD Omni, TCAD Omni Utility,
TCAD & EDA Omni Utility, TFT, TFT 3D, Thermal 3D, TonyPlot, TonyPlot 3D, TurboLint,
Universal Token, Universal Utility Token, Utmost III, Utmost III Bipolar, Utmost III Diode,
Utmost III GaAs, Utmost III HBT, Utmost III JFET, Utmost III MOS, Utmost III MultiCore,
Utmost III SOI, Utmost III TFT, Utmost III VBIC, Utmost IV, Utmost IV Acquisition
Module, Utmost IV Model Check Module, Utmost IV Optimization Module, Utmost IV
Script Module, VCSEL, Verilog-A, Victory, Victory Cell, Victory Device, Victory Device
Single Event Effects, Victory Process, Victory Process Advanced Diffusion & Oxidation,
Victory Process Monte Carlo Implant, Victory Process Physical Etch & Deposit, Victory
Stress, Virtual Wafer Fab, VWF, VWF Automation Tools, VWF Interactive Tools, and Vyper
are trademarks of Silvaco, Inc.
All other trademarks mentioned in this manual are the property of their respective owners.
Copyright 1984 - 2014, Silvaco, Inc.
Style Conventions
Font Style/Convention
Description
Example
1.
To open a door:
1. Unlock the door by inserting
the key into keyhole.
2. Turn key counter-clockwise.
3. Pull out the key from the
keyhole.
4. Grab the doorknob and turn
clockwise and pull.
FileOpen
Courier
HAPPY BIRTHDAY
File
symbol
New Century
Italics
x+y=1
2.
3.
Note:
Schoolbook
Bullet A
Bullet B
Bullet C
Table of Contents
Chapter 1
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 What is Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Gateway Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3 QuickStart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Loading Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.2 Checking the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3 Netlisting and Control Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.4 Input Deck and Pre-Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.5 Simulation and Cross-Probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3.6 Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 2
File Operations and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1 GUI Environment and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.1 Windows and Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.2 Preferences Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.2 Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.3 Number Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.2.4 Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.2.5 Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.2.6 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2.7 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.2.8 Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.2.9 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2.10 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.2.11 Managing Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3 Special Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.4 File Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4.1 Loading a Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4.2 Opening a Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.4.3 Create a New Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.4.4 Saving Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.4.5 Exporting Drawings to Picture Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.4.6 Printing from Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.5 Importing and Exporting Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.5.1 Exporting Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.5.2 Importing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.6 Help Menu and User Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table of Contents
Chapter 3
Schematic Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.1 Gateway Design Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.1.1 Flat Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.1.2 Hierarchical Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.2 Navigating between Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.3 Sheet to Sheet Connecting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 4
Libraries and Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.1 Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2 Workspace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.2.1 Changing Workspaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.2.2 Saving Workspaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3 Library Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.1 Library Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.2 Library Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.3 Modifying Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.3.4 Version Control System (VCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Chapter 5
Schematic Editing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.1 Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.2 Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.3 Filtering Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.1.4 Switching Design Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.2 Placing Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.1 Selecting and Deselecting Objects/Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.2.2 Rotating and Mirroring Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.2.3 Moving Symbols and Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.4 Copying and Pasting Objects and Symbol Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.5 Deleting Wires, Objects, or Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2.6 Disconnecting Wires and Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3 Attribute Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.4 Editing Symbol Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.4.1 Ordering and Positioning Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.5 Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.1 Wiring Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.5.2 Creating Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.5.3 Wire Snapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.5.4 Diagonal Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.6 Inherited Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.6.1 Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.6.2 The netInherit Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.6.3 Net Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.6.4 Inherited Net Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.7 Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table of Contents
Chapter 6
Viewing and Navigating Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.1 The View Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.1.1 Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.1.2 Ascending and Descending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.1.3 Design Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.1.4 Showing Node and Symbol Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.1.5 Viewing Net Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.1.6 Viewing the Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 7
Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.2 Checking a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.2.1 Error Handling and Viewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.2.2 Enabling and Disabling Warnings and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.3 Netlisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table of Contents
Chapter 8
Simulation and Post-Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
8.1 Pre-Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
8.2 Analog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
8.2.1 Marking the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
8.2.2 Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
8.2.3 Calculating DC Operating Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
8.2.4 DC Bias Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.2.5 Threshold Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
8.2.6 SmartSpice Status and Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
8.2.7 Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
8.3 Digital Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Chapter 9
EDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
9.2 EDIF Import Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
9.2.1 Importing an EDIF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
9.3 Conversion of Imported Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
9.3.1 Conversion Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
9.4 Exporting EDIF 2 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Chapter 10
Schematic Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.1 Importing Verilog and SPICE into Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.2 Example 1 Importing Verilog to a New Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
10.3 Example 2 Importing Spice to an Existing Symbol Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Chapter 11
Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
11.1 Javascript in Gateway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.1 Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.2 Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.3 Run Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.4 Run Script with Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.1.5 Command line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
11.2 Callback Scripting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table of Contents
Appendix A
Communications Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
A.1 Common Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
A.1.1 Cannot create input deck/netlist/control deck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
A.1.2 Simulation Does Not Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
A.1.3 Cannot Plot Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
A.1.4 DC Bias markers Not Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
A.1.5 Output/Error File Not Present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
A.1.6 Licensing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
A.1.7 Nameservice Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Chapter 1
Getting Started
What is Gateway
Getting Started
Gateway is the entry point of the design as its main purpose is generating a netlist that can be
loaded into circuit simulators. Schematics are drawn in Gateway and then transformed into a
specified netlist format. This netlist is an ASCII file describing the circuit connectivity. This
is the first file needed for the simulation flow. The next file used in the design process is the
control file, which can be created for each simulator that Gateway will run. This control file
contains all model and simulation options and parameters. When you create a netlist and a
control file, they merge to form the main portion of the input file.
At this point, Gateway can be switched into the simulation mode before running the
simulation. The simulation mode is used for marking node voltages and branch currents to be
plotted. These markers complete the input file that is submitted to the simulator for
simulation. Then, the simulator loads and simulates the input file and displays the progress of
the simulation in a dialog. Following the completion of the simulation, output and rawfiles
may be generated for viewing. The output file contains the text output of the simulation and
all the statistics and results of the run. The rawfile contains all the raw graphical data for
viewing the waveforms in SmartView. When the simulation finishes and generates the
rawfile, SmartView launches automatically and loads the rawfile with waveforms plotted.
At this point, it is common to have the Gateway Schematic window open and the SmartView
Plot window open with the waveforms. Any vectors (traces) that were saved into the rawfile
can then be marked back on the schematic and plotted, or cross-probed, from there. With
cross-probing, you can select and plot any combination of saved vectors on the schematic
following the simulation.
Note: Waveforms are plotted for the SmartSpice family of simulators.
10
What is Gateway
Getting Started
11
Gateway Window
Getting Started
12
QuickStart
Getting Started
1.3 QuickStart
1.3.1 Loading Files
This quickstart section describes the basic steps of using Gateway by going through the
current mirror example that is shipped with the software. First, launch Gateway and then
proceed to open the workspace for the current mirror. To do this, first select
FileOpenWorkspace. Then, browse to the following directory:
<installation_directory>\examples\gateway\<date>\analog\006_current_mirror
Select current_mirror.workspace and finally click OK. When the workspace loads, the
available libraries will appear in the library pane. Clicking one of these libraries in the pane
displays the list of symbols available below in the symbol pane. You can change the display
view of the symbols by clicking the pulldown menu and choosing a view. The large icon view
is the default.
Now, select FileOpenSchematic and select current_mirror.schlr from the dialog
and click OK. The Gateway window will appear as shown in Figure 1-3.
13
QuickStart
Getting Started
Click the spicelib library name in the library pane and the symbols will appear in the symbol
pane. Click on any symbol in the symbol pane and then move the mouse over the schematic.
The symbol will be attached to the pointer for placement. Press the ESC key to return to the
default select mode.
14
QuickStart
Getting Started
15
QuickStart
Click
Getting Started
again to check the drawing and then click the Session tab. The following
16
QuickStart
Getting Started
The netlist has been created successfully. Now click the Edit Control File icon (Figure 1-11)
to look at the control statements and the Control File window will appear (Figure 1-12).
17
QuickStart
Getting Started
For example, to generate a .TRAN statement, click the transient icon (Figure 1-14) and type
the parameters into the Transient dialog (Figure 1-15).
18
QuickStart
Getting Started
19
QuickStart
Getting Started
Notice that the statements in the control file appear in the Analyses pane of Figure 1-16.
Moving the mouse over that pane displays a tooltip of the entire statements for quick viewing.
This shows exactly what is set to run without having to open the control file. Figure 1-18
shows the tooltip.
On the Cross Probe pane, there are columns for the name of the vector, the type of vector, and
the schematic and sheet where they exist. A check in the Save column means the vector will
be saved for the analyses run. A check in the Plot column means that vector will be plotted
after simulation. A check in the March column means the vector will be plotted real-time
using SmartSpices interactive plotting. The vectors update as the simulation progresses.
To the right side of the cross probe pane, there are some checkboxes enclosed in a box named
Save. These checkboxes are used to save vectors by type but not to plot them unless chosen
after the simulation. By default, nothing is saved unless marked on the schematic or checked
by these checkboxes. All vectors that are marked (have cross probes) will be plotted while the
vectors saved by the checkboxes will be available in SmartViews data browser for plotting
after the simulation. After the simulation, any vector saved can be probed on the schematic
and plotted by dropping the marker on the schematic and clicking the Plot button (see Figure
1-17).
20
QuickStart
Getting Started
21
QuickStart
Getting Started
22
QuickStart
Getting Started
23
QuickStart
Getting Started
1.3.6 Sessions
A Session consists of the environment that is open and loaded into Gateway at any time. This
can be a workspace only, or a workspace plus any number of drawings. When Gateway is
exited, the session is automatically saved so that next time the application is launched, the
session may be resumed as it was before it was closed. This saves time in loading workspaces
and opening drawings if it is desired to resume the previous session.
When Gateway is launched, a dialog may appear, depending on the Session settings in the
user preferences (see Figure 1-24). Clicking Yes resumes the previous session. Clicking No
opens Gateway without anything being pre-loaded. Clicking Exit closes Gateway.
24
Chapter 2
File Operations and Settings
26
The Session tab (Figure 2-2) can contain multiple types of information. These can be filtered
by the icons in the top left.
Information
Warning
Shows/Hides warnings.
Error
Shows/Hides errors.
Script
27
28
29
30
31
Preferences Dialog
Application
Auto-Save
Colors
Drawing Checks
Frame
Grid
Information
Naming
Netlist
Atlas
CDL
LVS/Guardian
NDL
SPICE
Verilog
Number Format
Reporting
Session
Shortcuts
Technology
Toolbars
User Interface
Tools
Layout Editor
Simulator
Text Editor
Waveform Viewer
32
Preferences Dialog
2.2.1 Application
These are the options that affect Gateway. These are the settings:
Auto-Save
Colors
Drawing Checks
Frame
Grid
Information
Naming
Auto-Save
Turn Auto-Save On by setting the Enable property to True and all open drawing(s) will be
saved at the interval specified in the Interval box. The smallest interval to Auto-Save is 1
minute. The default is 5 minutes. If the Auto-Save is Off, the recovery system is turned off
and the changes are lost if Gateway exits unexpectedly. The other options on this dialog are
Save Drawings when simulating - Saves all active open drawings when a simulation is
run.
Save Drawings when checking - Saves all active open drawings when a drawing check
is run.
Show conversion warning - Shows warnings if saving the drawings will result in a file
conversion format change.
33
Preferences Dialog
Colors
Figure 2-8 shows the color settings.
This is the dialog where all colors for the Gateway application can be changed. The pulldown menu called Color Scheme is set to the black color scheme by default. There are four
preset schemes: Black, White, Printer, and Custom. The colors for the selected scheme are
shown below in the palette. To modify any color, select the item and click the Change Color
button or double-click on a row in the table.
There is a Preview window at the bottom of the dialog that displays the effect of both the
items selected in the list and the effect of the current color scheme.
The Editing Colors are
34
Preferences Dialog
35
Preferences Dialog
Drawing Checks
Figure 2-9 shows the settings for warnings and errors. The dialog is broken down into two
sections: System Drawing Checks and Configurable Drawing Checks.
System Drawing Checks consist of errors only and cannot be downgraded to warnings. These
are marked by a red icon ( ) and each has an index number to reference the error. Errors
prevent a netlist from being generated.
Configurable Drawing Checks can be either warnings or errors, depending on how severe you
want to label each drawing check. Warnings are marked by ( ) yellow icons. To toggle a
specific drawing check, click the box in the Status column. In the Severity Column, all checks
are set as warnings unless you check the box and set to Error status. You can also turn off the
status of configurable checks using the Review Errors pane by right-clicking on a given
drawing check and selecting Disable.
36
Preferences Dialog
Frame
Figure 2-10 shows the frame settings.
37
Preferences Dialog
38
Preferences Dialog
Grid
Figure 2-11 shows the grid settings.
39
Preferences Dialog
The Major Multiplier (Schematic or Symbol) is set to 8 by default. This number is used in
calculating the Major Grid distance. The major grid is outlined with darker lines on the grid
(the grid color).
Major Grid distance = ( Snap Spacing Minor multiplier Major multiplier )
= ( 0.0625 2 8 )
= 1 inch
See Figure 2-12 for a graphical representation of the default grid.
Show as Grid (Schematic) - Grid is drawn on the Schematic view as either Dots or
Lines.
Dots - Dots drawn at the Major and Minor X and Y Grid intersections.
Lines - Lines drawn on the Major and Minor X and Y grid lines.
Show as Grid (Symbol) - Grid is drawn on the Symbol view as either Dots or Lines.
Dots - Dots drawn at the Major and Minor X and Y Grid intersections.
Lines - Lines drawn on the Major and Minor X and Y grid lines.
40
Preferences Dialog
41
Preferences Dialog
Information
This shows the tooltips or the information bubbles.
42
Preferences Dialog
Naming
This specifies the net naming format that is generated by Gateway.
The Symbol Name Separator field is for specifying a string that will go between the symbol
prefix and referemce designator for the netlist. The Net name format option sets the naming
scheme for system-generated nets.
43
Preferences Dialog
2.2.2 Netlist
These options control the generation of the supported netlists in Gateway. These are the
settings:
Atlas
CDL
LVS/Guardian
NDL
SPICE
Verilog
44
Preferences Dialog
Atlas
Figure 2-15 shows the settings that can be used to generate the Atlas netlist.
3D Mode - Adds .begin 3d at the top of the netlist to place Atlas in 3D mode.
Include Atlas control file - Includes the Atlas control file in the netlist. The control file
will be appended to the netlist. If you enter a .end statement in their Atlas control file,
then Gateway will not add one. If Gateway detects that a .end is missing, it will add one
to the end of the netlist.
Use quotation marks where neccessary - If checked, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
Default File Extension - Sets the default file extension for the Atlas netlist. The default is
.in.
Line length - Sets the maximum number of characters per line in the netlist.
Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
45
Preferences Dialog
Order Pins
Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
Manual editing - When True, the generated files (.net and .in) will be writable.
46
Preferences Dialog
CDL
Figure 2-16 shows the settings that can be used to generate the CDL (Circuit Desciption
Language) netlist.
Include CDL control file - If True, this adds the contents of the CDL control file to the
netlist.
Use quotation marks where neccessary - If True, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
Line length - Sets the maximum number of characters per line in the netlist.
Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
Order Pins
Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
Manual editing - When True, the generated files (.net and .in) will be writable.
47
Preferences Dialog
LVS/Guardian
Figure 2-17 shows the settings that can be used to generate the LVS and Guardian netlist.
Add .SUBCKT around top level - Creates a subcircuit of the entire design by placing a
.SUBCKT and .ENDS around the contents of the design.
Include LVS control file - Adds any statements (model, dotcard, or other types) written
in the Guardian control file into the Guardian netlist. This includes anything defining
pcells or model related that is unrelated to the actual simulation.
Use quotation marks where neccessary - If True, Gateway will put quotation marks
around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or contain
spaces.
Line length - Sets the maximum number of characters per line in the netlist.
Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
Order Pins
Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
48
Preferences Dialog
49
Preferences Dialog
NDL
Figure 2-18 shows the settings that can be used to generate the Netlist Driven Layout (NDL)
netlist.
Add .SUBCKT around top level - Creates a subcircuit of the entire design by placing a
.SUBCKT and .ENDS around the contents of the design.
Include NDL control file in netlist - Adds any statements (model, dotcard, or other
types) written in the NDL control file into the NDL netlist. This includes anything
defining pcells or model related that is unrelated to the actual simulation.
Use quotation marks where neccessary - If set to True, Gateway will put quotation
marks around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or
contain spaces.
Line length - Sets the maximum number of characters per line in the netlist.
Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
50
Preferences Dialog
Order Pins
Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
Manual editing - When set to True, the generated files (.net and .in) will be writable.
51
Preferences Dialog
SPICE
Figure 2-19 shows the settings that can be used to generate the SPICE netlist.
Use quotation marks where neccessary - If set to True, Gateway will put quotation
marks around values of attributes if they contain mathematical operators (e.g., +,-,/,*) or
contain spaces.
Line length - Sets the maximum number of characters per line in the netlist.
Rebuild Netlist Always - Rebuilds the netlist by default when an input deck or
simulation is run.
Order Pins
Alphanumerically - Orders pin names on subcircuit definitions alphanumerically.
by direction - Orders pin names on subcircuit definitions by their direction (input,
output, and bidirectional).
by Verilog definition - Orders pin names on subcircuits by their Verilog string
definition.
Manual editing - When True, the generated files (.net and .in) will be writable.
52
Preferences Dialog
Verilog
Figure 2-20 shows the settings that can be used to generate the Verilog netlist.
53
Preferences Dialog
The default is the nearest Systeme Internationale (S.I.) prefix. For example, the number
1e-006 will be displayed as 1u.
54
Preferences Dialog
Equation:Precision - Specifies the precision of the result for values calculated by and
equation.
2.2.4 Reporting
This controls the reporting level and what to show in the Session Window.
55
Preferences Dialog
2.2.5 Session
This controls whether to resume the previous session.
Resume previous session - Only reloads the workspace from the last session, not
the schematics.
Always - Automatically loads the last Gateway session when launching a new
session. The session is the workspace and all open schematics (default).
Never - Opens Gateway without loading the prior session.
Query - Asks you when running Gateway whether you want to resume the last
session.
Working Directory - Sets the location of the current working directory.
Use workspace directory - Sets the current working directory to the location of
the currently loaded workspace.
Use current working directory - Sets the working directory to directory gateway
was started from.
User defined working directory - Sets the current working directory to the path
set in the User defined directory property.
User defined directory - This is the path to the user defined location to use for the
current working directory.
56
Preferences Dialog
The Ask Before Qutting option ensures the session option will be set before exiting
Gateway.
2.2.6 Shortcuts
Figure 2-24 shows the Shortcuts settings in the Preferences dialog.
57
Preferences Dialog
2.2.7 Technology
Figure 2-25 shows the Technology settings in the Preferences dialog.
Assigning the name GND to the NBulk node or PBulk node box in the preferences means that
GND will be the node name put in the netlist for the bulk pins on these symbols. These
symbols usually only have three physical pins for wiring. Using these bulk definitions,
however, allows these symbols to netlist as four pin devices with a bulk node.
58
Preferences Dialog
2.2.8 Toolbars
Figure 2-26 shows the Toolbars settings in the Preferences dialog.
59
Preferences Dialog
60
Preferences Dialog
61
Preferences Dialog
2.2.10 Tools
This controls the external applications (e.g., SmartSpice) that you run. These are the settings:
Tools
Layout Editor
Simulator
Text Editor
Waveform Viewer
Layout Editor
Figure 2-29 shows the Layout Editor settings in the Preferences dialog. This dialog is used to
set the version and path of Expert. When checked, the Use Default Path box sets the path to
the same location where Gateway is installed. If this checkbox is unchecked, you can set the
path to another location to point to the directory where Expert is installed. The combo-box
allows you to select the version. Default is the latest version.
62
Preferences Dialog
Simulator
The Simulator settings in the Preferences allows the choice of target simulator, version, path,
and various startup options for the following simulators:
SmartSpice and SmartSpice RF
SmartSpice is set as the default simulator. When checked, the Use Default Path box sets the
path to the same location where Gateway is installed. If this checkbox is unchecked, you can
set the path to another location to point to the directory where the simulator is installed. The
combo-box allows you to select the version. Default is the latest version. The Host combobox allows you to choose whether to run SmartSpice locally or remote. If running remotely,
you will need to enter the host, user, password, and executable location on the remote
machine. A valid SSH server will need to be installed on the remote machine for this
functionality to work. The settings described in this section apply to the complete SmartSpice
family of simulators.
63
Preferences Dialog
Hostname The name of the host machine to run the SmartSpice simulation on. This
machine must have SSH installed and be capable of running SmartSpice.
Username The username of the valid account that SmartSpice runs under on the
remote host machine.
Password The valid password for the user account that SmartSpice will run under on
the host machine. This will be encrypted before being stored on the local machine. You
will be prompted for the password if not supplied.
Executable The path to the executable on the host machine for SmartSpice. This path
must be supplied. The installation location maybe different on the remote host.
Plot Vectors every The number of points calculated by SPICE and then plotted at a
time. This number of points is calculated and held in memory. It is then released to the
disk when the number has been reached.
Raw File Directory The directory to write raw file. The default is the working
directory.
Output File Directory The directory to write output file. The default is the working
directory.
Suppress Rawfile If checked, a rawfile will not be written. When SmartView is closed,
all data will be lost. If unchecked, a raw file will be written.
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Preferences Dialog
Load DC Bias points If enabled, Gateway will load the DC Bias points generated by
the last run of this simulation.
Generate DC Bias points If enabled, Gateway will request the simulator to generate
the DC Bias points and will store them with the simulation.
Startup File
Do Not Read This will not read a startup file when launching SmartSpice.
Default This will use the default SmartSpice initialization file.
User-defined If enabled, this specifies the path to the file to be read on the
startup for SmartSpice.
Timeout The number of seconds to wait for SmartSpice to start.
User-defined startup file - The file to be read on Smartspice startup.
Number of core processors Specifies the number of processors SmartSpice will use.
Number of solver processors Specifies the number of processors SmartSpice will use
when solving.
Command Line Any additional command line options can be specified here (e.g., hspice).
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Preferences Dialog
Atlas (DeckBuild)
Figure 2-32 shows the Atlas and DeckBuild tool settings in the Preferences dialog. This
dialog is used to set the version and path of DeckBuild. When checked, the Use Default Path
box sets the path to the same location where Gateway is installed. If this checkbox is
unchecked, you can set the path to another location to point to the directory where DeckBuild
is installed. The combo-box allows you to select the version. Default is the latest version.
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Preferences Dialog
HSPICE
Figure 2-33 shows the HSPICE tool settings. In the simulator text box, specify the path to the
HSPICE executable. By default, the Generate log file box is True, which generates an ASCII
*.lis file.
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Preferences Dialog
Silos
Figure 2-34 shows the Silos tool settings. When checked, the Use Default Path box sets the
path to the same location where Silos is installed. If this checkbox is unchecked, you can set
the path to another location to point to the directory where the simulator is installed. The
combo-box allows you to select the version. Default is the latest version.
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Preferences Dialog
Text Editor
Figure 2-35 shows the Text Editor settings in the Preferences dialog. This dialog is used to set
the text editor for supporting all text files that run in Gateway. This includes the netlist
(.net), control file (.ctr), input deck (.in), output file (.out), and error file (.err). The
default text editor is the Silvaco Text Editor. To choose a different editor, click the Other
Editor and then the Browse button to specify the path to the executable.
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Preferences Dialog
Waveform Viewer
The Waveform Viewer settings in the Preferences allows the choice of target waveform
viewer, version, path, and various startup options for the following viewers:
SmartView
Figure 2-36 shows the SmartView settings in the Preferences dialog. When checked, the Use
Default Path box sets the path to the same location where Silvaco EDA tools are installed. If
this checkbox is unchecked, you can set the path to another location to point to the directory
where SmartView is installed. The combo-box allows you to select the version. Default is the
latest version.
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Preferences Dialog
TonyPlot
Figure 2-37 shows the TonyPlot Viewer settings in the Preferences dialog. TonyPlot is the
viewer used for analyzing Atlas MixedMode simulations. This dialog is used to set the
version and path of TonyPlot. When checked, the Use Default Path box sets the path to the
same location where Silvaco and Silvaco EDA tools are installed. If this checkbox is
unchecked, you can set the path to another location to point to the directory where TonyPlot is
installed. The combo-box allows you to select the version. Default is the latest version.
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Preferences Dialog
AvanWaves
Figure 2-38 shows the AvanWaves Viewer settings in the Preferences dialog. AvanWaves is
the viewer used for analyzing HSPICE simulations. This dialog is used to set the version and
path of AvanWaves. Use the Browse button lo locate the path for the awaves executable.
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Preferences Dialog
Exporting Preferences
Figure 2-39 shows the Manage Preferences settings in the Preferences dialog.
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Preferences Dialog
74
Preferences Dialog
Importing Preferences
After settings are exported to a *.spf file, they may be imported into Gateway on any
computer. To import a preferences file, click the Import button on the Manage Settings
window of the Preferences dialog. The Import Preferences dialog will appear (Figure 2-41).
In this example in Figure 2-41, only the colors from the blk_031605.spf preferences file
will import into the existing Gateway preferences. This makes it easy to pick and choose
which settings you may want to import from different preferences files. To import preferences
from multiple files, repeat the steps to import, checking only the preferences you want from
each specified file.
Factory Settings
To reset the preferences back to the original Gateway defaults, click the Factory Settings
button. The dialog in Figure 2-42 appears to confirm whether you want to reset to the default
settings.
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Preferences Dialog
Recent Files
To clear the recent file menus from memory, press the Recent Files button. Then click Yes on
the confirmation dialog. That clears the recent file menu and the recent workspace menus.
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Special Keys
Esc Pressing the escape key returns Gateway to the default mode, the select mode.
S The s key is reserved for wire snapping or auto wiring
Shift This modifier key has multiple purposes:
77
File Operations
78
File Operations
79
File Operations
80
File Operations
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File Operations
If you edit multiple drawings and then close Gateway, you will be prompted once to save all
edited files (see Figure 2-50).
File Types
*.bmp
*.jpeg, *jpg
*.pbm
Portable Bitmap
*.pgm
Portable Graymap
*.png
*.ppm
Portable Pixmap
*.xbm
X Bitmap
*.xpm
X Pixmap
To export the drawing, open the drawing, click FileExportTo File, and type the name of
the desired file. Then, select the type as shown in Figure 2-51.
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File Operations
83
File Operations
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File Operations
The Show Preview checkbox displays the preview window when checked and hides it when
unchecked.
The Exclusion tab is used to exclude cells from specific libraries to be printed. To exclude a
library from printing, click the Add button and then type the name of the library in the Add
Exclusion Library text box.
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86
87
When a schematic design is open and the Export Design is selected, the dialog will look
similar to Figure 2-55.
88
Expanding even further (Figure 2-57) reveals the individual files that are to be exported with
the active selection. Notice that when a schematic design is exported, only the required
symbols that are found on the schematic design are exported instead of the entire symbol
libraries. The reason is to export only what is needed for the design. To export the entire
libraries, select from the libraries listed under Workspace in the tree.
89
Figure 2-58 shows the Export Design dialog for a design after a simulation was run and
completed. Now in addition to everything that existed in the dialog from before the
simulation, there are additional input files (netlist and input file) and an output file category to
include any raw, output, and error files. The Export Design tool is versatile in that it allows
you to export the entire design or any portion thereof by selecting only what you want to
export.
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91
92
Chapter 3
Schematic Structures
Schematic Structures
94
Schematic Structures
95
Schematic Structures
96
Schematic Structures
In Gateways Design Browser window, the top level of any design is the root branch. From
there, the tree expands down for each level of hierarchy. You can select any symbol that has a
sub-schematic on the drawing and descend into it. You can ascend/descend through the
hierarchy using the View menu options or the Design Browser. Figure 3-3 shows the Design
Browser window for this example.
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Schematic Structures
98
Schematic Structures
99
Chapter 4
Libraries and Workspace
Libraries
4.1 Libraries
A library in Gateway is a directory on an operating system that contains schematics or
symbols or both. Schematics have a .schlr file extension and symbol files have a .symbol file
extension. The library structure in Gateway is flat, meaning that each directory must be
mapped individually in the workspace to be valid. Subdirectories are ignored if they are not
mapped with their own paths in the workspace. The symbols in the Library/Symbol pane are
listed alphabetically. The default view is the Large Icon view. You can choose from one of the
four available views to display the available symbols by using the combo box in the symbol
pane.
The spicelib is the default library in Gateway. This contains the active and passive
SmartSpice symbols needed for simulating any simple design using SmartSpice. The spicelib
library contains subcircuit cells for the examples. Although schematics are contained in
libraries, they are not visible in the library or symbol pane areas. Only symbols appear in the
symbols pane. If there is a symbol and schematic with the same name in a same library, such
as inverter.symbol and inverter.schlr, the inverter symbol appears in the symbol pane
for that library. This also describes a descendable pair, or a symbol file that descends into its
schematic view, as the files have the same base name and are in the same library.
There is an examples folder under your Silvaco installation directory. From there, choose the
Gateway folder. The following describes the structure of that directory:
There is a libraries directory has five library folders:
spicelib
rflib
digilib
atlas
vprims
analog
digital
rf
tcad
Note: For libraries containing more than 1000 symbols, Gateway will create sub-libraries up to 1000 symbols in
each for best performance in searching and sorting symbols.
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Workspace
4.2 Workspace
The workspace is a file containing the libraries that will be used in creating a schematic. The
workspace file in Gateway has a file extension *.workspace. You must create or load a
workspace before creating a schematic or symbol drawing. To create a new workspace, select
FileNewWorkspace and the New Workspace dialog will appear (Figure 4-1).
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Workspace
Figure 4-3 Workspace Settings Dialog with a new row to add a library
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Workspace
There is a blank row inserted in the dialog. To name the library, click on the library with the
left mouse button and type in another name. Once the library is named, the file path to the
library folder must be specified. If symbol files in the library refer to a callback file, enter the
file name in Callback Script. To specify a path, either type the path in the Path field or press
Browse to find the path where the folder resides. When you use the Browse button, Gateway
specifies that file path as a relative path (see Figure 4-4). The path may also contain
environment variables. This is achieved by adding chevrons around the environment variable
(e.g., <S_INSTALL_ROOT>/examples/gateway/libraries/spicelib).
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Workspace
Figure 4-5 Workspace Settings Dialog with a valid library and an invalid library
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Workspace
106
Library Management
107
Library Management
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Security
4.4 Security
When opening a schematic (.schlr) or symbol file (.symbol), Gateway locks the file to
ensure that another user cannot change the file while making edits. When the file is closed,
the lock is released, and other users may edit the file.
Gateway creates a file with the same name as the schematic or symbol with the extension
".lck". This file contains lock information (e.g., User and process). This file is deleted when
the lock is released.
The drawing window title will display the following:
"[Locked by <user>]" - If another user has the lock file and is not available for edit.
"[Available]" - If the drawing is opened for read purpose but not locked by another
user.
If there is a problem with the lock file, i.e., the user has edited it and changed the format,
Gateway will display:
"[Lock file error]" - This will only occur if the lock file is badly formatted
To release the lock on a drawing so another user may open for edit, select FileRelease
Lock. To obtain a lock on an available drawing for editing purposes, select FileGet Lock.
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Chapter 5
Schematic Editing
Overview
Schematic Editing
5.1 Overview
This chapter describes the principles of schematic editing. It covers placing symbols on the
schematic, editing instance attributes, and wiring a drawing. Symbols are also covered in this
chapter. Some useful editing utilities are also described. These include automatic symbol
generation from schematics, automatic pin name generation, and other miscellaneous editing
features.
5.1.1 Workspace
A workspace must be loaded before any schematic or symbol can be opened. For more
information about workspaces, see Section 4.2 Workspace.
5.1.2 Libraries
Figure 5-1 shows the library pane of the main Symbol/Options Window. The libraries must be
flat (non-hierarchical) and this is indicated by the layout of the library pane. When a library is
selected by clicking on it, the symbols in that library are displayed in the symbol pane below.
Gateway automatically generates symbol icons to reflect the actual footprint of the symbol.
All symbols that come with Gateway or created by a designer will show in this pane. Figure
5-2 shows the large icon view for library symbols, which is the default. Figure 5-3 shows the
small icon view. Figure 5-4 shows the list view with name only. Figure 5-5 shows the list icon
view has the full symbol name and small icon in a list. Use the scrollbars to browse through
the lists of symbols. Use the slider bars to resize the areas of both windows.
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Overview
Schematic Editing
112
Overview
Schematic Editing
113
Overview
Schematic Editing
114
Overview
Schematic Editing
115
Overview
Schematic Editing
116
Overview
Schematic Editing
Figure 5-7 Selecting the schematic view from the symbol view
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Overview
Schematic Editing
118
Overview
Schematic Editing
119
Placing Symbols
Schematic Editing
120
Placing Symbols
Schematic Editing
4. Press the ESC key or click the middle mouse button to return to the Select mode. The
cursor no longer has a symbol attached to it. The vpulse symbol is placed and the
schematic should have one symbol as shown in Figure 5-10.
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Placing Symbols
Schematic Editing
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Placing Symbols
Schematic Editing
Select Rotate Clockwise or Rotate Counter-Clockwise from the Edit menu to perform
a rotation (rotate as many times as needed).
Use the Right Mouse menu and select Orientation and choose which way you want to
rotate the object.
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Placing Symbols
Schematic Editing
from the Toolbar or select Paste from the right mouse menu.
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Placing Symbols
Schematic Editing
125
Placing Symbols
Schematic Editing
126
Attribute Editing
Schematic Editing
Property pane editing is done by selecting an object on the drawing (e.g., wire, symbol) and
then editing the fields in the Property Editor pane. This is for single instance editing and is
generally a quick method to edit attributes for a single selection.
The instance attributes dialog shows a table of attributes for the selected objects and the
attribute fields with them that may be edited. Double-clicking on an object opens the instance
attribute dialog. You can edit single or multiple selected objects. To set the number of
instances to apply the edits, use the Scope combo box.
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Schematic Editing
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Schematic Editing
The top panel (Symbol Details) of this dialog shows the detailed information about the
symbol. The Symbol Details panel contains the following fields.
By default, the Instance field has a box next to it with a value assigned by Gateway. You can
always change that value to something else.
There is a combo box that selects the scope of the design that the edits will apply to. The
choices for scope are:
The Netlist Preview button is used to preview how the device statement will appear in the
netlist. The netlists that Gateway can generate are Verilog, SmartSpice, Guardian, NDL,
CDL, and Atlas. Using the preview gives you a look at how that device is written for each
netlist string. For example, Figure 5-16 shows the netlist preview for a vsin symbol.
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Schematic Editing
The lower panel (Attributes) of the dialog shows the name of the attributes for the symbol in
the Name column. The Value column shows the value for each attribute. To adjust or create a
value, click on a cell and enter in a value. The Visibility column is used to show the visibility
of these attributes on the schematic. To set the visibility, click on the cell to right of the value.
Here are the following visibility settings.
The icons showing the orange arrows reset the attributes current value back to its default
when pressed. The Reset All button in the dialog resets all attribute values back to their
defaults.
When you complete the changes, press one of the following:
Alphabetically
by Definition (in the Edit Properties dialog)
by SPICE String
To align and evenly space the attributes select EditPosition and Align AttributesFixed.
This will position, align, and evenly space the attributes to the right of the Symbol as drawn in
the Symbol View. The attributes current ordering will be maintained but with the Designator
moved to the top position.
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Schematic Editing
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Schematic Editing
Figure 5-19 shows the drawing after selecting EditAlign Attributes by Definition.
Order by Definition
Order Alphabetically
Top Right
Top Center
Top Left
Middle Right
Middle Left
Bottom Right
Bottom Center
Bottom Left
Fixed
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Schematic Editing
You can also align attributes for net names, wires, and for pins. Sometimes, you can
inadvertently move net names away from their parent wires. Instead of manually moving
them all to their original location, you can select EditSelect all and then use one of the
position actions. The result is that all attributes will become aligned to their parent objects,
regardless if the parent object is a pin, wire, or symbol instance.
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Wires
Schematic Editing
5.5 Wires
5.5.1 Wiring Rules
Terminology
Node A single wire that may or may not be connected to other wires.
Net A collection of nodes that are connected together.
Super-Net A collection of nets that are connected together by their names.
Implicit When a wire is connected to another wire by name but not physically.
Global A wire name can be global which allows all levels of the schematic to implicitly
connect to it.
Synonym An alias wire name.
Signal The primary name that will be used for netlisting purpose.
When two or more signals are joined (from the first four items in the list above), a synonym
will be created. A synonym is a net alias. Therefore, the signal of higher alphanumeric value
is retained for the physical netlist, and the other is noted as a synonym to the first net.
Naming Rules
1. Nodes can have the following properties:
Ability to be left unconnected
Net name may be always shown
.GLOBAL definition
Node may be implicitly connected
2. The netlist engine will only name super-nets that do not already have a name.
3. Gateway will validate against having implicit and global flags set without having a name.
4. A signal attached to a pin has priority over all other names in a Super-Net.
5. A node will only be named if it differs from the signal attached to a pin. The exception is
if a node was already named the same as the signal and is either implicit or global and is
then merged with the pin.
6. When changing the implicit or global flags for a node name, the changes will be applied
to all names attached to nodes on the same Super-Net.
7. The following non-alphanumeric characters are allowed in net and node names:
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Wires
Schematic Editing
exclamation (!)
left chevron (<)
right chevron (>)
hyphen (-)
plus sign (+)
forward slash (/)
asterisk (*)
high hat (^)
ampersand (&)
pound or hash symbol (#)
underscore (_)
left square bracket ([)
right square bracket (])
8. Any net or signal name that ends in an exclamation mark (!) is considered to be a globally
defined node and will behave as such for simulation. This includes single bit signals and
buses.
Graphical Rules
1. A Single Node That Is Named
When a single node is named, the name remains part of the node until it is deleted.
Double-clicking on the name can change it.
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Wires
Schematic Editing
Case B
NET2 has a higher precedence level than NET1(e.g., NET2 is implicit whereas
NET1 isnt).
Case C
NET1 is not an implicit or global signal.
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Wires
Schematic Editing
Case D
NET1 is implicit.
or select DrawWire.
2. Begin the wire by placing the cursor where the wire will start and click the left-mouse
button.
3. Move the mouse in the direction to the end point for the wire and double-click the leftmouse button to end the wire.
4. Click the right-mouse button to exit the wire mode.
To change the direction of a wire or make a vertex, click the left-mouse button while drawing
the wire and change direction with the mouse.
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Wires
Schematic Editing
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Wires
Schematic Editing
The Properties dialog for the wire has the following options:
Name: This is the name of the wire. This name will be the net name in the netlist.
Rip/Add Signal - Designates that the wire segment in context is ripped from a bus or
bundle.
Type The combo box for choosing net declarations. By default, wire type is set. The
other type declarations supprted for Verilog and Verilog-A are reg, tri, tri0, tri1, triand,
trior, trireg, supply0, supply1, wand, wire, wor, electrical, voltage, current, integer,
real, and wreal.
Assignment - Used to allow you to assign values to wires in Verilog mode. For example,
if the wire type is set to reg and the value is set to 1'b1, then the Verilog file will contain
the declaration reg a=1'b1;, assuming the name of the wire is called a.
Connection - The type of connection must be one of the following:
Normal: Normal connection without dependencies.
Implicit connection: Creates connectivity between nodes without actually wiring
them together.
Global connection: Defines the net as a global net or makes these nodes directly
available in all subcircuits. This is generally used for PWR supplies and clocks and
larger circuits. Any internal subcircuit node that has the same name as a global
node assumes that it refers to the global node. For example:
VCC NET1 0 4V
.GLOBAL VCC
The .GLOBAL statement defines the power supply VCC as a global node,
connecting it to all VCC nodes on internal subcircuits.
Rename: when an existing net is being renamed, it can be renamed as follows:
Local Net - Renames the local net that is the context of the dialog box.
Super Net - Renames the entire net, including segments that are implicit in type
(not physically connected, but electrically connected).
Width - Sets the graphical width of the wire from 1 (thinnest) to 5 (thickest).
Show name always: Displays the net name even if net names are turned off in the
customize settings or if the nets have been toggled off. When two or more wires are
drawn and labeled with the same name and the Implicit connection box is checked,
selecting ViewInfo verifies that these wires have the same net name.
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Inherited Nets
Schematic Editing
Net Properties - This is defined on symbol instances including the netInherit symbol.
Net Expressions - This is defined on wires and nets.
where the [property] is the name of the property used throughout the design and the
[value] is the assigned value at any location.
An example of a net property is:
[POWER]=[VCC!]
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Inherited Nets
Schematic Editing
which means VDDA overrides any signal wherever the [POWER] property is used on the
schematic and below.
where [property] is the name of the property that is passed in and [value] is what is actually
passed in and used.
You can setup these net expressions in two ways to accomplish the desired connectivity:
Using default signals - If the net should be given a name that is used always unless a net
property overrides it. The syntax is:
[property]:[netname]
An example of this is a net expression defined as [POWER]:[vcc]. This will use vcc
always unless the [POWER] property is defined above. If defined, vcc will be overridden.
Using default connections - If no specific node name will be used for default. Instead, the
connection as the circuit is wired should be used as a name. The syntax is:
[property]:[%]
In this case, % means to use the netname of the given wire where the net expression
resides unless a net property overrides it.
An example of this is shown in Figure 5-26 where a net property [PWR]:[%] exists on a wire.
If the [PWR] property exists above, this net will use the value defined for it. If its not defined
above, Gateway resorts to the name of the physical wire. In this case, the wire is connected to
the VDD pin. Therefore, VDD is used.
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Inherited Nets
Schematic Editing
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Inherited Nets
Schematic Editing
This makes VDDA overrides the [POWER] property on the cmos circuit below. Instead of using
VDD, all three instances use VDDA.
For this case, the net property at the instance has a higher precedence than the netInherit
symbol. The result is that X1 and X2 use VDDA for [POWER], but X3 uses VDD2 for [POWER].
Examples illustrating inherited net use are found in the Gateway examples directory that is
included with the software. The three example directories all begin with the string netInh.
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Inherited Nets
Schematic Editing
Figure 5-28 X3 POWER property overrides the netInherit symbol for the X3 instance
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Buses
Schematic Editing
5.7 Buses
5.7.1 Bus Naming Conventions
There are multiple ways to define buses and wire bundles in Gateway. The bus naming
supports the following syntax styles:
Separator
Square Brackets
Angle Brackets
Multiplier
Parentheses
Prefix Repeat operator
Separator
The separator character is a comma (,) and allows the ability to specify multiple signals on the
same wire.
Example
Bus Name
A, B
A, B
ENABLE, S1, S2
ENABLE, S1, S2
A<0>
A<0>
B<0:2>
BUSA<3:0>
SCAN<4,0,1>
Bus ranges also support step operators that are specified by adding a second colon (:)
character.
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Buses
Schematic Editing
Example
Bus Name
A<4:0:2>
B<0:6:2>
SCAN<0:3:2>
SCAN<0>, SCAN<2>
SCAN<0:3:1>
Multiplier
The multiplier operator gives the ability to repeat a name or bit.
Example
Bus Name
A*5
A, A, A, A, A
B<0, 1, 2*2>
Parentheses
Parentheses, (), allow you to group different signalsand then use an operator on them. For
example, the Prefix Repeat operator or Multiplier.
Example
Bus Name
B<(0,2)*2>
<*5>(A, B), C
A, B, A, B, A, B, A, B, A, B, C
<*3>A
A, A ,A
<*5>(A, B)
A, B, A, B, A, B, A, B, A, B
<*2>(DATA_IN, <*2>(A,B)), C
DATA_IN, A, B, A, B, DATA_IN, A, B, A, B, C
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Buses
Schematic Editing
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Buses
Schematic Editing
Figure 5-30 shows the completed bus with all ripped component segments.
The ORDER property defines the bit mapping order from the signals attached to the origin
pin to the signals attached to the destination pin. The origin pin is always pin A, and the
destination pin is always pin B. The PRECEDENCE property defines which net is given the
priority name in the netlist. The three choices are
A - Forces the net on the origin side to be the name in the netlist.
B - Forces the net on the destination side to be the name in the netlist.
PRIMARY - Resolves the supernet to the primary signal name that is determined by the
following list of importance, from highest to lowest:
width (2 bit width higher priority than single bit wide)
pins (user-defined)
global nets
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Buses
Schematic Editing
implicit nets
pins (system generated)
alpha-numeric nets (user-defined)
alpha-numeric nets (system-generated)
Figure 5-31 shows a four bit bus x aliased to a four bit bus y. That is, the four bits in
ascending order are aliased to the four bits on the right in ascending order.
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Buses
Schematic Editing
Figure 5-32 shows the setup in a sample circuit that yields the following netlist:
R<0> X<0> GND 1k
R<1> X<1> GND 1k
R<2> X<2> GND 1k
R<3> X<3> GND 1k
R<4> X<0> GND 2k
R<5> X<1> GND 2k
R<6> X<2> GND 2k
R<7> X<3> GND 2k
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Buses
Schematic Editing
Figure 5-33 shows the circuit with the PRECEDENCE changed to the right side. This forces the
netlist to write in terms of the right-hand side bus, or in this case: y<0:3>.
Figure 5-33 PRECEDENCE set to the right and bit order retained
That change produces the following netlist:
R<0> Y<0> GND 1k
R<1> Y<1> GND 1k
R<2> Y<2> GND 1k
R<3> Y<3> GND 1k
R<4> Y<0> GND 2k
R<5> Y<1> GND 2k
R<6> Y<2> GND 2k
R<7> Y<3> GND 2k
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Buses
Schematic Editing
Figure 5-34 shows the circuit where the ORDER has changed to reverse the bit order from left
to right, and still shows the PRECEDENCE for the netlist as the right side.
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Buses
Schematic Editing
Figure 5-35 shows the circuit with the PRECEDENCE changed to the side A.
If you set the PREDECENCE to Primary instead of A or B, then Gateway uses the signal
derived from the wire merging that is described in the beginning of this section.
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Buses
Schematic Editing
Figure 5-37 One Flip Flop Instance naming four iterated instances
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Symbols
Schematic Editing
5.8 Symbols
Gateway symbols are files with a *.symbol file extension.
Symbols may or may not have a PREFIX attribute. The PREFIX attribute of a symbol
designates the type of symbol it will represent in the target simulator. The PATH attribute of a
symbol designates the instance name of a particular instance. Together, the PREFIX and PATH
form a reference designator (also known as the instance designator).
An example of a reference designator for a MOSFET transistor would be M5, representing
the fifth instance of type MOSFET. In this case, the PREFIX for the symbol is set to M, and
the PATH is numbered automatically by Gateway as devices are placed.
An example of a reference designator for a digital symbol would be I2, where the PREFIX is
I, and the 2 represents the second instance on the drawing.
The $default library symbols represent ports, pins, connection symbols, power rails, grounds,
and other special symbols that add information to schematics. The spicelib library symbols
contain the active and passive devices that are native to SPICE. The digilib library of symbols
contains primitive digital devices for capturing on schematics.
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Symbols
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Normal: A pin with a name and no signal information associated with it.
Unconnected_OK: Allows the pin to be unconnected (unwired). If the SIGNAME text box
is empty, Gateway will ignore the pin for the netlist. If the SIGNAME box has a value and
the pin is not wired, Gateway will use that SIGNAME value for the node name at that pin. If
the pin is wired, the signal name of the wire will become the node name at that pin for
netlisting purposes.
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Symbols
Schematic Editing
Implicit: Assigns an implicit connection from the pin to a node name elsewhere on the
schematic. The SIGNAME can be VCC, GND, or any node that exists in the simulation. Its
visibility will always be on. If the pin is wired, the implicit SIGNAME will override the
existing wire name due to procedure.
Figure 5-40 describes all possible cases. In addition to the other pin attributes, there are pin
direction and vlg discipline attributes. The pin direction assigns directional behavior to the
pins as input, output, bidirectional, or undefined. By default, the pins are input type. If the pin
types in the symbol do not match pin types for the schematic view of the same cell, Gateway
will issue a warning at drawing check and netlist times. For simulators where pin direction
does matter (i.e., Verilog), make sure you assign the correct direction attribute for the pins.
The Vlg discipline field is used for assigning VerilogAMS disciplines to a node or a pin. This
is optional.
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Symbols
Schematic Editing
To add, delete, or modify symbol attributes, click EditProperties... when the symbol file is
open (Figure 5-41).
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Symbols
Schematic Editing
The Properties dialog for the Symbol file has five fields at the top:
Designator Prefix - Specifies the prefix of the symbol which represents its type for the
simulator
Category - This can be used optionally to assign the symbol to a category of symbols,
such as MOS, for example. This field is then used in the symbol pane in the editor for
filtering
Init Callback- Executes the callback when the symbol or instance properties dialog is
initialized (populated).
Value Changed Callback - Executes the callback when a value changes on the dialog.
Done Callback - Executes the callback when the dialog/property is finished by pressing
OK on the dialog.
To add an attribute, click the Add button and then a new row in the dialog will appear.
Navigate through the dialog with the tab or arrow keys. Click in a cell to modify its contents.
As attributes are added, they can be ordered in the dialog. This order from top to bottom will
be the order the attributes are shown in the instance dialogs from top to bottom. Usually for
SPICE primitives, they will be in the order the attributes appear in the SPICE string. In the
row of navigation buttons on the right side of the dialog, there are options to move attributes
one up or down at a time, or move to the top or bottom of the list, and also one to reverse the
current order.
The columns in this dialog are defined as follows:
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Symbols
Schematic Editing
Default Attributes
The following is the definition of a default attribute:
Attributes in the symbol instance that aren't present in the symbol definition will remain.
The attribute, however, can be deleted using the Symbol Instance Properties dialog.
Attributes in the symbol definition that aren't present in the symbol instance are added.
Fixed Attributes in the symbol definition will overwrite matching attributes in the symbol
instance.
Non-fixed attributes in the symbol instance will overwrite matching non-fixed attributes
of the symbol definition.
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Symbols
Schematic Editing
GUARDIAN - Guardian (LVS) template string (used for Layout vs. Schematic comparison).
GUARDIAN_INFO_TEMPLATE - Guardian extra information string, added to the end of the
control file.
NDL - NDL (Netlist Driven Layout) template string (used for generating initial placement
for Expert).
NDL_INFO_TEMPLATE - NDL extra information string, which is added to the end of the
control file.
ATLAS - Atlas template string (used for creating Atlas MixedMode simulations).
ATLAS_INFO_TEMPLATE - Atlas extra information string, added to the end of the control
file.
VERILOG - Verilog template string (used for Silos simulator).
VERILOG_INFO_TEMPLATE - Verilog extra information string, added to the end of the
control file.
CDL - Circuit Description Language format string.
Note: Symbols having blank Guardian or NDL strings will use Smart_Spice strings in their place when a Guardian or NDL
netlist is created.
To edit these strings, assign characters that denote how the string will parse variables and
arguments to create the string. There is a legend that describes these metatokens that can be
seen by clicking the Show Legend box on any string editor dialog as shown in Figure 5-43.
There are two mechanisms for specifying these strings as shown in Figure 5-43. The function
mechanism is the first method, since the functions are named to represent what role they play
in the string definitions. The second mechanism is the metatoken approach.
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Symbols
Schematic Editing
GND
GND
NMOSTUB
W='(10)*1E-6'
L='((4)*1E-6)'
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Symbols
Schematic Editing
163
Symbols
Schematic Editing
164
Symbols
Schematic Editing
165
Symbols
Schematic Editing
No definition
Embedded Definition
Attached Definition
Generated Definition (from schematic)
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Symbols
Schematic Editing
Each symbol can use only one definition per simulator string. An example of this is a symbol
that may behave as a primitive for SPICE, but for Verilog it can behave as a behavioral
module coming from an attached file. In the case of this symbol, all instances of the symbol
must behave the same way. Changing the symbol definition for a symbol propagates the
change to all instances of the symbol on all schematics.
No Definition
When this option is chosen, there is no underlying or attached circuit that is used. This is the
case for special symbols (e.g., many of the symbols found in the $default) and the analog
primitive symbols, whose definitions are derived only from the SPICE string.
Embedded Definition
An embedded definition is the case where the definition entered and stored in the symbol file.
This can be typed in or copied and pasted in. The embedded definition means is that there are
no external file path dependencies. The definitions can be edited by opening the symbol and
making changes, and saving.
Figure 5-49 shows an ideal opamp symbol and its embedded file definition. After opening the
symbol for edit, click the SmartSpice button and click the Definition tab. Then, choose
Embedded Definition from the pulldown menu. The definition of the ideal opamp subcircuit
is entered in, saved, and becomes the definition now for SmartSpice simulations.
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Symbols
Schematic Editing
After completing the definition, you can automatically format the netlist instance string so
that the string and definition are compatible for the netlist and simulation. To do this, click the
button. After that is pressed, the dialog now looks like Figure
Instance tab and press the
5-50 and the instance string and definition are complete. Press OK on the string editor dialog,
then press OK again on the Symbol Properties dialog, and then save the file.
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Symbols
Schematic Editing
Figure 5-51 shows an embedded file definition that uses a Verilog module for the Verilog
string of a symbol. Then, clicking the Instance tab on the dialog and pressing the Generate
String from Definition button to generate the instance string results in Figure 5-52.
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Symbols
Schematic Editing
170
Symbols
Schematic Editing
Attached Definition
The Attached Definition option is used to attach a subcircuit definition or module definition
to the symbol by using a separate file. The file may have one or more subcircuits or module
definitions included in it. But the Instance tab on the dialog is used to isolate the specific
subcircuit or module definition to be used. The attached definition method is the only method
where encrypted definitions may be used.
Attached Files Containing Single Definition
To use the attached definition, open a symbol file or create one new. Then, open the symbol
properties dialog and then click one of the simulator strings. When the next dialog opens,
select the Definition tab. Then, choose Attached File from the pulldown menu and click the
Add button (plus sign). In the File box, click the Browse button and browse to the file. Then,
click OK and the dialog will look like Figure 5-53.
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Symbols
Schematic Editing
To use this method, the $$ metatoken is used to denote a direct reference to the library. In
this case, when you use $$libraryname, Gateway resolves the paths automatically and
ensures the files are available for netlist and simulation. In this example, there is a library
named design and a file named primitives that has a subcircuit definition for the 2-input
nand subcircuit.
There are two other fields in the Attached File Definition: Type and Entryname. The Type
field is for setting what type of file is added here. Choose the .INCLUDE option for only
including a file. For attaching SPICE libraries, use the .LIB option and then type in the
library entryname in the Entryname field. For attaching Verilog-A files, use the .VERILOG
option. For Verilog string types, there are no Type and Entryname fields in the dialog.
Regardless of which method was used, the instance string needs to be created to complete the
symbol. To do this, click the Instance tab and press the Generate String from Definition
button to create the netlist string. The result is Figure 5-54.
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Symbols
Schematic Editing
It is also common that there can be multiple subcircuit or module definitions residing in the
same file. The procedure to attach the file is similar to the one previously described, except
there is an extra step involving choosing the specific subcircuit or module to be used. In this
method, when generating the simulator string, there is a pulldown menu for choosing the
specific subcircuit or module. Figure 5-55 shows the dialog for choosing a module definition
from the file primitives.v that contains several dozen module definitions. Once the correct
module is chosen, Gateway knows how to format the netlist string.
Multiple files may be attached for dependencies. If more than one attached file contains a
subcircuit or module definition with the same name, Gateway always will use the first file
shown in the list. Use the up and down arrow buttons on the dialog to move files up or down
in the list.
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Symbols
Schematic Editing
174
Symbols
Schematic Editing
Figure 5-57 shows the Instance tab for the inverter symbol with the Generate String button
grayed out for this reason.
Figure 5-57 Generated View that does not need an Instance String
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Symbols
Schematic Editing
176
Symbols
Schematic Editing
Figure 5-59 Properties Dialog (for Symbol File) shows width and length attributes for n-type and p-type
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Symbols
Schematic Editing
178
Symbols
Schematic Editing
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Symbols
Schematic Editing
Defparams
The defparam statement must be used when passing instance specific parameter results. The
syntax of the defparam statement is $(defparam(n, n1)), where n is the name of the
attribute whose result is placed in the defparam and n1 is an optional parameter to the
statement in cases where the result needs a different name.
For instance, $(defparam(r, res)) will create .defparam X1.R1.res = 10k in SPICE,
assuming the instance level is X1 and the instance name is R1.
Other examples of using the .defparam statement for SPICE netlists are
.defparam x1.x4.wn=10u
.defparam l=5u
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Schematic Editing
Begin at This is the first number of the renaming sequence. For example, to start
renaming nets with net1, set this field to 1.
Increment by This the number added to the number in the Begin at field or the number
the sequence will increment for each instance. For example, if you set this field to 1 for
the example above, the next items in sequence will be renamed as net2, net3, and so on.
Direction Choosing X renames the objects in a horizontal direction. Choosing Y
renames the objects in a vertical direction.
Assign from Choose from Top left, Top right, Bottom left, or Bottom right to choose
the starting point of the selection for the renaming sequence.
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Schematic Editing
182
Schematic Editing
183
Schematic Editing
184
Creating Arrays
Schematic Editing
185
Creating Arrays
Schematic Editing
186
Creating Arrays
Schematic Editing
To create a single column of resistors, set the dialog as shown in Figure 5-70.
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Creating Arrays
Schematic Editing
To create an array of 55 resistor devices, set the dialog as shown in Figure 5-72. The
resulting schematic will then look like Figure 5-73.
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Creating Arrays
Schematic Editing
The Instance Name Order section of the dialog controls how the instances will be named.
The default is the X direction beginning from the top left of the array. Figure 5-73 shows this
as the instances begin at R1 on the top left and progress in the X direction.
The X Offset and Y Offset fields tell Gateway how much to separate the elements in the
array (in pixels) in either dimension. A 55 array is shown in Figure 5-74 where the offset
distances for both X and Y are doubled from 60 to 120.
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Creating Arrays
Schematic Editing
Figure 5-75 shows how the array will be named if the Instance Name Order Direction was
set to Y and beginning at the top left.
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Generating Symbols
Schematic Editing
). To rotate text orientation on the pin, select the pin(s) and press the
button.
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Generating Symbols
Schematic Editing
The Place Pins option is for setting the pin names to be inside or outside of the symbol
footprint. The Place Title option specifies where the title (if applicable) of the symbol should
be placed. By default, it is in the center of the symbol. The Place PATH option specifies
where the instance designator is to be placed for the symbol. By default, it is located on the
bottom-right of the footprint.
There are two options that are related to the calculation of how the symbol is automatically
sized. These options are:
Include Title in dimension calculation With this option ON, the symbol having long
names will scale to be large enough to encompass the name of the symbol within the
footprint. With the option OFF, the symbol names can overlap the footprint.
Include Pin names in dimension calculation With this option ON, pin names are
taken into consideration in calculating the symbol dimensions to prevent text from
overlapping on the symbol.
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Schematic Editing
193
Change Symbol
Schematic Editing
The Change Symbol dialog is designed to quickly and efficiently process the changes either
globally or on a per instance level. Follow the sequence of sections in this dialog from top to
bottom.
1. Select to merge or replace the attributes for the targeted instances.
2. Decide which instances are going to be affected by the Selection Filter. The Selection
Filter also specifies the scope of the target instances in terms of the design scope.
3. Use the Existing Symbol Filter to show the specifics of the symbol and libraries of the
selected instances.
4. Use the New Symbol Filter to choose the new symbols and from what library they are to
come from.
This choice of merging or replacing is important. Merging them will retain attribute values
from the original symbols if those attributes exist in the new symbols. Replacing instances is
the equivalent of actually deleting and re-instantiating the instances. Therefore, nothing from
the original instances is retained.
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Change Symbol
Schematic Editing
195
Change Symbol
Schematic Editing
Entire Simulation - Changes the desired symbol instance(s) on the current level, down the
hierarchies, and the parent cells. This is for schematics that are open and the active schematic
is other than the top cell.
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Schematic Editing
197
Schematic Editing
2. Type in the text and press OK. The text will now be floating with the cursor.
3. Click the left mouse button to place it at the desired location.
Lines
Circles
Semi-circles
Quarter-circles
Arc by 3 points
Use the left mouse button to begin drawing. Then, click the left mouse button again to finish.
Lines can be drawn vertically, horizontally, or diagonally. Circles and arcs are drawn using
the radius of the circle. Once you place an object, double-click on the object to edit the size
and thickness of the object.
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Schematic Editing
Figure 5-82 shows the dialog for line properties of a line drawn on a schematic. Figure 5-83
shows the dialog for changing the properties of a circle object.
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Schematic Editing
Top
Right
Left
Bottom
Horizontal Center
Vertical Center
Figure 5-85 shows the space evenly icons Horizontal spacing on the left and Vertical spacing
on the right.
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Schematic Editing
For schematics that are multisheet, you can add sheet frames to all sheets at once by selecting
ToolsFrameAdd to All Sheets. Sheet Frames may be deleted by selecting
ToolsFrameDelete from This Sheet or ToolsFrameDelete From All Sheets.
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Find Dialog
Schematic Editing
5.16.1 Example
To find a specific resistor (R5) on a schematic, enter R5 into the Find What field and press
the Find Next button.. The R5 instance will be highlighed and selected, and the Properties
pane will reflect the selection.
To find all resistors, type R in the Find What field and press Find Next. Each time you press
Find Next, Gateway will highlight the next resistor found, and the context will be shown in
the Properties pane.
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File Details
Schematic Editing
203
File Details
Schematic Editing
204
Chapter 6
Viewing and Navigating Designs
Description
Zoom In
Zoom Out
Zoom Full
Zoom to Area
Ascend
Descend
Symbol
Schematic
Net NamesAll
Net NamesUnique
206
Grid
Info
Capture/Simulation
Full Screen
Refresh
Re-center
Clear
Windows
Toolbars
207
208
209
210
211
Goto Instance Highlights and centers the selected instance on the active drawing.
Goto Definition Opens the definition of the selected instance in its active view
(schematic definition, embedded definition, or file definition).
Goto Symbol Opens the selected symbol for editing.
Properties Opens the instance attributes dialog for the selected instance.
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213
214
215
216
All Shows all names for all named segments of the net.
Unique Shows the main name of the net and hides the other segments of the same
name.
None Toggles off all net names unless the "Show Name Always" flag is set for the
specific net.
Show Generated Names Toggles on or off the visibility of net names generated by
Gateway.
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Chapter 7
Design Flow
Overview
Design Flow
7.1 Overview
Once the schematic has been defined and captured, its ready for a design flow. Figure 7-1
shows the design flow in Gateway. To perform a design flow, begin with the schematic
capture and proceed as follows:
1. Choose a simulator and a domain. This can be done later but choosing at this point in the
flow means that all instance views will be set as defined at the time they are placed on the
schematic.
2. Check the schematic design.
3. Review any errors and make changes to the schematic. If there are errors creating the
netlist, review the errors and correct them. If there are no errors, go to step 4.
4. Generate and view the netlist.
5. Create a simulation profile. A control file is then created for the active simulator
preference. Specify any analysis, model information, options, or additional information
needed in the control file.
6. Place markers on the schematic for saving vectors (for the SmartSpice family of
simulators only).
7. Create and view the input file. This is the file that assembles the netlist, control file, and
associated files for simulation.
8. Run the simulation.
9. View the waveforms in the waveform viewer, and post process the data.
10. Cross probe between waveform viewer and schematic (for the SmartSpice family of
simulators only).
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Checking a Schematic
Design Flow
applicable.
2. Check all levels
220
Checking a Schematic
Design Flow
221
Checking a Schematic
Design Flow
222
Checking a Schematic
Design Flow
223
Netlisting
Design Flow
7.3 Netlisting
A netlist is a file created by Gateway containing connectivity information between symbols,
signals, wires, and pins of a schematic. The types of netlists Gateway can generate are as
follows:
SmartSpice: The SmartSpice netlist is the simulation netlist for running the SmartSpice
analog circuit simulator. As an example, if the schematic design is named RSFF.schlr,
then the SmartSpice netlist is RSFF.net.
SmartSpice 200: The SmartSpice 200 netlist is for simulating using SmartSpice 200.
SmartSpice RF: The SmartSpice RF netlist is used for simulation with SmartSpice RF.
Silos: The Silos netlist is a Verilog netlist and used for running Verilog simulations in
Silos.
HSPICE: The HSPICE netlist format is used for running analog designs in HSPICE.
Atlas: The Atlas netlist is generated for running TCAD Atlas MixedMode simulations.
NDL: The NDL (Netlist Driven Layout) is the netlist that has directives for higher
productivity in pre-layout.
Guardian: The Guardian netlist reflects the physical layout for LVS. Using the RSFF
example, the Guardian netlist is RSFF_lvs.net.
CDL: The CDL netlist is the Cadence CDL netlist option.
Figure 7-7 shows an example of a SPICE netlist after selecting SimulationCreate Netlist
when the simulator is set to SmartSpice. Figure 7-8 shows an example of a Verilog netlist of
a design when the simulator is set to Silos.
By default, netlists are created in read-only mode to synchronize to the schematic drawing.
This ensures that the schematic and netlist are equivalent at simulation time and prevents
inadvertent discrepancies between the two.
To edit the netlist files for use outside the Gateway environment, go to the Preferences and
check the Manual editing of .net files option in the applicable tab for each netlist type.
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Netlisting
Design Flow
225
Netlisting
Design Flow
226
Netlisting
Design Flow
227
Netlisting
Design Flow
228
Netlisting
Design Flow
Example
Assume there is a hierarchical drawing for a phase locked loop. One of the blocks on the
drawing is a divide-by-N counter. The counter clock is made up of JK flip flops. This flip flop
subcircuit may be useful to include in a .SUBCKT netlist form for input decks running outside
of Gateway (i.e., Batch or Interactive Mode, SmartSpice). If used, the top level D_PLL circuit
is now opened. Then, use hierarchy browser to open the JK_FF schematic you wish and then
open the Create Specific Netlist dialog. Check the Make .SUBCKT box and press the Netlist
button. The result is shown in Figure 7-11. The JK_FF subcircuit will be in .SUBCKT form.
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Control Files
Design Flow
230
Control Files
Design Flow
analyses to simulate
models
libraries
parameters
parametric and corner analysis
statements for calculating measurements
SPICE options (including RF)
include files
statements for saving specific vectors
If the default text editor (Sedit) is used, then there are toolbars (for example Figure 7-14) and
dialogs that aid in building statements for the SmartSpice family of simulators. Examples of
these can be seen in Figures 7-15, 7-16, and 7-17. From these, the following SPICE analysis
statements can be generated:
Transient
DC
231
Control Files
Design Flow
AC
Noise
Distortion
Transfer Function
Network
OP (Operating Point)
PZ (Pole-Zero)
.MODIF
Fourier
ENVELOPE analysis
HAC (Periodic Steady-State AC Analysis)
HARMONIC (Periodic Steady-State Analysis)
HNET (Periodic Steady-State Two-Port Analysis)
HNOISE (Periodic Steady-State Noise Analysis)
HOSCIL (Periodic Steady-State Oscillator Analysis
HTF (Periodic Steady-State Transfer Function Analysis)
SPAC (Quasi-Periodic Steady-State AC Analysis)
SPECTRAL (Quasi-Periodic Steady-State Analysis)
SPNET (Quasi-Periodic Steady-State Two-Port Analysis)
SPNOISE (Quasi-Periodic Steady-State Noise Analysis)
SPTF (Quasi-Periodic Steady-State TF Analysis)
PSS-Shooting (Periodic Steady-State Oscillator Analysis by Shooting Method)
PSS-HB (Periodic Steady-State Oscillator Analysis by Harmonic Balance Method)
PHASENOISE analysis
For more information about the control card statements, see SmartSpice User's manual Vol. 1.
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Control Files
Design Flow
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Control Files
Design Flow
234
Control Files
Design Flow
235
Control Files
Design Flow
236
Control Files
Design Flow
237
Design Flow
238
Design Flow
239
Design Flow
. To resume a
simulation, press
again. For more information about the simulation, see Chapter 8
Simulation and Post-Processing,.
240
Chapter 8
Simulation and Post-Processing
Pre-Simulation
8.1 Pre-Simulation
The simulation menu in Gateway consists of actions that cover the entire flow. Figure 8-1
shows the Simulation Toolbar. It begins with the drawing checks that were covered in Section
7.2 Checking a Schematic along with the creation of the netlist, control, and input files. The
next step in the progression of the flow is the simulation itself. Gateway is integrated with the
following list of simulators:
Silvaco SmartSpice
Silvaco SmartSpice 200
Silvaco SmartSpice RF
Silvaco Silos
Silvaco Atlas TCAD MixedMode
Synopsys HSPICE
Description
Drawing checks (this level, down hierarchy, entire simulation) as covered in Section
7.2 Checking a Schematic.
Generates and displays the netlist.
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Pre-Simulation
243
Analog Simulation
244
Analog Simulation
The Analyses pane shows the contents of the control file, if one exists. If one does not exist
yet (for a new schematic), the pane will reflect that there are no control statements or
analyses. Figure 8-3 shows the control file contents for the current mirror example schematic.
This pane filters out all the comment lines to condense the amount of data shown and only
displays what is live or active for the simulation.
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Analog Simulation
Analysis Type: Sets the analysis that you want to plot. If more than one, select All
Analyses.
Plot to:
Create a New Chart Creates new chart and plots data there.
Replace Existing Chart Replaces data in existing chart with new data after each
run.
Add to Existing Chart Adds to data in existing chart after each run.
Replace Existing Simulation Replaces old simulation data after each run for all
analyses in the deck.
Overlay on Existing Simulation Overlays new simulation data on top of older
data for all analyses in the deck.
Existing Chart: Allows you to select the chart to replace or add the traces onto. It queries
SmartView for all the available charts. This option is enabled if Plot To is set to Replace
the Existing Chart or Add to the Existing Chart.
Existing Simulation: Allows you to select the simulation to replace or overlay the new
simulations traces onto. It queries SmartView for all the available simulations. If a
simulation contains parametrics (i.e., multiple analyses) and plotted on different charts in
SmartView, the option allows you to select which one of the charts per analysis type will
be replaced/overlayed. This option is enabled if Plot To is set to Replace the Existing
Simulation or Overlay on Existing Simulation
Chart Layout: Chooses the layout display of the charts (e.g., vertical or horizontal).
Plot Parametric to Same Chart: Specifies whether to plot all the analyses of the same
type for a parametric simulation (e.g., .ALTER, .TEMP, .MODIF, .ST) to the same chart.
246
Analog Simulation
is for marking
is
for measuring the difference in voltages or currents. The cursor will have a plus sign next to it
when you drop the first marker (Figure 8-7). The cursor will have a minus sign next to it when
you drop the second marker (Figure 8-8). The resulting marker will look like Figure 8-9,
which shows the difference between the first and last marker. You can also select these
markers using the Post-Process menu in Gateway.
247
Analog Simulation
248
Analog Simulation
This Cross Probe tab shows the information about each marker, including the name, the
schematic drawing that the marker resides on, the sheet number, and whether the vector
should be plotted or marched. If there is a check in the checkbox in the Save column, this
indicates that the vector will be saved by the simulation into raw data for postprocessing. If a
vector is checked in the Plot column, it will be plotted following the completion of the run. If
the checkbox in the March column is checked, the vector will be marched or plotted
progressively in real time during the simulation.
The four checkboxes in the Save area are for saving groups of data. They are as follows:
If you check any of these, these vectors will be saved but not plotted. This means that after the
simulation is complete, these vectors will be available in SmartViews Data Browser window
for selecting and plotting. The only vectors that will be plotted from the schematic are the
ones that are listed in the Cross Probe pane. Otherwise, anything that is saved can be plotted
after the simulation in SmartView.
The crb file (crossprobe markers file) contains the crossprobes that were marked for the
simulation. This includes all markers on subcircuits and all marker types. In other words, db,
phase, diff and normal. The crb file is stored at the same location as the top level schematic of
the simulation. For example, if the top level schematic was named ex2.schlr and a marker
is placed on its subcircuit then a crb file named ex2.crb will contain the marker.
Note: Cross-probing and Save checkboxes only apply to the SmartSpice family of simulators.
249
Analog Simulation
again. Press Hide to hide the RunSmartSpice license. To resume a simulation, press
Time Dialog. The Run-Time Dialog will disappear but the simulation will continue.
Alternatively, you can select these actions from the Simulation menu in Gateway.
The current schematic will be netlisted to include the latest changes in the SPICE deck.
A list of voltages and currents to be saved by SmartSpice will be incorporated into the
SPICE deck along with the user-defined control cards.
SmartSpice will be started if its not already running in the system. The SPICE deck will
be loaded into SmartSpice once its running. At this point, any control card or netlist
errors in the deck will be detected by SmartSpice and will appear in the Session Window.
Figure 8-12 shows the schematic marked and ready for simulation. The only things that
should plotted are the voltages for NET5 and NET6 as shown. After running the simulation,
Figure 8-13 shows those voltages for each analysis. When the simulation completes, the
and see the output (see
output file will be ready for viewing. To view this file, click
Figure 8-14). You can also click the Output tab to see the SmartSpice output. If there are fatal
errors from SmartSpice and a separate error file is created, this file can be viewed by selecting
SimulationView .ERR File.
250
Analog Simulation
251
Analog Simulation
252
Analog Simulation
253
Analog Simulation
Current - DC bias data exists and is up-to-date. No schematics in the simulation have
been modified since the last simulation run or since Gateway was launched.
Stale DC bias data exists but is out-of date. At least one drawing in the simulation has
been modified since the last simulation run. DC bias markers may still be displayed. The
Stale status indicates the values from the previous run.
If a simulation has not been run, the title bar will not show any status.
254
Analog Simulation
255
Analog Simulation
256
Analog Simulation
Also, clicking any pin will drop a current marker with the DCOP current displayed on the
marker. Additionally in this mode, rolling the mouse over a pin or wire will highlight the
object and show the DCOP voltage or current in a tooltip (see Figure 8-23).
For transient simulations, transient data can be seen for any node or device current as long as
they were specified to be saved before running the simulation. To show these values on the
schematic, turn on the voltage or current markers by pressing the V or I icons, and then select
ViewWindowsBias Display. The window pane in Figure 8-19 is displayed.
257
Analog Simulation
258
Analog Simulation
259
Analog Simulation
In Figure 8-24, the Simulator is set to SmartSpice. The first icon in the series of three icons is
the simulator icon. The second icon is the waveform viewer icon. In this case, SmartView is
shown as the Waveform Viewer chosen for this session. The third icon is for the layout editor,
and in this session it is set to Expert. Figure 8-24 shows all three icons are lighted which
indicate that Gateway is connected to all three applications. If one of them is disconnected or
closed, the icon will turn gray. Figure 8-25 shows Gateway disconnected from Expert.
260
Analog Simulation
261
Analog Simulation
Figure 8-28 Properties Dialog (for the Symbol Instance) with Parameters Selected
262
Analog Simulation
Symbols can be setup to show their simulation device parameters simulations on all designs
where they are used. To do that, first open the symbol for edit. Then, open the symbol
properties and click on the Device Parameters tab. Click the Add button to add parameters
to the list, and enter their names. Figure 8-30 shows the parameters region and vth
being added to the PMOS symbol. After the symbol is saved, all designs using the PMOS
symbol will show values for the region of operation and the vth on the schematics following
the simulations.
Figure 8-30 region and vth parameters added to the PMOS Symbol
263
Analog Simulation
8.2.7 Post-Processing
The Cross Probe Toolbar (Figure 8-31) shows the icons that post-process the data.
. To
delete markers from the stack in the Cross Probe pane, click
and all checked markers
will be deleted. All post processing and plotting uses the settings stored in the Plot Options
pane. To launch SmartView, click on
select PostprocessReset Markers.
264
Digital Simulation
265
Digital Simulation
266
Digital Simulation
Generate the Verilog netlist shown in Figure 8-35 by selecting SimulationCreate Netlist.
Then, view the Verilog control file shown in Figure 8-36 by selecting SimulationEdit
Control File. You can also view the input file shown in Figure 8-37 by selecting
SimulationView Input File.
267
Digital Simulation
268
Digital Simulation
269
Digital Simulation
Figure 8-39 SmartView showing Digital Vectors from the Verilog simulation
270
Chapter 9
EDIF
Overview
EDIF
9.1 Overview
EDIF (Electronic Design Interchange Format) is an ANSI/EIA (American National Standard
Institute/Electronic Industries Association) standard file format that is used to transfer data
from one CAD/CAE system to another. In Gateway, the EDIF file format transfers schematic
drawings from other tool vendor schematics into Gateway. Gateway only supports importing
and exporting of EDIF Version 2 0 0 files.
272
EDIF
General Options
Fix case sensitivity conflicts Resolves conflicts for library, cell, and net names that
have duplicate alphanumeric strings in the EDIF file by naming them uniquely.
Discard invalid characters in node names Strips out node name characters that are
invalid for SmartSpice.
Verbose output Produces extra information during import that may be useful in
diagnosing import errors. If an import fails for some reason, you may want to turn on
Verbose output and try importing again. The verbose messages might help to locate the
problem.
Filter attributes Ignores specified attribute names during the EDIF import and prevent
them from importing. To specify these attributes, click the Edit button on the dialog.
273
EDIF
Add default Attributes Adds default values to attributes in symbol files that are
importing into Gateway. To add values to the list or to edit the list, click the Edit button
on the dialog.
Cadence Options
Add Viewdraw pins Adds pins to schematic files where necessary for the purpose of
hierarchical connectivity and netlisting.
Retain Viewdraw snap spacing - Converts Viewdraw schematics/symbols from the
imported file to the Gateway schematic grid.
OrCAD Options
Retain OrCAD snap spacing - Converts MicroSIM PSPICE and OrCAD schematics/
symbols from the imported file to the Gateway schematic grid.
274
EDIF
275
EDIF
276
EDIF
Parsing complete
Beginning phase 2...
Phase 2 complete
Beginning phase 3...
File uses EDIF Version 2 0 0 Level 0
Time Stamp 3/31/2004 12:24:13 PM UTC
Author 'Cadence Design Systems'
Data Origin 'carmel'
Program 'edifout'
(cds12107) $'
Version
't
version
5.0.0
09/26/2003
18:20
to
file
277
EDIF
to
file
to
file
to
file
278
EDIF
to
file
If the file import is successful, the dialog in Figure 9-4 will show at the end of the import.
279
EDIF
280
EDIF
Load a workspace.
Import the EDIF file with these options as shown in Figure 9-6.
Press Import.
Press OK on successful import notification dialog.
Open the imported schematic. The imported drawing now looks like Figure 9-7.
281
EDIF
282
6.
7.
8.
9.
EDIF
283
EDIF
Figure 9-8 Imported Schematic with Netlist Preview and Empty SmartSpice String
284
EDIF
Figure 9-9 Resistor symbols before edit: (Left: spicelib and Right: analoglib)
285
10.
11.
12.
13.
14.
EDIF
Figure 9-10 Resistor symbols after edit: (Left: spicelib and Right: analoglib)
After you convert step 9, click ToolsReload All Libraries. The schematic shows the
primitives converted. Resistors that were named Xr0 and Xr1 are now Rr0 and Rr1,
respectively, and will now behave as primitive resistors.
To convert the other symbols (special symbols), such as the ground pins and voltage
references, begin by right clicking a ground symbol and choosing Change Symbol.
Change all analoglib ground symbols to ground symbols from $default.
Repeat step 12 for the vcc and vss symbols, replacing all the analoglib vcc and vss
symbols with symbols from $default.
Since there are question marks beside the transistors, double-click one of the transistors
and in the MNAME field, type a model name there. Then, set the scope pull-down to
Matching. Click OK.
286
EDIF
15. To finish, browse through the symbol instances to see if there are any attribute values you
want to set or attribute visibilities you want to enable or disable. Then, press F3 that runs
a drawing check and displays the netlist. Figure 9-11 shows the final resulting netlist.
287
Exporting EDIF 2 0 0
EDIF
288
Exporting EDIF 2 0 0
EDIF
289
Exporting EDIF 2 0 0
EDIF
290
Exporting EDIF 2 0 0
EDIF
291
Chapter 10
Schematic Design Examples
293
294
295
296
3. Choose a name for the new library and directory path where the library will reside. In this
case, the library is named example_digital. See Figure 10-5.
297
5. Since this is a primitive digital library in this example, the shape will be set to Use Filter
so that logic symbols can be used wherever applicable (Figure 10-7).
298
7. After all data has been imported, the Import dialog closes. In the Gateway library and
symbol panes, the new library can be selected and resulting symbols shown (Figure 10-8).
299
300
301
302
303
Figure 10-13 Manually Selecting the Correct Definition to Match the Symbol
304
Chapter 11
Scripting
Javascript in Gateway
Scripting
Use the command line text box at the bottom of the main window.
Write a script file and execute the commands by selecting ToolsRun Script .
Use the debug environment by using ToolsRun Script with Debugger.
Pass a script file into Gateway at startup using either the -mnu or -jscript command
line arguments.
306
Callback Scripting
Scripting
Init
Value Changed
Done
The Init action is called when you first interact with the symbol (i.e., selects the symbol). This
gives the ability for instance to the symbol designer to decide which attributes to show to you
depending on the value of other attribute.
The Value Changed callback will run the script when the value is being committed to the
schematic instance.
The Done callback is run when all editing has been changed. If editing with the Properties
editor on the design browser, this callback is fired on a lost focus event. If in the properties
dialog, this callback is fired when all the current changes have been applied. Typically, this
action is used to allow validation to take place.
307
Callback Scripting
Scripting
308
Callback Scripting
Scripting
Init
This is called when the symbol instance initializes the properties editor/dialog.
Syntax
function <myfunc>(hSymbol, attributes);
Parameters
Name
Description
hSymbol
attributes
Return Value
None
Example
with (Silvaco.Gateway)
{
function resInit(hSymbol, attributes)
{
if(attributes.R.value < 10)
// value, enable, visible
{
attributes.SCALE.visible = true;
attributes.SCALE.enable = true;
attributes.SCALE.drawing_visibility = NVV_NAME_VALUE ;
}
else if(attributes.R.value > 10)
{
attributes.SCALE.visible = false ;
attributes.SCALE.drawing_visibility = NVV_INVISIBLE;
}
}
}
309
Callback Scripting
Scripting
Value Changed
This is called when a value has changed on the symbol instance.
Syntax
function <myfunc>(hSymbol, changed, attributes);
Parameters
Name
Description
hSymbol
changed
attributes
Return Value
None
Example
with (Silvaco.Gateway)
{
function isChanged(changed, name)
{
for (p in changed)
{
if (changed[p] === name)
return true;
}
return false
}
function resValueChanged(hRes, changed, attributes)
{
const rho = 200;
var W = parseFloat(attributes.W.value);
var L = parseFloat(attributes.L.value);
if (isChanged(changed,"W"))
{
display("Width changed: Calculating R");
R = rho * L / W;
}
attributes.R.value = R;
}
}
310
Callback Scripting
Scripting
Done
This is called when you finish editing an attribute or, in the case of the dialog, when a set of
attributes have been applied.
Syntax
function <myfunc>(hSymbol, attributes);
Parameters
Name
Description
hSymbol
attributes
Return Value
Boolean. If failure, the attribute changes are not committed.
Example
with (Silvaco.Gateway)
{
function resDone(hSymbol, attributes)
{
if(attributes.R.value < 10)
{
attributes.SCALE.visible = true;
attributes.SCALE.enabled= true;
attributes.SCALE.drawing_visibility = NVV_NAME_VALUE ;
}
else if(attributes.R.value > 10)
{
attributes.SCALE.visible = false ;
attributes.SCALE.enable = false;
attributes.SCALE.drawing_visibility = NVV_INVISIBLE;
}
}
}
311
Callback Scripting
Scripting
Properties
Property
Description
value
enabled
visible
drawing_visibility
Constants
Constant
Description
NVV_INVISIBLE
NVV_VALUE
NVV_RESULT
NVV_NAME
NVV_NAME_VALUE
NVV_NAME_RESULT
NVV_DESCRIP
NVV_DESCRIP_VALUE
NVV_DESCRIP_RESULT
312
Appendix A
Communications
Troubleshooting
Common Issues
Communications Troubleshooting
Cannot create input deck/netlist/control deck (see Section A.1.1 Cannot create input deck/
netlist/control deck)
Simulation does not run (Section A.1.2 Simulation Does Not Run)
Cannot plot vectors (Section A.1.3 Cannot Plot Vectors)
DC Bias markers not present (Section A.1.4 DC Bias markers Not Present)
Output/error file not present (Section A.1.5 Output/Error File Not Present)
Licensing issues (Section A.1.6 Licensing Issues)
Nameservice issues (Section A.1.7 Nameservice Issues)
67
the first part of the line shows the user permissions (i.e., drwxr-xr-x). This particular
example shows that the user username has read (r), write (w), and execute (x) permissions on
this directory. It also shows that any one in the Silvaco group has read (r) and execute (x)
permissions and all other users also have read (r) and execute (x) permissions.
On Windows platforms, right-click on the directory in Explorer and choose Properties
(see Figure A-1).
314
Common Issues
Communications Troubleshooting
Filesystem
kbytes
used
export/data1/users/username
70565698
25885917
avail
On Windows platforms, right-click on the drive in Explorer and choose Properties (see
Figure A-2).
315
Common Issues
Communications Troubleshooting
316
Common Issues
Communications Troubleshooting
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example, if you were looking for 2.17.0.R on Windows the directory
would be c:\sedatools\lib\smartspice\2.17.0.R\x86-nt and the executable name
would be smartspice.exe. As an added security measure, SIPC can only launch
applications listed in $S_INSTALL_ROOT/var/sipcclients.cnf.
Typical sipcclients.cnf file
This file contains the programs that can be launched through the SIPC Communications.
# ---------------------------# Sipc authorized applications
#
# File syntax:
# ----------# - All the fields of this file must be separated by 1 or
#
#
# - Quote are allowed but you don't need to quote Application name
if
#
it contains spaces because spaces are not considered as
separators.
#
# - The App Type column is a single letter in ['S'|'C'|'N']:
#
+ 'S' means : the application is a Sipc Server (with Sipc >=
0.3.0)
#
317
Common Issues
Communications Troubleshooting
SIPC_TEMPLATE_VERSION
1.0
# ---------------------------SIPC_TEMPLATE_VERSION
1.0
# +---------------+----+----------------+-----------# |ALIAS
# | NAME
|Type|
Name| arguments
# +---------------+----+----------------+-----------# |
smartspice
<S_INSTALL_ROOT>/bin/smartspice
smartview
<S_INSTALL_ROOT>/bin/smartview
scholar
<S_INSTALL_ROOT>/bin/scholar
vwf
<S_INSTALL_ROOT>/bin/vwf
-d -fg
Confirm that the input deck is present and can be read by the user
To confirm that the input deck is present and can be read by the user, go to the directory where
the schematic file is placed (e.g., c:\examples) and look for the file <schematic name>.in
(e.g., RSFF_Simulation.in which corresponds with RSFF_Simulation.schlr).
To confirm if the user can read input deck, do the following:
On UNIX, use the command ls l <inputdeck> in the schematic directory to get its
base permissions. For example:
-rw-r--r-1
RSFF_Simulation.in
username
silvaco
2791
Nov
14
15:52
On Windows platforms, right-click on the directory in Explorer and choose Properties (see
Figure A-3).
318
Common Issues
Communications Troubleshooting
319
Common Issues
Communications Troubleshooting
Check to see if there are any errors present in the Gateway Session window
Another reason for the simulation not running could be due to actual simulation errors, such
as cannot find model, cannot converge, and no control statements present. These errors will
be displayed in the Gateway Session Window (see Figure A-4).
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example if you were looking for 2.9.38.R on Windows, the directory
would be c:\sedatools\lib\smartview\2.9.38.R\x86-nt and the executable name
would be smartview.exe. Due to added security to the SIPC launching of a program,
specifically not allowing the ability to launch any program (unless the Administrator has
authorized it), there is an alias file, $S_INSTALL_ROOT/var/sipcclients.cnf .
320
Common Issues
Communications Troubleshooting
This file contains the programs that can be launched through the SIPC Communications.
# ---------------------------# Sipc authorized applications
#
# File syntax:
# ----------# - All the fields of this file must be separated by 1 or
#
#
# - Quote are allowed but you don't need to quote Application name
if
#
it contains
separators.
spaces
because
spaces
are
not
considered
as
#
# - The App Type column is a single letter in ['S'|'C'|'N']:
#
+ 'S' means : the application is a Sipc Server (with Sipc >=
0.3.0)
#
#
# - Trailling or leading SPACEs, TAB char are removed from a whole
line.
#
# - Environment variables should be enclosed by < and >.
#
# - The first parsed line must be
#
SIPC_TEMPLATE_VERSION
1.0
# ---------------------------SIPC_TEMPLATE_VERSION
1.0
# +---------------+----+----------------+-----------# |ALIAS
# | NAME
Name| arguments
# +---------------+----+----------------+-----------# |
|
smartspice
|
S
|
<S_INSTALL_ROOT>/bin/smartspice
321
Common Issues
Communications Troubleshooting
smartview
<S_INSTALL_ROOT>/bin/smartview
scholar
<S_INSTALL_ROOT>/bin/scholar
vwf
<S_INSTALL_ROOT>/bin/vwf
-d -fg
Check to see if there are any errors present in the Gateway Session Window
Another reason that can cause vectors not to be plotted could be due to actual simulation
errors. For example, cannot find vector, cannot converge, or no control statements present.
These errors will be displayed in the Gateway Session Window (see Figure A-4).
where <version> is the version that you are interested in and <platform> is the platform
that you are on. For example if you were looking for 2.17.0.R on Windows, the directory
would be c:\sedatools\lib\smartspice\2.17.0.R\x86-nt and the executable name
would be smartspice.exe.
Check to see if there are any errors present in the Gateway Session Window
The DC Bias markers may not be present due to actual simulation errors, such as cannot find
model, cannot converge, and no control statements present. These errors will be displayed in
the Gateway Session Window (see Figure A-4).
322
Common Issues
Communications Troubleshooting
Check to see if there are any errors present in the Gateway Session Window after running
the simulation, such as model errors and unable to converge.
Make sure the user has write permissions in the output/error directory
Check to see if there are any errors present in the Gateway Session Window
If there are no errors present in the Session window, then the error file may not be present or
will be empty. If this occurs, then Gateway will not allow you to view the error file. These
errors will be displayed in the Gateway Session Window (see Figure A-4).
Make sure the user has write permissions in the output/error directory
The output/error file can be absent due to write permissions in the output/error directory. To
confirm the write permissions for the output/error directory, do the following:
On UNIX use the command ls al . in the output/error directory to get its base
permissions and search for the . entry. For example:
drwxr-xr-x
67
the first part of the line shows the user permissions (i.e., drwxr-xr-x). This particular
example shows that the user username has read (r), write (w), and execute (x) permissions on
this directory. It also shows that any one in the Silvaco group has read (r) and execute (x)
permissions and all other users also have read (r) and execute (x) permissions.
On Windows platforms, right-click on the directory in Explorer and choose Properties (see
Figure A-5).
323
Common Issues
Communications Troubleshooting
where
<S_INSTALL_ROOT>
is
the
When the Silvaco Management Console appears, select SystemLicensing (see Figure A6). The Licensing tab will show which server the license monitoring program is using and
what licenses are currently checked out.
324
Common Issues
Communications Troubleshooting
325
Common Issues
Communications Troubleshooting
326
Index
A
Adding
Diagonal Wires .............................................................. 139
Drawing Objects ............................................................ 198
Symbols ....................................................................... 120
Text ............................................................................ 198
Wires ................................................................... 134139
Analog ............................................................................ 244
Analyses Toolbar ................................................................. 17
Application Settings Group
Auto-Save ...................................................................... 33
Colors ...................................................................... 3435
Drawing Checks ............................................................... 36
Frame ...................................................................... 3738
Grid ......................................................................... 3941
Number Format ............................................................... 54
Shortcuts ........................................................................ 57
Technology ..................................................................... 58
Toolbars ......................................................................... 59
Arrays ..................................................................... 185190
Atlas ................................................................................. 45
Control File ................................................................... 237
Netlisting ...................................................................... 224
Preferences .............................................................. 45, 66
Template String ............................................................. 161
Attribute Object ................................................................. 312
Attributes
Editing ......................................................... 127, 128130
Ordering and Positioning .......................................... 130133
Symbol ................................................................ 158161
Symbol Pin ................................................................... 156
Wires ................................................................... 138139
AvanWaves
Preferences .................................................................... 72
B
Buses
Chord Symbol ....................................................... 148153
Iterative Instances .......................................................... 154
Naming Conventions ............................................... 145146
Ripping ................................................................ 147148
C
Callback API ............................................................. 309312
Callback Script
Attaching ...................................................................... 307
Callback Scripting
Specifying .................................................................... 308
CDL
Control File ................................................................... 237
Netlisting ......................................................................224
Template String .............................................................161
Changing Symbols .....................................................194196
Checking Designs ............................1416, 36, 220223, 242
Chord Symbol ...........................................................148153
Colors ...............................................................................34
Editing and Resetting to Default .........................................199
Control Cards ........................................................1617, 250
Control Files
Atlas ............................................................................237
CDL ............................................................................237
Guardian ......................................................................236
NDL ............................................................................237
Simulation ............................................................230237
SmartSpice ...................................................................230
Verilog .........................................................................231
Window ..........................................................................17
Converting from EDIF .................................................281287
Copying ...........................................................................124
Creating
Control Files ..........................................................230237
Schematic Drawings .........................................................80
Specific Netlists .....................................................227229
Symbols ...............................................................155164
Symbols from Schematic ..................................................192
Cross Probing ...........................................................247249
D
DC Bias ...................................................................254259
Deck ...............................................................................238
DeckBuild ...........................................................................66
Deleting ...........................................................................124
Descending ......................................................................193
Deselecting ......................................................................122
Design Checking ..............................1416, 36, 220223, 242
Design Flow
Control Files ..........................................................230237
Error Checking .......................................................220223
Input Deck ....................................................................238
Netlisting ..............................................................224229
Simulation ....................................................................240
Designs
Exporting ..................................................8690, 299300
Importing ........................................................91, 302304
Disconnecting ...........................................................125126
Done ...............................................................................311
Drawing .............................................................................36
Drawings
Creating .........................................................................80
327
Index
Exporting ........................................................................ 82
Opening ......................................................................... 79
Printing .................................................................... 8485
Saving ..................................................................... 8182
E
EDIF
Converting Imported Files ........................................ 281287
Exporting .............................................................. 288291
Importing Files ....................................................... 275280
Edit Symbol Attributes Dialog ............................... 128130, 158
Editing
Schematics ........................................................... 110204
Symbols ............................................................... 156164
Errors .............................................................................. 222
Disabling and Enabling .................................................... 223
Review Errors Pane .................................................. 14, 220
Expert ....................................................................... 62, 260
Exporting
Designs ................................................... 8690, 299300
EDIF ................................................................... 288291
Picture Formats ............................................................... 82
F
File Details ............................................................... 203204
File Operations
Create Drawings .............................................................. 80
Exporting Designs ...................................................... 8690
Exporting Drawings ..................................................... 8283
Loading Workspaces ......................................................... 78
Opening Drawings ............................................................ 79
Printing Drawings ....................................................... 8485
Saving Drawings ........................................................ 8182
Files ................................................................................. 90
G
Gateway Window ................................................................. 12
Generating
Names ................................................................. 181184
Symbols ............................................................... 191192
Go to Sheet Dialog ............................................................... 98
Guardian
Control File ................................................................... 236
Netlisting ...................................................................... 224
Preferences .................................................................... 48
Template String ............................................................. 161
GUI Environment and Settings
Panes ...................................................................... 2631
Preferences Dialog ..................................................... 3269
Windows .................................................................. 2631
H
Help .................................................................................. 92
HSPICE
Netlisting ...................................................................... 224
Preferences ..............................................................52, 67
Template String .............................................................161
I
Importing
Designs ..........................................................91, 302304
EDIF ....................................................................273280
SPICE .................................................................293298
Verilog .................................................................293298
Inherited Nets
Examples .............................................................143144
Expressions ..................................................................141
Properties .....................................................................140
Init ..................................................................................309
Input Deck ............................................................1922, 238
Instance Attributes Dialog ....................................................127
Instances
Attributes Dialog .............................................................128
Disconnecting ........................................................125126
Inverting Selection ......................................................122, 123
L
Layout Editor ..............................................................62, 260
Libraries
Filtering ........................................................................116
Modifying ......................................................................107
Reloading .....................................................................197
Spicelib ........................................................................101
Structures .....................................................................107
Version Control System (VCS) ..........................................108
Licensing .................................................................324325
LVS ..................................................................................48
Control File ...................................................................236
Netlisting ......................................................................224
Preferences ..............................................................48??
Template String .............................................................161
M
Mirroring ..........................................................................123
MixedMode .........................................45, 161, 224, 237, 242
N
Nameservice .....................................................................326
NDL
Control File ...................................................................237
Netlisting ......................................................................224
Preferences ....................................................................50
Template String .............................................................161
netInherit ..........................................................................141
Netlists
Atlas ......................................................................45, 224
CDL ......................................................................47, 224
LVS/Guardian ..........................................................48, 224
NDL ......................................................................50, 224
Rebuilding ....................................................................224
328
Index
O
Objects
Alignment and Spacing ............................................ 199200
Open Symbol Dialog ........................................................... 155
Options ............................................................................ 274
Ordering Pins for Netlisting .......................................... 227228
Output Tab ................................................................. 12, 220
P
Panning ................................................................... 207209
Pasting ............................................................................ 124
Pins
Attributes Dialog ............................................................ 156
Bi-Directional ................................................................. 183
Input ............................................................................ 183
Page ................................................................. 9495, 99
Regenerating Names ...................................................... 183
Plot ................................................................................. 244
Plotting
From Archive ................................................................. 264
Options ........................................................................ 244
Vectors .................................................... 20, 64, 249, 264
Preferences
Exporting .................................................................. 7374
Importing ........................................................................ 75
Managing ................................................................. 7375
Recent Files .................................................................... 76
Resetting to Defaults ......................................................... 75
Preferences dialog
Application Settings Group ........................................... 3359
Netlist Settings Group ................................................. 4452
Tools Settings Group .................................................. 6268
Printing ........................................................................ 8485
Property pane editing .......................................................... 127
Q
QuickStart .................................................................... 1324
R
Rawfile ................................................................ 10, 64, 264
Rebuild ............................................................................ 224
Regenerating
Pin Names .................................................................... 183
S
Schematic Design
Design Browser .....................................................212215
Design Flow ..........................................................219240
Design Sheets. ..........................................................9499
Editing .................................................................111204
Example ...............................................................293304
File Details ............................................................203204
Miscellaneous Editing Options ...................................198201
Showing Node and Symbol Information ...............................216
Viewing ................................................................206217
Schematics .......................................................................176
Selecting ..........................................................................122
Session Tab .......................................................12, 220, 248
Setting Plot Options ....................................242, 244246, 322
Sheets
Adding ...........................................................................98
Connecting .....................................................................99
Deleting .........................................................................98
Navigating ......................................................................98
Pins ..............................................................................99
Silos
Example ...............................................................265270
Netlisting ......................................................................224
Simulator ........................................................................68
Template String .............................................................161
Simulation
DC Bias Display .....................................................254259
Post-Processing .............................................................264
Pre-Simulation .......................................................242243
Running .................................................23, 240, 250253
Schematic Marking .................................................247249
SmartSpice Device Information ..................................260263
SmartSpice Status ..........................................................259
SmartSpice .......................................................................162
Analyses ..............................................................232234
Importing to Gateway ..............................................293295
Netlisting ......................................................................224
Preferences ....................................................................52
Simulator ........................................................................63
Template String .....................................................161, 162
SmartSpice RF
Analyses ......................................................232234, 236
Netlisting ......................................................................224
Preferences ....................................................................52
329
Index
Simulator ........................................................................ 63
Template String ............................................................. 161
SmartView
Example ................................................................. 24, 270
Preferences .................................................................... 70
Special Keys Bindings .......................................................... 77
Stubs Wires and Stub Wires with Pins .................................... 198
Switching ......................................................................... 117
Symbols
Attributes. ............................................................. 128133
Changing ............................................................. 194196
Copying ....................................................................... 124
Creating ....................................................................... 155
Deleting ....................................................................... 124
Deselecting ................................................................... 122
Editing ................................................................. 156164
Embedded, Attached, and Schematic Definitions ........... 166178
Files ............................................................................ 101
Generating ........................................................... 191192
Mirroring ...................................................................... 123
Moving ......................................................................... 124
Opening ....................................................................... 155
Passing Parameters From Symbol to Schematics .......... 176178
Placing ................................................................ 120124
Primitive ....................................................................... 165
Regenerating Instance Names .......................................... 182
Rotating ....................................................................... 123
Selecting ...................................................................... 122
Showing Information ....................................................... 216
Special ........................................................................ 166
Subcircuits .................................................................... 193
Verilog-A ...................................................................... 172
Example ...............................................................265270
Importing into Gateway ............................................293295
Netlisting ......................................................................224
Simulator ......................................................................173
Template String .............................................................161
Viewing
Schematics ...................................................................205
Switching Design Views ...........................................117119
Visibility Constants .............................................................312
vprims .............................................................................101
Zooming ..................................................................207209
W
Warnings ...................................................................36, 222
Disabling and Enabling ....................................................223
Review Errors Pane ..........................................................14
Waveform Viewer
AvanWaves ....................................................................72
SmartView ......................................................................70
TonyPlot .........................................................................71
Wires
Attributes Dialog .....................................................138139
Creating .......................................................................137
Deleting .......................................................................124
Disconnecting ........................................................125126
Merging Rules .......................................................134137
Snapping ..............................................................138139
Terminology ..................................................................134
Types ..........................................................................139
Workspaces
Changing Settings ..........................................................105
Saving .........................................................................106
V
Value Changed ................................................................. 310
Vectors
Plotting .................................... 20, 64, 249, 264, 320322
Verilog ....................................................................... 53, 161
330