FUTURE WORK

In the last few years, a new transistor designthe tunnel FET, or TFEThas
been gaining momentum. Unlike the MOSFET, which works by raising or
lowering an energy barrier to control the flow of current, the TFET keeps this
energy barrier high. The device switches on and off by altering the likelihood
that electrons on one side of that barrier will materialize on the other side.
paving the way for faster, denser, and more energy-efficient circuits that will
extend Moores Law well into the future.
Unlike the MOSFET which holds the source and drain in a doped substrate the
TFET holds the source and the drain in an intrinsic semiconductor i.e. it follows
the PIN orientation. This when supplies with sufficient gate bias leads to a
concept called band to band tunnelling, band-to-band tunnelling (BTBT) occurs
when the conduction band of the intrinsic region aligns with the valence band of
the P region. Electrons from the valence band of the p-type region tunnel into
the conduction band of the intrinsic region and current can flow across the
device. As the gate bias is reduced, the bands becomes misaligned and current
can no longer flow.
Advantages of TFET over MOSFET
Lower power consumption
Steep sub-threshold transistors
Small voltage swing switches
Sub-threshold leakage reduction
Low off current
ON current - band-to-band tunnelling(BTBT).
Lower sub-threshold slope (< 60 mV/dec) [higher ION-IOFF ratio]

The TFET SRAM

The TFET 6T SRAM structure is similar to a structure that of the CMOS
SRAM the only difference being that, since the TFET device is unidirectional it
can either take data inwards of give data outwards based on this we can have
four possible configurations for the TFET 6T SRAM
outward n-type
outward p-type
inward n-type
inward p-type
On an overall comparison between the TFET, CNTFET and MOSFET the
TFET is far superior in terms of the noise margin and the power dissipation
factors, it is also well suited for design of digital logic elements like the SRAM
because of the improved stability and also the faster switching characteristics.
The main objective of this paper at first was to design the TFET SRAM cell but
due to many technical constrains we faced during the process we decided to try
working with the CNTFET first and use this as a stepping stone for the second
phase of our project where will extensively work with the design of the TFET
SRAM, with the aim of achieving an in depth and extensive study about two of
the newer technologies and to be able to decide the final verdict by comparing
both of them with a common standard.
To start moving towards the goal we first decided to generate one transistor
with all the parameters set and then to use that as a module to build more
complex structures. we have also written a .va(extension for verilog analog)
code to initiate the device.

CODE

`include "constants.vams"
`include "disciplines.vams"

module NTFET(d,g,s);
inout d,g,s;
electrical g,d,s;
real Ids, Cgs, Cgd,Qg, Qgs, Qgd, f;
real VgsEff;
integer out_file;
parameter real W=1;

analog begin

Ids=$table_model(V(d,s), (V(g,s)), "IdVg-GaSb-InAs-HNTFET-Lg20nm.tbl","1LL,1LL");

Cgd=$table_model(V(d,s), (V(g,s)), "CGD-GaSb-InAs-HNTFET-Lg20nm.tbl","1LL,1LL");
Cgs=$table_model(V(d,s), (V(g,s)), "CGS-GaSb-InAs-HNTFET-Lg20nm.tbl","1LL,1LL");

if(analysis("dc")) begin
I(d,s) <+ 1*Ids*W;
end
else begin
if(analysis("tran")) begin
Qgd = (W*1*Cgd)*(V(g,d));
Qgs = (W*1*Cgs)*(V(g,s));

Qg=Qgd+Qgs;
I(d,s) <+ 1*Ids*W ;
I(g) <+ ddt(Qg);
I(s) <+ ddt(-1*Qgs);
I(d) <+ ddt(-1*Qgd);
end
end

end
endmodule

The main problems we faced were the errors that the software threw while
simulating this code probably due to the lack of availability of model files for
the design of the structure. At this point we were able to assign a new
technology called TFET to the software and generate a symbol for the same the
only hurdle that is left between us and generation of our first TFET transistor is
that we are still not able to teach the software how this new technology behaves,
the code mentioned above uses design based lookup tables to generate the
required device characteristics, unfortunately the system is not accepting this
approach and is throwing some errors.

In the second phase of this project we will extensively look into the various
errors that have occurred now and work our best to rectify them so that we can
finally have the analysis module for one transistor and hence a full working
structure of the TFET 6T SRAM we will also try to simulate the four modes for
the same.