iMX6 Dual/Quad Processor Timing Model for DDR3L-1066 Memory

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From
Alexander Karas
Date : 23 August 2013
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Hans Klos (Sintecs)
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Subject :
: iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066.doc
Tom Berends (Sintecs)
iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066
Classification: internal
iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066
DOCUMENT CHANGE & HISTORY RECORD

Maintainer
Last update
Status
Version
Alexander Karas
06-04-2013
Draft
0.1
Comment
Timing analysis report
Reference documents
Ref.
1.1
Title
Document name
i.MX 6Dual/6Quad Automotive and

Infotainment Applications Processors
IMX6DQxxEC.pdf
Modified
date
Rev. 1,
11/2012
1.2
1.3
Analyses performed with the Mentor Graphics high-speed board design analyses tooling (Hyperlynx).
Page 1 of 13
Status
Date :
23 August 2013
Ref :
iMX6_Dual-Quad_Processor_timing_model_creation_DDR3L-1066.doc
Subject: iMX6_Dual-Quad_DDR3L-1066
Index
1
i.MX6Solo processor timing analysis .................................................. 3

1.1
1.2
1.3
1.4
Introduction.......................................................................................................... 3
Project activities and deliverables ....................................................................... 3
Analysis software information .............................................................................. 3
Critical Net List .................................................................................................... 3
Timing model ........................................................................................ 4

3.1
DDR3 timing model i.MX6Dual/Quad Memory Controller (1066 MT/s) ............... 4
3.1.1
Deriving tCKAC(min) and tCKAC(max) ........................................................ 6
3.1.2
Deriving tCKCTL(min) and tCKCTL (max). 6
3.1.3
Deriving tCKDQS(min) and tCKDQS(max) .................................................. 6
3.1.4
Deriving tDQSDQ(min) and tDQSDQ(max).................................................. 7
3.1.5
Deriving tDS and tDH ................................................................................... 7
3.1.6
Summary of DDRx Wizard Parameters ........................................................ 7
3.2
DDR3 timing model memory device (Micron, JEDEC DDR3-1066 model) ........ 11
Conclusion .......................................................................................... 13
Page 2 of 13
Date :
23 August 2013
Ref :
i.MX6Dual/Quad processor timing analysis
1.1
Introduction
A timing analysis is done for the i.MX6-Dual/Quad DDR3L Memory Controller. This
document describes the results of these analyses.
In this chapter, all the information, needed for setting up the simulation database is
mentioned.
1.2
Project activities and deliverables
For the Timing analyses of the i.MX6-Dual/Quad processor design, the following tasks
and activities had to be done:
1. Collect i.MX6-Dual/Quad Memory Controller timing information

2. Creation timing model
3. Analysis document
1.3
Analysis software information
Simulator:
- Mentor Graphics HyperLynx Timing Model Wizard
1.4
GROUP
DDR3L-1066
Critical Net List

NAME
FREQ
DRAM_DQS*
DRAM_DQ*
DRAM_CK*
DRAM_ADDR*
DRAM_CMD*
533 MHz
533 MHz
533 MHz
266 MHz
266 MHz
DRAM_CTRL*
266 MHz
Page 3 of 13
DESCRIPTION
DDR3 strobe
DDR3 data
DDR3 clock
DDR3 address
DDR3 command
DDR3 control
8.2.1
Date :
23 August 2013
Ref :
2 Timing model
2.1
DDR3L timing model i.MX6-Dual/Quad (1066 MT/s)
Freescale iMX6-Dual/Quad Memory Controller Datasheet Parameters Timing Diagram
Page 4 of 13
Date :
23 August 2013
Ref :
Parameters
tIS
tIH
tDS
tDH
tDQSS(min)
tDQSS(max)
tDQSDQ(min)
tDQSDQ(max)
Definitions
Add/Cmd/Ctrl signals setup time with relative to MCK
Add/Cmd/Ctrl signals hold time with relative to MCK
DQ/DQM setup time with relative to DQS
DQ/DQM hold time with relative to DQS
DQS to CK skew (min)
DQS to CK skew (max)
DQS to DQ valid data, Read cycle
DQS to DQ valid data, Read cycle
Page 5 of 13
Value
500 ps
400 ps
240 ps
240 ps
- 0.25 tCK
+ 0.25 tCK
-225 ps
225 ps
Date :
23 August 2013
Ref :
2.1.1
Deriving tCKAC(min) and tCKAC(max) for i.MX6Solo Memory Controller
SpeedGrade
DDR3L-1066
tCK
1/533 MHz =1876 ps
tCKAC(min)
tCK + tIH = 1876 ps + 500 ps = 1376 ps
2.1.2
tIH
500 ps
400 ps
tCKAC(max)
tCKAC(max) = tIS = 400 ps
Deriving tCKCTL(min) and tCKCTL (max) for i.MX6Solo Memory Controller
SpeedGrade
DDR3L-1066
tCKCTL(min)
tCK
tIS
500 ps
1876 ps
tIH
400 ps
tCKCTL(max)
tCK + tIH = 1876 ps + 500 ps = 1376 ps
2.1.1
tIS
tCKAC(max) = tIS = 400 ps
Deriving tCKDQS(min) and tCKDQS(max) for i.MX6Solo Memory Controller
SpeedGrade
DDR3L-1066
tCKDQS(min)
tCKDQS(min) = -0.25 * tCK = -469 ps
tCK
1876 ps
Page 6 of 13
tDQSS(min)
tDQSS(max)
- 0.25 * tCK
0.25 * tCK
tCKDQS(max)
tCKDQS(max) = 0.25 * tCK = 469 ps
Date :
23 August 2013
Ref :
2.1.2
Deriving tDQSDQ(min) and tDQSDQ(max) for i.MX6Solo Memory Controller
SpeedGrade
tCK
DDR3L-1066
1876 ps
tDQSDQ(min)
0.5*tCK + tDH = 0.5 * 1876 +240 = 698 ps
2.1.3
Deriving tDS and tDH for i.MX6Solo Memory Controller

SpeedGrade
tCK
DDR3L-1066
1876 ps
tDS
|tCISKEW(max)| = tDQSShift tDQSDQ(max) = 469
225 = 244 ps
2.1.4
tDS
tDH
240 ps
240 ps
tDQSDQ(max)
tDS = 240 ps
tDQSDQ(min)
tDQSDQ(max)
225 ps
225 ps
tDH
|tCISKEW(min)| = 0.5*tCK
tDQSShift tDQSDQ(min) = 938
469 225 = 244
Summary of DDRx Wizard Parameters for i.MX6-Dual/Quad Controller
DDRx Wizard Required Parameters

tCKAC
tCKCTL
tCKDQS
tDQSDQ
tDS
tDH
Min (ps)
1376
1376
469
698
244
244
Timing model in Hyperlynx:

Page 7 of 13
Max (ps)
400
400
469
240
Date :
23 August 2013
Ref :
Address/Command timing
Control timing
Page 8 of 13
Date :
23 August 2013
Ref :
Write strobe timing
Write data timing
Page 9 of 13
Date :
23 August 2013
Ref :
Read data timing
Page 10 of 13
Date :
23 August 2013
Ref :
2.2
DDR3 timing model memory device (Micron, JEDEC DDR3-1066 model)
This model (values) is supplied by the JEDEC committee and Micron DDR3 devices
comply with the JEDEC specification.
Clock vs. address/command/control constraints
Strobe to clock constraints (write)
Page 11 of 13
Date :
23 August 2013
Ref :
Setup and Hold constraints
Strobe delay relative to the clock (read)
Page 12 of 13
Date :
23 August 2013
Ref :
Data delay relative to the Strobe (read)
Conclusion
No timing issues found in the DDR3 interface.
Page 13 of 13

iMX6 Dual/Quad Processor Timing Model for DDR3L-1066 Memory

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Edality

3-i Zagorodnyi lane

Date : 23 August 2013

Hans Klos (Sintecs)

Tom Berends (Sintecs)

DOCUMENT CHANGE & HISTORY RECORD

i.MX 6Dual/6Quad Automotive and

i.MX6Solo processor timing analysis .................................................. 3

Timing model ........................................................................................ 4

i.MX6Dual/Quad processor timing analysis

Project activities and deliverables

1. Collect i.MX6-Dual/Quad Memory Controller timing information

Analysis software information

Critical Net List

DDR3L timing model i.MX6-Dual/Quad (1066 MT/s)

Freescale iMX6-Dual/Quad Memory Controller Datasheet Parameters Timing Diagram

Deriving tCKAC(min) and tCKAC(max) for i.MX6Solo Memory Controller

Deriving tCKCTL(min) and tCKCTL (max) for i.MX6Solo Memory Controller

tCK + tIH = 1876 ps + 500 ps = 1376 ps

tCKAC(max) = tIS = 400 ps

Deriving tCKDQS(min) and tCKDQS(max) for i.MX6Solo Memory Controller

Deriving tDQSDQ(min) and tDQSDQ(max) for i.MX6Solo Memory Controller

Deriving tDS and tDH for i.MX6Solo Memory Controller

Summary of DDRx Wizard Parameters for i.MX6-Dual/Quad Controller

DDRx Wizard Required Parameters

Timing model in Hyperlynx:

Write strobe timing

Write data timing

Read data timing

DDR3 timing model memory device (Micron, JEDEC DDR3-1066 model)

Clock vs. address/command/control constraints

Strobe to clock constraints (write)

Setup and Hold constraints

Strobe delay relative to the clock (read)

Data delay relative to the Strobe (read)

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