SAN MARCOS
(Universidad del Per. Decana de Amrica)
CURSO
DISEO DIGITAL
PROFESOR
ING UTRILLA
ALUMNO
CODIGOS:
03190045
AULA
LABORATORIO DE DISEO
DIGITAL
TEMA
TRABAJO FINAL 2
ESCUELA DE ELECTRONICA
CURSO
PROFESOR
CICLO ACADEMICO
: DISEO DIGITAL
: ING. DARIO UTRILLA SALAZAR
: 2009-I
Ejercicios:
1. Implemente y simule el circuito latch:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity latch is
port (enable,data:in std_logic;
q:out std_logic);
end latch;
architecture algoritmo of latch is
begin
Process(enable,data)
begin
if enable='1' then
q<=data;
end if;
end process;
end algoritmo;
library ieee;
use ieee.std_logic_1164.all;
entity conta1 is
port( clk : in std_logic;
enable
: in std_logic;
qa
: out integer range 0 to 15);
end conta1;
architecture algoritmo of conta1 is
signal cnt: integer range 0 to 15;
begin
process (clk)
begin
NOTA: Para la simulacin la seal de reloj es peridica y tiene una frecuencia de 1KHz. La
seal enable se habilita durante 5ms a partir del tiempo 12ms.
Escribir el cdigo que utiliz para la simulacin en el ModelSim
library ieee;
use ieee.std_logic_1164.all;
entity conta2 is
port( clk : in std_logic;
clear : in std_logic;
q
: out integer range 0 to 15);
end conta2;
architecture algorit2 of
conta2 is
begin
process (clk)
variable cnt : integer range 0 to 15;
begin
if clk = '1' then
3.1.- Indique que diferencias encontr entre las simulaciones de conta1 y conta2
library ieee;
use ieee.std_logic_1164.all;
entity preg4 is
port (control,clk:in bit;
cuenta:out integer range 0 to 15);
end preg4;
architecture contador_up_down of preg4 is
begin
process(clk)
variable cnt:integer range 0 to 15;
begin
if (clk='1') then
if control='0' then
if cnt=15 then
cnt:=0;
else
cnt:= cnt +1;
end if;
else
if cnt=0 then
cnt:=15;
else
cnt:= cnt -1;
end if;
end if;
end if;
cuenta<=cnt;
end process;
end contador_up_down;
5.
library ieee;
use ieee.std_logic_1164.all;
entity preg5 is
Port ( Clk,LD: in bit;
DATO:in integer range 0 to 15;
Sum:out integer range 0 to 15);
end preg5;
architecture carga of preg5 is
begin
process
variable cnt:integer range 0 to 15;
begin
wait until clk='1';
if LD='0' then
if cnt=15 then
cnt:=0;
else
cnt:=cnt+1;
end if;
else
cnt:=DATO;
end if;
sum<=cnt;
end process;
end carga;
6. Simular
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
Port (d :in bit_vector(7 downto 0);
clk :in bit;
q :out bit_vector(7 downto 0));
end pipo;
architecture algoritmo of pipo is
begin
process
begin
wait until clk='1';
q <=d;
end process;
end algoritmo;
library ieee;
use ieee.std_logic_1164.all;
entity registro is
port (d, clk, clr, pre
q
end registro;
: in std_logic;
: out std_logic);
Si el clr esta activo por la salida solo saldr un 0 lgico sin importar la
seal que ingrese; si pre esta activo saldr un 1 lgico en la salida sin
importar la seal de entrada y si ambas estn desactivadas solo actuara
la seal de entrada la cual para nuestro caso es el clk.
8. Implementar un circuito decodificador a 7 segmentos para un display de nodo
comn utilizando la sentencia CASE.
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(data : in bit_vector(3 downto 0);
sal : out bit_vector(6 downto 0));
end decoder;
architecture a7segmt of decoder is
begin
conv: process (data)
begin
case data is
when "0000" => SAL <= "1111110";--// 0
when "0001" => SAL <= "1100000";--// 1
when "0010" => SAL <= "1011011";--// 2
when "0011" => SAL <= "1110011";--// 3
when "0100" => SAL <= "1100101";--// 4
when "0101" => SAL <= "0110111";--// 5
when "0110" => SAL <= "0111111";--// 6
when "0111" => SAL <= "1100010";--// 7
when "1000" => SAL <= "1111111";--// 8
when "1001" => SAL <= "1110111";--// 9
when "1010" => SAL <= "1000000";--// A
when "1011" => SAL <= "0111111";--// B
when "1100" => SAL <= "1100010";--// C
when "1101" => SAL <= "1111111";--// D
when "1110" => SAL <= "1110111";--// E
when "1111" => SAL <= "1100010";--// F
end case;
end process conv;
end a7segmt;
9. Escriba
el cdigo VHDL
0,1,2,3,4,0,1,2,3,4,01...
para
implementar
un
circuito
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity de0_4 is
Port (clk :in bit;
sal :out integer range 0 to 4);
end de0_4;
architecture contador of de0_4 is
contador:
begin
process
variable cnt: integer range 0 to 4;
begin
wait until clk='1';
if cnt=4 then
cnt:=0;
else
cnt:=cnt+1;
end if;
sal<=cnt;
end process;
end contador;
10.
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity unseg is
Port ( clk : in std_logic;
reloj : buffer std_logic);
end unseg;
architecture Behavioral of unseg is
begin
process(clk)
variable cuenta: std_logic_vector(8
downto 0);
begin
if clk='1' and clk'event then
cuenta:= cuenta+1;
if cuenta = 500 then
reloj <= not reloj;
end if;
end if;
end process;
end Behavioral;
11.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY contadisplay is
port (
--pines del display HEX7
disp_hex7: out std_logic_vector(6 downto 0);
--pines de entrada de los switches SW0, SW1, SW2 y SW3
SW0, KEY0, clock:in std_logic);
end contadisplay;
--------------------------------------------------------------------------architecture solucion of contadisplay is
--seales auxiliares
signal contador1: integer range 0 to 10:=0;
signal contador1seg: integer range 0 to 25000001:=0;
signal clock1seg: std_logic:='0';
begin
-----------------------------------------------------------Proceso 1: Divisor de frecuencia para obtener un clock de
-- 1 segundo de periodo
---------------------------------------------------------proc_divf:process (clock)
begin
if clock='1'and clock'event then
contador1seg<=contador1seg+1;
if contador1seg = 25000000 then
clock1seg <= not clock1seg;
contador1seg <= 0;
end if;
end if;
end process;
-----------------------------------------------------------Proceso 2: Maquina de estados del contador
---------------------------------------------------------proc_contador: process (SW0, KEY0, clock1seg)
begin
if clock1seg'event and clock1seg ='1' then
if SW0 = '1' then
if KEY0 = '0' or contador1 = 10 then
contador1 <= 0;
else
contador1 <= contador1 +1;
end if;
case contador1 is
when 0 => disp_hex7 <= "1000000";
when 1 => disp_hex7 <= "1111001";
when 2 => disp_hex7 <= "0100100";
when 3 => disp_hex7 <= "0110000";
when 4 => disp_hex7 <= "0011001";
when 5 => disp_hex7 <= "0010010";
when 6 => disp_hex7 <= "0000010";
when 7 => disp_hex7 <= "1111000";
when 8 => disp_hex7 <= "0000000";
when 9 => disp_hex7 <= "0010000";
when 10 => disp_hex7 <= "1111111";
end case;
end if;
end if;
end process;
end solucion;
12.
13.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY control IS
PORT (
boton: IN bit;
clk: IN bit;
motor: OUT bit);
END control;
ARCHITECTURE solucion of control is
TYPE estado is (apagado1,apagado2,encendido1,encendido2);
SIGNAL presente: estado:=apagado1;
BEGIN
PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
CASE presente IS
WHEN apagado1 =>
motor<='0';
IF boton='1' THEN
presente<=encendido2;
END IF;
WHEN encendido2 =>
motor<='1';
IF boton='0' THEN
presente<=encendido1;
END IF;
WHEN encendido1 =>
motor<='1';
IF boton='1' THEN
presente<=apagado2;
END IF;
WHEN apagado2 =>
motor<='0';
IF boton='0' THEN
presente<=apagado1;
END IF;
END CASE;
END IF;
END PROCESS;
END solucion;