Circuits Syst Signal Process (2014) 33:10351051

DOI 10.1007/s00034-013-9692-2

High-Level Power Analysis for Intellectual

Property-Based Digital Systems
Yaseer Arafat Durrani Teresa Riesgo Alcaide

Received: 7 March 2013 / Published online: 28 November 2013

Springer Science+Business Media New York 2013

Abstract Power consumption in VLSI (Very Large Scale Integration) design is becoming a mainstream issue that cannot be neglected. Low power solution for SoC
(system-on-chip) flow gives designers a powerful methodology to analyze, estimate,
and optimize todays increasing power concerns.
In this paper, a new power macro-modeling technique at architectural level for the
digital electronic systems is presented. This technique allows estimating the power
dissipation of intellectual property (IP) components to their statistical knowledge of
the primary inputs/outputs. During power estimation procedure, the sequence of an
input stream is generated by a genetic algorithm (GA) using input metrics and the
macro-model function is used to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation
is performed for register transfer level (RTL) and the power dissipation is predicted
by a macro-model function. The most important contribution of the method is that it
allows fast power estimation of IP-based design by a simple addition of individual
power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our
model, we have constructed IP-based digital systems using different IP macro-blocks.
In experiments with an individual IP macro-block, the average error is 12 %, and
for an entire IP-based system with interconnects, the error is measured in the range
of 915 %.

Y.A. Durrani ( )
Electronic Engineering Department, University of Engineering & Technology, Taxila, 47050,
Pakistan
e-mail: yaseer.durrani@uettaxila.edu.pk
T.R. Alcaide
Centro de Electrnica Industrial, E.T.S.I. Industriales, Universidad Politcnica de Madrid, C/ Jos
Gutirrez Abascal 2, 28006 Madrid, Spain
e-mail: teresa.riesgo@upm.es

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Keywords Power estimation Digital system Power macro-modeling Monte

Carlo simulation Genetic algorithm Intellectual property

1 Introduction
In VLSI design, low power consumption has been made into one of the most important design goals for a wide range of electronic systems. A key challenge in the low
power systems is the accurate and fast power estimation. Hence, an estimation technique for low power is the keystone for the successful power-conscious SoC design.
As the system complexity grows rapidly and verifications become increasingly
difficult and time consuming, power and performance analysis at the early stages of
the design flow is essential for shortening the turn-around time. The design cost and
time-to-market of the electronic systems can be greatly reduced through the reuse of
predesigned circuits. In this approach, components from possibly different IP vendors
are combined to form complete programmable systems. To support the exploration of
the numerous architectural alternatives that can arise when designing IP components,
fast and accurate electronic design automation (EDA) tools are required to evaluate
key design characteristics such as timing, area and power dissipation.
The use of silicon IP has been proposed as one possible solution to the problems
associated with SoC design. Designers need to leverage pre-validated components
and IPs. Design methodology further supports IP reuse in a plug-and-play fashion,
including buses and hierarchical interconnection infrastructure. Reuse design techniques employing IP cores cut down on time-to-market, and fast estimation shortens
the design evaluation time, which is more efficiently used in design-space exploration. Power estimation models can be used at different levels of abstraction with
corresponding variations in speed and accuracy.
Power analysis of an IP-based system is a particularly challenging task at the architecture level because designers need to compute accurate power estimates without
direct knowledge of IP design details. With the wide deployment of portable systems, low power chip design is becoming an increasingly important focus of VLSI
research. Thus, at the architecture level, the development of efficient and effective
power estimator for IP-based systems is important and urgent to the VLSI design
communities [14, 17].
In response to this need, the power macro-modeling technique is a promising solution to solve the problem of high-level power estimation. The macro-model construction consists in generating a mapping between the power dissipation of a circuit and
certain statistics of the input signals. This technique has been proven to be effective
for individual IP components building IP power models [17]. The urgent need of a
feasible IP power model is becoming more useful in recent years. The application
of power macro-modeling on the IP blocks of an entire system requires knowledge
of the signal statistics among the different IP blocks. To obtain this information, the
designer must perform different functional simulations.
In this paper, we present a power estimation methodology at RTL based on the
macro-modeling technique applied to IP-based systems. Various power estimation
techniques have been introduced previously. They can be divided into two categories:

Circuits Syst Signal Process (2014) 33:10351051

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probabilistic and statistical. Probabilistic techniques use the probabilities of the input
stream and their propagation into the circuit to estimate the internal switching activities of the circuit [4, 18, 19]. These techniques are very efficient, but they cannot accurately capture factors like glitch generation, propagation, etc. On the other hand, in
statistical techniques the circuit is simulated under randomly generated input patterns
and the power dissipation is monitored using a power estimator. Therefore, the power
values obtained are used to estimate the power consumption for every input stream.
For accurate power estimation, we need to produce a required number of simulated
vectors, which is usually high and causes a run-time problem. To handle this problem,
a Monte Carlo simulation technique was proposed that uses input vectors randomly
generated to obtain the power values [2, 12]. Several samples combined with previous ones are required to determine whether the entire process needs to be repeated
in order to satisfy given criteria. Most of the existing approaches of statistical power
estimation consider the input signal probabilities and their average switching activities of the input signal and use signal probabilities propagation methods to estimate
the internal switching activities [10]. In those approaches, there is no guarantee that
the estimated power keeps any relation to the real dissipation of the circuit. To solve
this problem, a look-up table (LUT) based macro-model was presented in [11] and
further improved in [13] that stores the equi-spaced discrete measured power values
of the input signal statistics. The interpolation method was introduced in the case the
input statistics do not correspond to any value stored on the LUT. The interpolation
scheme was improved by using the power sensitivity concept [3]. For better accuracy,
numerous power macro-modeling techniques have been introduced in [1, 15, 16].
In our recent work, we introduced temporal correlation Tin that captures those features which are missed on signal probability Pin , transition density Din , and spatial
correlation Sin [58]. In this paper, we continue our previous research in developing power macro-modeling technique based on the power estimation methodology.
The input/output (I/O) metrics of our macro-model are the average input signal probability Pin , average input transition density Din , input spatial correlation Sin , input
temporal correlation Tin , average output signal probability Pout , average output transition density Dout , output spatial correlation Sout , and output temporal correlation
Tout . In the experiments, our macro-model f (.) in Eq. (15) is evaluated on two different IP-based test systems. The most important contribution of our new method is that
it allows fast power estimation of an IP-based design by a simple addition of individual power consumptions. This makes the power modeling of SoCs an easy task that
permits evaluation of power features at the architectural level. Finally, we performed
detail statistical error analysis in Eq. (17) to find non-affective input metrics in each
test system individually and developed a new macro-model with only affective metrics in Eq. (18) and Eq. (19). The average error with an individual IP macro-block
is 12 %, and for the entire test system (with macro-blocks and interconnects), the
average error is estimated to be 915 %.
The rest of this paper is organized as follows. In Sect. 2, we give the background
of input/output metrics of our power macro-model. In Sect. 3, we propose the power
estimation methodology for IP-based test systems. Our macro-model is evaluated in
Sect. 4, and Sect. 5 summarizes our work.

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Fig. 1 Extraction of input/output metrics

2 Macro-modeling Background
One of the most challenging aspects in the construction of a power macro-model
is the choice of the models input parameters, or metrics. These metrics should be
capturing the features that are primarily responsible for a systems dissipation and
can thus help in obtaining good estimates of its power dissipation. We focus on
the problem of statistical power macro-modeling at register transfer level for IPbased designs. Our model is LUT based. The I/O metrics of our macro-model are
Pin , Din , Sin , Tin , Pout , Dout , Sout , and Tout .
Once the I/O metrics are selected, the input sequences are computed by our genetic
algorithm (GA) [9] while output metrics are extracted from the functional simulations
using a simulator as shown in Fig. 1. This section describes and motivates the metrics
of our macro-model.
2.1 Characterization
Our power macro-model uses statistical techniques and it estimates the average power
dissipation for a digital system. We first introduce some definitions in this approach
and then present the macro-modeling methodology.
The IP macro-blocks are simulated under different sample streams with Pin , Din ,
Sin , Tin . Given an IP macro-block with the number of primary inputs r and the input
binary stream q = {(q11 , q12 , . . . , q1r ), (q21 , q22 , . . . , q2r ), . . . , (qs1 , qs2 , . . . , qsr )} of
length s, these metrics are defined using Eqs. (1), (2), (3), and (4) as follows [11, 13,
16]:
Definition 1 The signal probability P (x) in Eq. (1) of a node x in the circuit corresponds to the average fraction of clock cycles with a period of T in which the node

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has a steady state logic value of ONE:

r

s

i=1

P (x) =

j =1 qij

r s

(1)

The signal probability is used for accurate estimation of a signal activity. Therefore, it
is essential to accurately calculate the signal probability for further use in estimating
activity.
Definition 2 The transition density D(x) in Eq. (2) is defined as the average number
of transitions from 0 1 and 1 0 per unit time:
r
D(x) =

j =1

s1

i=1 qij

qi+1j

r (s 1)

(2)

Every signal in a logic circuit can be related to a statistical process. Input correlation plays a significant role in power dissipation, especially when the circuit is part
of a wide data-path. We have therefore decided to incorporate input correlation to
the metrics of our model. To capture temporal and spatial correlations, we consider
correlation metrics S(x) and T (x).
Definition 3 Two (or more) signals are spatially correlated as given by S(x) in
Eq. (3) if the values that one assumes are dependent on the values of the other. Two
signals are called spatially independent if they are not spatially correlated. In other
words, we compute the average of the bit-wise XNOR between all possible channel
streams qi = {(q1i , q2i , . . . , qsi )} and qj = {(q1j , q2j , . . . , qsj )} in the stream:
r
S(x) =

j =1

r
k=1

s

i=1 qij

qik

s r (r 1)

or S(x)ij = P {xi xj = 1}

(3)

where xi and xj are the input signals, i.e., S(x)ij is the probability of both inputs
being high simultaneously. Even though the joint probability is not what is usually
referred to as correlation coefficient between two random variables, in this case of
Boolean variables the joint probability of two bits is enough to capture their complete
joint distribution and, therefore, suffices as a measure of their correlation. These four
variables are not independent. The symbol denotes XNOR in Eqs. (2) and (3).
Definition 4 A signal is temporally correlated as given by T (x) in Eq. (4) if the value
that it assumes on the next clock cycle is dependent on its present and (or) previous
values. In other words, the input stream has its next value depending on its current
value and on previous values.
For a given channel stream of length s, the convolution with an arbitrary window
Yj of length t from the channel stream qj is used to compute:
r
T (x) =

j =1

st+1
t1

r s

(yj qj )

(4)

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Circuits Syst Signal Process (2014) 33:10351051

where is the convolution. Each term in the convolution represents the number of
times that two signals are simultaneously high. Each term indicates how well the
chosen subset is reproduced in the sequence, and therefore provides an estimate of
the signals temporal correlation.
2.2 Input Macro-modeling for IP-Based Macro-blocks
Similar power macro-modeling techniques were presented in [11, 13, 15]. Our macromodel consists of LUT based approach. This model estimates the average power
dissipation PIP_avg of IP macro-block using Eq. (5):
PIP_avg = f (Pin , Din , Sin , Tin ).

(5)

The macro-model function f (.) in Eq. (5) is obtained by a given IP macro-block

which maps the space of input signal properties to the power dissipation of a circuit.
When the input metrics of f (.) are solely determined by the input signals, the computation of power estimates is a straightforward and fast function evaluation. The most
commonly used templates for the macro-model function f (.) are low-order polynomial functions. For a kth order complete polynomial function with n input paramek
ters, a total of Sn+k
coefficients need to be computed. Using Eqs. (1), (2), (3), and
(4), input metrics in Eqs. (6), (7), (8), and (9) can be defined as:
r s
i=1
j =1 qij
,
(6)
Pin =
r s
r s1
j =1
i=1 qij qi+1j
Din =
,
(7)
r (s 1)
r s1 s
i = 1qij qik
j =1
k=1
Sin =
,
(8)
s r (r 1)
r st+1
j =1
t1 (yj qj )
Tin =
.
(9)
r s
In the estimation procedure, the actual signal statistics are derived and applied to f (.)
in Eq. (5) to compute the power estimate. The power sensitivity of the input metric R
shows how R affects P and is defined in [3] as:
P
.
R0 R
lim

(10)

In the characterization phase, the high sensitivity of R can be used to increase the
accuracy of the power macro-model. Given an analytical expression f (.), the power
sensitivity can be calculated by taking partial derivatives of f (.).
2.3 Output Macro-modeling for IP-Based Macro-blocks
Output macro-modeling was first introduced in [17], and we further improved it in [5,
6] to predict output metrics of an individual IP block from input metrics. In the characterization step, the functional simulation of the circuit is performed with different

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input sequences to obtain output metrics as shown in Fig. 1. The function f (.) in
Eq. (5) can be used to construct a set of functions fA , fB , fC and fD that map the
input metrics of a macro-block to its output metrics Pout , Dout , Sout , Tout which are
derived in Eqs. (11), (12), (13), and (14):
Pout = fA (Pin , Din , Sin , Tin ),

(11)

Dout = fB (Pin , Din , Sin , Tin ),

(12)

Sout = fC (Pin , Din , Sin , Tin ),

(13)

Tout = fD (Pin , Din , Sin , Tin ).

(14)

Similar to power sensitivity in Eq. (10), the sensitivities of an output metrics with
respect to Pin , Din , Sin , Tin is defined as partial derivatives of the corresponding function fi .
2.4 Monte Carlo Simulation
The Monte Carlo approach for power estimation was first proposed by F. Najm [2]
and further improved in [11, 13]. Using the same approach, our genetic algorithm
generates the corresponding logic input waveforms according to the Pin , Din , Sin , Tin
values. Then the method estimates the average power by sampling those input waveforms with certain length l and feeding them into the simulator to derive a sample
value. The average power consumption can be estimated with the average of several
sample values. We performed a Monte Carlo zero-delay simulation for the digital IPbased test system and obtained the power dissipation by our macro-model function.
The interpolation can be applied (to improve the power sensitivity concept), if the
input metrics do not match their characteristics scheme [3].

3 Power Macro-modeling for IP-Based Digital Systems

Several approaches have been proposed to construct power macro-models on ISCAS85 benchmark circuits [2, 11, 13]. We have observed that the same methodology
works as well for different IP macro-blocks such as array multipliers, comparators,
delay elements (shift registers), adders in terms of the statistical knowledge of their
primary I/O.
Recently, we have presented a macro-model for different IP blocks [5, 6]. The
proposed methodology was described as follows: In our statistical power macromodeling procedure, the sequence of an input stream was generated for a desired
input metrics: Pin , Din , Sin , Tin . Then using functional simulations and a power estimator, the output stream sequence and the average power dissipation PIP_avg were
extracted by the output waveforms of the IP macro-block. In our macro-model, we
use the LUT approach. The LUT consists of a table where the axis represents I/O
signal statistics and each table entry represents a power value. The LUT stores the
estimates for equi-spaced discrete values of the I/O signal statistics. For each entry
in the table, an equation is built by means of linear regression. At this moment, the

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Fig. 2 Two different IP-based test systems

power function in Eq. (5) can be defined. All this process is divided in two steps. In
the first step, the metrics of the I/O sequences are computed by our GA and the power
function is obtained using PIP_avg in Eq. (5). The interpolation scheme can be applied (to improve power sensitivity concept) if the input metrics do not match based
on their characteristics. In the second step, a Monte Carlo zero-delay simulation is
performed with different sequences of their signal statistics to evaluate the quality of
the power function PIP_avg. At the end, we get the power results.
In this section, we continue our previous work and present the application of the
statistical power estimation method for different IP-based test systems. In our preliminary work, the approach intended to reduce the intensive amount of simulations at a
higher abstraction level. We used the same IP blocks and their macro-model information for our IP-based systems [68]. Now, instead of simulating every IP block, we
applied the Monte Carlo zero-delay simulation to the entire test system. These macroblocks are connected together to construct the two different IP-based test systems as
shown in Fig. 2.

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1043

The application of the power macro-modeling on each IP block requires knowledge of the input signal statistics among these blocks. To obtain this information, different functional simulations need to be performed with different input statistical values of each IP macro-block. For example, in Fig. 2(a), the inputs of the block IP-1A
are the inputs of the test system I, while the outputs of IP-1A are the inputs of IP-1B,
and IP-1C IP blocks can be used as input signal statistics of the reference and so on.
The output signal statistical information for each IP block can be used as input signal
statistics of the reference connected IP macro-block. For IP-1A block, we generate
random input vectors with 25 different values using input metrics Pin , Din , Sin , Tin .
Then to construct the LUT, the test IP system is simulated 25 times, and for each IP
block 25 different values of input metrics are measured using functional simulations.
The average power dissipation Psystem is extracted using Eq. (15):
Psystem =

n


PIPi_avg .

(15)

i=1

We compare the estimated power Psystem in Eq. (15) with the simulated power estimation to evaluate the accuracy of the power macro-model function in Eq. (5).

4 Experimental Results
In this section, we show the results of our LUT based power macro-modeling approach. We have implemented this approach and built the power macro-model at the
architecture level. The accuracy of the proposed model is evaluated for two different IP-based test systems as shown in Fig. 2. For each IP macro-block, a random
sequence of test patterns is performed with different values of Pin , Din , Sin , Tin . The
function f (.) in Eq. (5) is used to construct to a set of functions fA , fB , fC and fD
in Eqs. (11), (12), (13), (14) that map the input metrics of a macro-block to its output
metrics Pout , Dout , Sout , Tout . During the characterization phase, the average power
consumption measured with the power function f (.), while using least squares fitting, is used to perform linear regression. The chosen input sequences are highly
correlated and they are generated by our new method. The accuracy is tested running
gate-level and RTL simulations. The power is estimated using the Monte Carlo zerodelay simulation technique. We compare our power macro-modeling results Pestimated
with Synopsys Power Compiler tool Pestimated and compute the average absolute and
maximum percentage errors using Eq. (16). Figure 3 demonstrates the method of
finding the error between the simulated and estimated power values.
The experimental results show that the randomly generated sequences have relatively accurate statistics and high convergence. For the verification of our random
sequences, we compared our power results with the functional sequences power results and found around 96 % correlation. Both random and functional sequences have
similar input features. Several 8, 16, 32 bit wide sequences were generated. We carried out a synthetic validation by applying a uniform set of stochastically generated
test-benches. All the results to be presented were obtained with 5 % error-tolerance
( = 0.05) and 95 % confidence ( = 0.05).

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Fig. 3 Power comparison between simulated and estimated power

Our pattern generator can generate a set of sequences over the entire space range
between [0, 1]. Therefore, it enables us to perform extensive experiments to reveal
the relation between IP design power dissipation and specific statistics of the input signals. In our study, we designed different IP macro-block/modules. For each
block, we generated from 350 to 1000 sequences with Pin , Din , Sin , Tin evenly distributed in the four/eight-dimensional space. Our parameter granularity is 0.1 over
the entire space. In practice, much larger sequences should be used for larger circuits.
Roughly speaking, for a given IP module, empirically we observe that sufficiently
long input sequences which produce similar steady state power exhibit similar total
power. Given an IP module, for all the input sequences that produce a steady state
power, we believe that hazardous power corresponding to input sequences has the
behavior of a random variable. Furthermore, among all these input sequences that
produce a steady state power, longer sequences tend to have smaller variance than
shorter sequences. As an example, given a three input logic network, consider sequences Seq1 = {101, 111}, Seq2 = {100, 110}, Seq3 = {110, 011, 010, 011, 101, },
Seq4 = {011, 101, 110, 110, 111, }, etc. They all exhibit the same steady power. We
believe that hazardous power produced by all these sequences, such as that by Seq3
and Seq4 , has a smaller variance than for shorter sequences, such as Seq1 and Seq2 .
Perror =

|Psimulated Pestimated |
100 %.
Psimulated

(16)

In Table 1, we illustrate a set of the input vectors and the average relative errors of
the estimated values obtained with our macro-model. It is evident from this table that
the function is more accurate estimating the average power in some cases than others. For the input metrics Pin , Din , Sin , Tin , we specify the range between [0, 1]. The

Circuits Syst Signal Process (2014) 33:10351051

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Table 1 Accuracy of power estimates

IP macro block

Using input metrics

Using input/output metrics

Average
error

Max
error

Average
error

Max
error

IP-1A

0.60 %

2.96 %

0.68 %

3.01 %

IP-1B

0.29 %

1.10 %

0.31 %

1.40 %

IP-1C

0.73 %

1.57 %

0.74 %

1.67 %

IP-1D

0.47 %

0.66 %

0.50 %

0.78 %

IP-1E

1.38 %

2.36 %

1.30 %

2.66 %

IP-1F

2.15 %

2.87 %

2.35 %

2.17 %

IP-1G

1.00 %

1.54 %

1.10 %

1.14 %

IP-1H

0.91 %

2.12 %

0.71 %

2.01 %

Average error

0.94 %

1.90 %

0.96 %

1.86 %

IP-2A

0.96 %

3.12 %

0.76 %

2.36 %

IP-2B

1.79 %

3.83 %

1.53 %

3.02 %

IP-2C

0.90 %

4.19 %

0.60 %

2.99 %

IP-2D

1.40 %

1.83 %

0.94 %

1.71 %

IP-2E

4.17 %

5.21 %

3.57 %

4.81 %

IP-2F

1.25 %

2.56 %

0.65 %

2.31 %

IP-2G

2.95 %

3.30 %

2.15 %

3.01 %

IP-2H

3.22 %

5.20 %

2.92 %

4.70 %

IP-2I

1.34 %

3.67 %

0.94 %

2.84 %

IP-2J

2.35 %

3.89 %

1.23 %

2.95 %

IP-2K

2.56 %

3.84 %

1.21 %

2.83 %

IP-2L

1.04 %

1.23 %

0.24 %

1.11 %

Average error

1.94 %

3.49 %

1.40 %

2.89 %

Test system-I

Test system-II

given input metrics values are more accurate for the specified range [0.2, 0.8] and less
accurate in [0, 0.2] and in [0.8, 1]. Our macro-model do not estimate the power consumption of interconnects among different IP macro-blocks. One important source of
error comes due to interconnects and other factors like glitch activities. For an individual IP block, we measured just 12 % error in [5, 6]. It is evident from the Table 1
that the macro-model function f (.) is accurate for estimating the average power for
IP macro-blocks such as array multipliers, adders, registers, and comparator circuits.
The individual IP block consists of 5005000 logic gates. In Table 1, the first column
shows the name of the macro-blocks. The four-dimensional input model estimates the
absolute average and maximum relative error which are shown in columns 2 and 3.
In our experiments, the average absolute error of the test system I and system II is
0.94 % and 1.94 %, while the average maximum error is 1.90 % and 3.49 %, respectively. Columns 4 and 5 give the average and maximum relative error for the estimates
obtained with the eight-dimensional input/output model. The average absolute error
for both systems is 0.96 % and 1.40 %, while the average maximum error is 1.86 %

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Circuits Syst Signal Process (2014) 33:10351051

Fig. 4 The correlation graph between the input and input/output metrics-based models

and 2.89 %, respectively. We found that considering output metrics in the macromodel can only improves 25 % accuracy. These results mirror those obtained for
power dissipation, showing that our technique could be used effectively to achieve
fast and accurate results in the early stage of the digital system design. But for the
entire IP-based system with interconnects, the error increases to 2030 %. This error
can be reduced by different techniques that improve the data-path of interconnects
among IP macro-blocks. In our experiments, the average error of the entire IP-based
test systems I and II is found to be 22.15 % and 27.64 %, respectively.
The minimum simulations length can be determined through convergence analysis. Considering the average power figure helps us identify the minimum length necessary for each simulation to converge which happens when the power consumption
gets close to a steady value given an arbitrary acceptance threshold. Also the convergent sample size is not a function of the circuit size, it depends on how widely the
power distributes. Regression analysis is performed to fit the models coefficients. For
the IP-based test systems I and II, we measured the correlation coefficient of 96 % and
87 %, respectively. Figure 4 demonstrates the 98 % correlation between the input and
the I/O metrics based macro-models. For different blocks, the prediction correlation
coefficient is measured around 97 %, which is quite good. Using the macro-model
function f (.), the output metrics do not significantly improve the average error, but
do improve the average maximum relative error. We have also noticed that the output
metrics effectively improve the error for the multiplier macro-blocks, while for the
comparator blocks the results become worse. For the individual IP characterization,
this would result in an increased processor time if I/O parameters were considered.
The results show that the transition density Din is very effective when estimating power dissipation and relatively linear to the power measures. In some cases, the
temporal/spatial correlations Tin , Sin do not significantly affect power dissipation and
are less sensitive than Din . While in other cases, neglecting correlation metrics at the
primary inputs causes inaccurate values for Pin and Din . To demonstrate the correlation impact, we performed simulations for different IP macro-blocks with different
sequences of input vectors. For example, every input was fixed to Pin = 0.50 for the
four simulations. The Din of primary input was set to 0.50 for the first simulation,
0.25 for the second, 0.10 for the third, and 0.02 for the fourth. A randomly generated

Circuits Syst Signal Process (2014) 33:10351051

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Fig. 5 Correlation between input metrics and error: (a) Test System I, (b) Test System II

uncorrelated input pattern was set to have energy E = 0.50. Thus, the first simulation
determines Din at internal signals with correlation of input increases. With decreasing
Din at inputs, the correlation of input increases. Techniques that neglect correlation
at inputs produce the same values for the transition probability of an internal signal
regardless of the actual transition probabilities at inputs, i.e., these techniques yield
the result of the first simulation for any assignment of E to the inputs. Therefore
E = 0.50 at the inputs is compared to the simulation E = 0.50 at the primary inputs.
4.1 Statistical Error Analysis
It is crucial to understand that all measurements of experiments are subject to uncertainties. It is never possible to measure anything exactly. In order to draw valid
conclusions, the error must be indicated and dealt with properly. Therefore, we performed statistical analyses to compute the error on the basis of various statistical tests,
including standard normal distribution, correlation, covariance, and variance analyses
with multivariate graphs, which give an interesting view into the results of our experiments. A multiple regression model is used to describe the relationship between the
error and four input variables in Eq. (17):
= 0 + 1 Pin + 2 Din + 3 Sin + 4 Tin

(17)

where is the error and 1 , 2 , 3 , 4 are the coefficients of input variables.

Figure 5 and Table 2 describe the relationship between the error and input variables
(Pin , Din , Sin , Tin ) of the two test systems discussed in Sect. 3. Table 2 demonstrates
the Pearson product-moment correlation between each pair of the variables giving
a value between +1 and 1 inclusive and measuring the strength of the linear relationship between two variables. The number of pairs of data values that are used to
compute each coefficient is also shown. We found strong correlation for the following

1048
Table 2 Relationships between
input metrics and error

Circuits Syst Signal Process (2014) 33:10351051

Variables

Error

Din

Pin

Sin

Tin

0.01

+0.95

+0.69

+0.84

+0.78

0.01

+0.97

+0.90

+0.85

0.01

0.03

0.09

+0.88

+0.67

Test System I
Error
Din

0
+0.95

Pin

0.01
+0.69

+0.97

Sin

0.03

+0.84

+0.90

+0.88

0.09

+0.78

+0.85

+0.67

+0.87

0.15

0.20

+0.96

+0.51

+0.35

+0.15

0.03

0.75

0.79

+0.90

0.11

0.16

Tin

+0.87

Test System II
Error
Din

Pin

0.15

0.03

+0.51

+0.90

Sin

0.20

0.75

0.11

+0.35

+0.63

Tin

0.31

0.79

+0.15

+0.96

0.31

+0.63

+0.47

0.16

+0.47

+0.92

+0.92

pairs of variables: in test system I, ErrorDin , ErrorSin , ErrorTin , Din Sin , Din
Tin , Sin Tin ; and in test system II, ErrorDin , Sin Tin . In Table 3, we illustrate the
statistical error analysis results to find the P -value. The P -value tests the statistical
significance of the estimated correlations. The P -values less than 0.05 statistically
indicate the significance of non-zero correlations at the 95 % confidence level. Other
inputs are not significant if the P -value is greater than 0.05. The important results for
both systems are given below:
Test system I: In Table 3, the first column shows the input variables of Eq. (17).
The second column demonstrates the standard error of the estimates with standard
deviation of the residuals, which is found to be 1.61. This value helps us construct
prediction limits for new observations. In the third column, the R-squared statistics
indicates that the model is fitted 90.20 % of the variability in error. The adjusted
R-squared statistics, which is more suitable for comparing models with different independent variables, is found to be 88.23 %. The mean absolute error of 1.14 is the
average value of the residuals. In fifth column of the table, we found the P -value of
Din to be 0.00, so there is a statistically significant relationship between the variables
at the 99 % confidence. Therefore, Din is the only significant parameter in the error,
which is the main factor of the power consumption for interconnections among IP
blocks, while other input variables (Pin , Sin , Tin ) are not very influenced in Eq. (17)

Circuits Syst Signal Process (2014) 33:10351051

Table 3 Statistical Error
Analysis for IP-based test
systems

Parameter

1049
Standard
estimates

R-squared
statistics

Total
error

P -value

0.19

Test System I
Constant

5.16

1.37

3.76

Din

18.24

6.16

2.96

0.00

Pin

0.06

0.07

1.18

0.95

Sin

0.27

0.09

3.03

0.93

Tin

2.58

0.61

4.24

0.55
0.00

Test System II
Constant

10.21

3.39

2.62

Din

4.56

2.07

1.20

0.04

Pin

1.51

1.03

1.04

0.17

Sin

3.45

1.02

3.36

0.32

Tin

11.95

2.51

4.76

0.02

for this particular test system. Hence, our model in Eq. (18) can be further simplified
as:
= 0 + 1 Din .

(18)

Figure 6(a) illustrates the correlation between the simulated power, estimated
power and the estimated corrected power values. After introducing the simplified
model in Eq. (18), we measured further improved correlation coefficient from 96 %
to 99 %. For the entire system, the average error is also improved from 22.15 % to
9.23 %.
Test System II: In the second column of Table 3, the standard deviation of the residuals is found to be 1.21. In the third column, the R-squared statistics indicates that
the model is fitted with 34.72 % of the variability in error. The adjusted R-squared
statistics with different independent variables is 20.21 %. The mean absolute error of
0.83 is the average value of the residuals. In the fifth column of the table, we found
the P -value of Din and Tin to be 0.04 and 0.02, respectively. It means that there is
a statistically significant relationship between the variables at the 9698 % confidence. Therefore, Din and Tin are the only significant parameters in the error, which
are the main factors of power consumption for interconnections among IP blocks,
while other input variables (Pin , Sin ) are not influenced in Eq. (17) for this particular
IP-based test system. Hence, our model in Eq. (19) can be further simplified as:
= 0 + 1 Din + 2 Tin .

(19)

Figure 6(b) illustrates the correlation between the simulated power, estimated
power and the estimated corrected power values. After introducing the simplified
model in Eq. (19), we observed the correlation coefficient decrease from 87 % to
85 %. For the entire system, the average error was improved from 27.64 % to 15.25 %.

1050

Circuits Syst Signal Process (2014) 33:10351051

Fig. 6 Correlation between Estimated, Simulated and Estimated-Corrected power: (a) IP-based Test System I, (b) IP-based Test System II

5 Conclusions
The main goal of power estimation is to optimize the power consumption of the electronic system design. Power is a strongly pattern-dependent function. Input statistics
greatly influence the average power. We solve the pattern dependence problem for IP
designs.
We have presented a new power macro-modeling technique for high-level power
estimation applied on two different IP-based test systems using several IP macroblocks. In our preliminary work, for individual IP blocks, we measured just 12 %
error. But for the entire IP-based system with interconnects, the error is measured in
the range of 2030 %. This is because the macro-model should consider the power
consumption of interconnects among different IP macro-blocks and other factors like
glitches. We demonstrated relatively better accuracy in some cases. Our improved
statistical model showed an average error of 915 % and a correlation coefficient of
9685 %. We found that considering output metrics in a macro-model can improve
the accuracy by only 25 %. Currently, we are evaluating our macro-model on more
complex IP-based systems and working to further improve its accuracy.

Circuits Syst Signal Process (2014) 33:10351051

1051

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