Variability in Nanoscale CMOS

Technology
David J. Frank
12/3/09
International Winter School for Graduate Students
IIT, Bombay, India

IBM Watson Research Center

Headquarters of the
Research Division
Yorktown Heights, NY
~1500-2000 people

Outline
1. Introduction
2. Sources and Types of variations
3. Specific Issues
z Doping
z Lithography
z Thermal
z Others
4. Consequences for circuits
5. Conclusions

Acknowledgements: A. Asenov, T. Brunner, B. Linder, S. Rauch

3

Example 1

45nm HKMG bulk CMOS technology

[From K. Mistry, et al. (Intel), 2007 IEDM, p.247]

Example 2 - Variations in Simulated IV Curve

VDS=0.7 V
Leff=11 nm

[D. Frank, IBM JRD 2002.]

Example 3 - How thick is this oxide?

Sources of Variations
1. Process variations Variations due to lack of perfect control of the
fabrication process. No two devices or structures are
exactly the same at the atomic level.

2. Environment variations Variations due to lack of perfect control over the

environment (temperature, voltage, etc.) in which the
circuit must operate.

3. Temporal variations Variations which cause the device to behave differently

at different times. Hot electron degradation, for
example.
7

Types of Variations
1. Global
Variations in the mean value of a parameter for the
entire chip.
2. Local
Device-to-device variations within any single chip.
3. Across-chip
Variations in average device parameters from one
part of a chip to another.

This distinction is important because these types

require different statistical treatment for proper
determination of impact on yield.
8

Matrix of Variations
Sources of Variations

Types of Variations

Process

Environment

Temporal

Operating temperature range,

VDD range

<NBTI> and
Hot electron shifts

Local

Line Edge
Roughness (LER),
Discrete doping,
Discrete oxide
thickness,
R and VBODY
distributions

Self-heating,
IR drops

Distribution of NBTI,
Voltage noise,
SOI VBODY history
effects,
Oxide breakdown
currents

Acrosschip

Line Width, due to

pattern density
effects

Thermal hot spots

due to nonuniform
power dissipation

Computational load
dependent hot spots

Global

<LG> and <W>,

<layer thicknesses>,
<R>'s,
<doping>,
<tOX>,
<VBODY>

The ones Im going to talk about

Sources of Variations

Types of Variations

Process

Environment

Temporal

Operating temperature range,

VDD range

<NBTI> and
Hot electron shifts

Local

Line Edge
Roughness (LER),
Discrete doping,
Discrete oxide
thickness,
R and VBODY
distributions

Self-heating,
IR drops

Distribution of NBTI,
Voltage noise,
SOI VBODY history
effects,
Oxide breakdown
currents

Acrosschip

Line Width, due to

pattern density
effects

Thermal hot spots

due to nonuniform
power dissipation

Computational load
dependent hot spots

Global

<LG> and <W>,

<layer thicknesses>,
<R>'s,
<doping>,
<tOX>,
<VBODY>

10

Scaling

The simulation
paradigm in 2000
A 22 nm MOSFET
In production soon
A 4.2 nm MOSFET
In production 2023
A. Asenov, University of Glasgow
11

How should a MOSFET be described?

H2O

C60

Chemistry
Si1156320O44934N48620Hf19607Ti42900As871B174

Continuum physics

12

Discrete dopant variations

The number of dopant atoms in
the depletion layer of a MOSFET
has been scaling roughly as
Leff1.5.

Statistical variation in the number

of dopants, N, varies as N1/2,
causing increasing VT uncertainty
for small N.

249,403,263 Si atoms
68,743 donors
13,042 acceptors

[D. J. Frank, et al., 1999 Symp. VLSI Tech.]

13

Behavior of discrete dopants

The potential due to an ionized dopant:
~ 1/ r
In 3D, isolated:
In a doped region, with carriers around:
screened by Debye length: ~ e r /
In depleted region, with a 2D conductor
nearby, dipole screening: ~ 1 / r 2

14

Impact on channel potential

Ionized dopants close to the channel create
large local potential barriers

Potential in the plane of the channel

of a simulated FET

Ionized dopants far from

the channel contribute low,
broad potential barriers.

[from Glasgow group]

15

Simulating discrete doping effects

16

17

Analyzing the variation of IV curves

I-<V>
mean VT

I0=2 nA
Continuum VT
Continuum IV

IV curves simulated
in 3D with
FIELDAY.
100 different
instances.

Determine VT shifts from subthreshold IV curves.

Measure shift between the VT for continuum doping and the
mean VT for stochastic doping.
Determine VT from the VT distribution for the stochastic
cases.
18

19

20

Random dopant placement creates

uncertainty in source/drain edge

[D. J. Frank and H.-S. P. Wong, IWCE, May

2000]

21

Threshold uncertainty versus

source/drain depth

Fluctuations due to source/drain discrete doping are negligible except for

deepest junctions.
Dominant effect is increasing body doping to maintain VT.
[D. J. Frank, et al., Symp. VLSI Technol., p.169, 1999]

22

Dependence of VT Variation on Width

Two cases have been studied:

[D. J. Frank, IEEE 2003 SOI Short Course]

23

Dependence of VT Variation on Width

Model for case with
oxide end caps:
Two FETs in
parallel

D
G

S
edge:

center:

w=wedge

w=wtot-wedge

<VTedge>

<VTcntr>

VTedge

VTcntr

This 'fit':
wedge=8 nm

<VTedge>-<VTcntr>=-88 mV
VTedge=40 mV

[D. J. Frank, IEEE 2003 SOI Short Course]

24

VT variation in ultra-small nFETs

Doping Density

Doping profile design is scaled from a previous 25 nm design by Y. Taur.

Gate insulator is 1 nm Al2O3.
Body is forward biased to achieve low VT: VBS=VDD=0.7 V.
Temperature is -40 C.

[D. J. Frank and H.-S. P. Wong, IWCE, May 2000]

25

Large Asymmetric Threshold Voltage

Distribution in Ultra-Small MOSFETs

VDS=0.7 V
Leff=17 nm

VDS=0.7 V
Leff=11 nm

VT at
ID=0.88
A

VT at
ID=1.36
A

VT=23.1 mV

VT=52.2 mV

Distributions are asymmetric, especially for very short channels.

D. J. Frank, IBM J. Res. Devel., 46, March/May 2002.

26

Examples of Potential Profiles for Worst

Case VT Shifts in 17 nm nFETs
0.4

0.050

0.4

0.050

0.0

Y (um)

-0.4

0.025

0.0

Y (um)

-0.4

0.025

-0.8

-0.8

0.000
0.05

0.000
0.07

0.09

0.05

X (um)

0.07

0.09

X (um)
0.4

0.050

0.4

0.050

0.0

0.0

Y (um)

-0.4

0.025

Y (um)

-0.4

0.025

-0.8

-0.8

0.000

0.000
0.05

0.07

X (um)

0.09

0.05

0.07

0.09

X (um)

[D. J. Frank and H.-S. P. Wong, IWCE, May 2000]

27

28

Example Data: Test Measurements on

a Large Array of Experimental FETs
VT measurements on ~4000
identical SOI nFETs at each
(W,L) dimension, all in a single
experimental macro.
[Collaboration with B. Linder.]
350

# of devices = 3481

300 = 25.58 mV
Vt

L=46 nm
W=122 nm

Standard Deviation (V)

Standard Deviation
for various drain voltages (W=245nm)
0.03

0.05 V

0.025

0.25 V

0.02

0.45 V

0.85 V

0.01

1.05 V

0.005
0.046

0.0723

0.116

0.221

0.4835

Gate length (um)

Standard Deviation

250

150
100
50
0
175 200 225 250 275 300 325 350 375

Threshold Voltage (mV)

Standard Deviation (log) (V)

for various drain voltages (Lgate=46nm)

200

Count

0.65 V

0.015

0.04
0.05 V
0.25 V
0.45 V
0.65 V
0.85 V
1.05 V

0.01
0.1

Width(log) (um)

29

Oxide thickness variations

Asenov, Kaya and Davies, IEEE TED 49, p.
112 (2002)
Oxide
interface
30 x 30nm

Electron
density
contour

Continuous doping,
NA=5x1018 cm-3

30 x 30nm

Potential
contours

OTV=Oxide thickness variation, DF=doping fluctuations

30

Ultra-thin SOI MOSFETs

For very thin SOI layers, the discrete number of atomic layers of
Si is expected to exhibit statistical variation. Simulations show
that this leads to additional VT variations.

Potential in center of channel

Conventional simulation

Density gradient QM corrected

[A. Brown, et al., 2003 NPMS and SIMD, Maui,

31 HI]

Functional dependence of VT

T. Mizuno, et al.

P. Stolk, et al.

P. Wong and Y. Taur

Asenov, et al., fit to large set of data.

But note that 1/sqrt(L) dependence can only be expected for laterally
uniform doping.
Long channel devices may not obey 1/sqrt(L), if most of the variation
arises from halos that are shorter than gate length.

32

Takeuchi model

Takeuchi, et al., 2007 IEDM

33

34

Gate oxide variability and reliability

Oxide thickness
profile

[S. Markov, 2006 SSDM, Glasgow Univ.]

35

Lithographic Sources of Variations

Global Variations
A. Imperfect Process Control
Critical Dimensions are sensitive to:
zfocus
zdose (intensity and time)
zresist sensitivity (chemical variations)
zlayer thicknesses
Intensity is modulated by interference effects, which are strongly
dependent on layer thicknesses.
Anti-reflection coatings (ARC) are
used, but there is still sensitivity.

[K. Ausschnitt, et al., 2003 AMM Conf.,

T. Brunner, et al., Proc. SPIE 2001 Micro]

36

Global Lithographic Variations - continued

B. Errors in Alignment, Rotation and Magnification:
These may cause either global or local shape-dependent device
variations.

Thermal expansion/contraction changes the

magnification, so T must be controlled to ~0.1oC.
[K. Ausschnitt, et al., 2003 AMM Conf.]

37

Local Lithographic Variations

1. Pattern sensitivity.
Interference effects from neighboring shapes
change the widths.

2. Interference effects from buried features.

(mostly a problem for wiring levels)
3. LER (Line Edge Roughness) [T. Brunner, ICP 2003]

38

Line Edge Roughness

Sources of statistical variation in
chemically amplified resists:
1 Fluctuations in the total dose
due to finite number of quanta
Shot noise
2 Fluctuations in the photon
absorption positions
3 Nanoscale nonuniformities in
the resist composition
4 Statistical variations in the
extent of acid-catalyzed
deprotection
5 Statistical effects in polymer
chain dissolution

2tot = 2dose + 2pos +2chem

[T. Brunner, ICP 2003]

39

Simulated contact hole exposure

Photons
absorbed

Deprotected
polymer

Disolved
polymer

2003, SPIE

Monte Carlo simulation of exposure and

development of a 80 nm contact hole using EUV
[J. Cobb, et al., Proc SPIE]
lithography.
40

Shot noise for different energy quanta

Estimated dose uncertainty for a 50 nm contact hole.
3 dose
variation

Lithography

Energy
Electron-volt

Resist Dose
mJ/cm2

# quanta per
50nm pixel

193nm

6.4

20

500,000

0.4%

EUV 13.5nm

92

3400

5%

X-Ray 1.3nm

920

40

6800

4%

E-beam

50,000

150

470

14%

Ion-beam

100,000

50

78

34%

(3 C/cm 2)
(0.5 C/cm 2)

[T. Brunner, ICP 2003]

41

LER trend

[A. Asenov, et al., IEEE TED, Sept. 2003]

42

Simulation of LER effects in MOSFETs

VDS=
1.0V
VDS=
0.1V

30x50
50x50

(Continuum doping)
Potential distribution in typical 30 x 200 nm MOSFET.

Random instances of line edge roughened FETs are generated by a

Fourier transform technique, and the IV curves are simulated to
evaluate the variations in VT, Ioff, and Ion.
[A. Asenov, et al., IEEE TED, May 2003]
[See also M. Hane, et al., 2003 IEDM Tech Dig., paper 9.5.]

43

Thermal Issues
1. MOSFETs may heat themselves up significantly
during operation.
At higher temperature the drive current is reduced and
the off-current is increased, impacting speed and bias
conditions.
The internal temperature may be history dependent ( ~
10-100 ns).
Especially problematic for SOI because of the high
thermal resistance of the buried oxide layer.

2. Whole circuit blocks may run at high power,

creating hot spots that perturb neighboring circuits.

44

Estimating Hot Spot Temperatures

Calculated temperature rise per KW/cm2 of power density in a hot
spot for various heat sinks and Si thicknesses, as a function of hot
spot size.

Silicon
thickness

[D. Frank, IBM JRD, 2002]

45

Examples of Temperature Variation

within a Processor

Temperature profile of an IBM chip.

from "Temperature-Aware Microarchitecture" talk,

by K. Skandron, et al., U. Va.

46

Wafer-to-wafer variability
3.0

2.5

2.0

1.5

1.0

Normalized metal resistance data over 90

[Chandu Visweswariah]
days
47

Interconnects variability and reliability

F. Twaddle, T. Drysdale

After G. Schnider

Increased resistivity
Electromigration and voids
Variability
[Asen Asenov, Glasgow Univ.]

48

Summary
Parameter variations have always been an issue
for circuit design.
In the past, CMOS technology variations have
mostly been due to imperfect process control.
In present and future devices, however, intrinsic
atomistic variations are becoming very important.
These variations cause uncertainty in IV curves,
in timing, and in power dissipation.

49

Impact of variability on circuits

1. SRAM
Analysis of margin loss
Alternative cell: 8T

2. Logic Circuits
Impact on delay and power
Statistical timing

50

6-T SRAM

6-transistor SRAM cell is widely adopted as industry standard

embedded memory.
2 nFET pass-gates drive cross-coupled inverters.
Separate supply voltages can be used for the cell and for the
wordlines and bitlines.
Bitlines are held high in quiescent state.
51

SRAM Failure Mechanisms

1 Process defect (e.g., shorts or opens)
Systematic failures or random defects
Process needs to be improved
2 Lack of stability margin
Individual cells fail to hold state properly
Individual cells fail to accept a new state properly
No process defect is involved
Cells on the tail of the distribution simply don't work
Lower Vdd decreases the nominal margin
Scaled devices have larger variations, widening the distribution
Increased density leads to more cells in the memory, and more
populated tails

Desireable process improvements narrow the distribution

52

Transistor strengths
Weak

Medium
Strong

Weak

Medium
Strong

Cell is written by T1 or T2 pulling

down T5 or T6.
T1 and T2 are not (supposed to
be) strong enough to pull up T3
or T4.
Cell is read by T1+T3 or T2+T4
pulling down one of the bitlines.

Sense amp sharing

To save space and power, SRAMs often share a sense amp among several
sets of bitlines.
The wordline (WL) activates all of its cells, both those connected to sense
amps and those not connected.
Those not connected to a sense amp are said to be half-selected, and their
bitlines are held to VDD to avoid accidentally changing their states.
53

The 6T Stability Margin

Standby

Noise Margin
approach

WL=0

Vright

No disturb
VDD

BL

BL

Vleft

Read

Vright

WL=V DD

VDD
Vleft

BL=V DD

Access FET
disturbs
0 Node
(Pulled above GND)

BL=V DD

Worst-case stability occurs during a half-select read event

Variability can magnify the disturbance

If the noise margin reaches zero, the cell is unstable.

[Leland Chang]

54

2nd Method to characterize margin

the SRAM N-curve

0.00006

WL=V DD

A
BL=V DD

BL=V DD

VZ0 node current (A)

0.00004

0.00002

0.00000

-0.00002

-0.00004
0.0

0.2

0.4

0.6

0.8

1.0

VZ0 node voltage (V)

Measure current at node A when sweeping voltage from

0 to Vdd, with wordline turned on
[Clement Wann, et al., 2005 VLSI-TSA]
55

the N-Curve
0.03

VZ0 node current (mA)

ICRIT

WL=V DD

A
BL=V DD

BL=V DD

0.02

PCRIT

0.01

1
0.00

VCRIT

-0.01

-0.02

-0.03
0.0

125 C, 0.7V
125 C, 0.7V, 50 mV Vt skew
0.1

0.2

0.3

0.4

0.5

0.6

0.7

VZ0 node voltage (V)

Points 1 and 3 are stable, point 2 is metastable

Point 1 is determined by the cell ratio
Point 2 is considered to be the switching point
For point 3, the other side of the cell needs to be analyzed for
instability.
If ICRIT reaches zero, the cell is unstable.
56

Analysis of Variations in SRAMs

1 Traditional method: Monte Carlo at the circuit level
2 'Analytic' method: most-probable worst case vector
Since parameter variations are
approximately Gaussian and not
bounded, it is not possible to
absolutely guarantee functionality.
Therefore design must be based on
achieving a target yield (e.g., 95%).

Goal of this analysis is to

evaluate the expected yield.

Trial design

Try again

Evaluate expected
yield
Good
enough
?
Yes
Go on vacation

No

57

Monte Carlo Circuit Simulations

Randomly assign characteristics separately for each FET.
Simulate circuit to see if it works.
Under some conditions, a small fraction of such cells fail.
Cell 1
Cell 1
Cell 2
Cell 2
Model 1 Model 2 Model 1
Model 2

SRAMs may have 10M cells.

How can we tell if 1 in 10M

cells is failing?

58

Analytic method: Finding the mostprobable worst case

For any given measure of an SRAM cell's performance, there is some

value at which the cell will fail. (For example, when Icrit=0.)
We need to find the most

likely way of causing that

failure, and determine how
likely it is.
Using that failure probability,
we then determine the
likelihood of the entire
SRAM functioning.

Two variable example:

MPWC
vector
3 2 1

Red curves are hypothetical values of a function M.

Blue curves are lines of constant probability, falling off from
the center.
59

Some definitions
zLet M be a measurement function (such as ICRIT) used to evaluate
the performance or functionality of an SRAM cell.
There may be several such functions to consider.
zThis parameter can be linearized about the nominal design point:

where the xi are the deviations from nominal of the various device
parameters that are important in determining the functionality of the circuit,
such as the VT deviations of the 6 different FETs in an SRAM cell.

zThe standard distribution of the M values is then

where the xi are the standard deviations of the various device parameters
(e.g., the VT's). (This assumes the distributions are reasonably Gaussian.)

60

Most Probable Worst Case

For linear measurement functions M, one can evaluate exactly the most
probable worst case. This direction is given by:

M xi

xi =
xi M
For nonlinear measurement
functions M, one should carry out
numerical evaluations in this worst
case direction.
The function M is evaluated along
this path until the point at which
the cell stops working. The
number of sigmas, M/M, to this
point yields the probability of the
cell failing.
Equivalent paths must also be
considered. e.g., swapping left
and right transistor parameters in
the cell.

Two variable example:

MPWC
vector
3 2 1

Blue curves are lines of constant probability, falling off

from the center.
Red curves are hypothetical values of a function M.
61

Linearity of ICRIT
Reasonably linear to
start with.

"A"

40

Linearity improves
when all devices vary
simultaneously.
ICRIT (uA)

30

20

T6
10
T4

T3

T1

0
0

All varying
together in
worst-case
manner

"B"

100

200

300

400

V T skew (mV)

62

Define ADM
Since ICRIT is quite linear, use the
simplest form, and define:
ADM (Access Disturb Margin) =
where I

CRIT

I CRIT
=
i
i xi

I CRIT

CRIT

63

Margin / size / redundancy requirements

SRAM
Maximum
stability
SRAM size in
margin due to a chip w/ yield
Vt variation
target 90%
3
3.5
4
4.5
5
5.2
5.5
6
6.5

77
437
3.2K
30K
350K
1M
5.3M
102M
2.5B

Redundancy
bits needed
for 1M array
w/ 90% yield
target
~1400
~ 250
38
6
1
0
0
0
0

*90% of the time, 5 or fewer bits are bad

Redundancy
bits needed
for 10M array
w/ 90% yield
target
~ 14000
~ 2400
~ 330
42
5*
2
1
0
0
DJF/BW/CW

ADM determines the stability limited yield of a given

array size and the required redundancy
Quick feedback when exploring the design space

10% improvement in ADM 10X increase in array

size
64

Impact of SRAM variability

1000
1000

Power
Power (W/cm2)
(W/cm2)

100
100

1000

A
Accttiiv
vee PPoowweer
rDDeennssitiyty 100

10
10

10

11

Pa
ss
ive

0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
1E-5
1E-5
0.01
0.01

1
0.1

Po
we
r

0.01

De
ns
ity

0.001
0.0001
1E-5

0.1

11

Number of Bad SRAM Bits per

MPU Chip

Industry Trends

Lpoly (um)
65

Mitigating the problems

SRAM: no more business-as-usual.
Much slower scaling of devices (W & L)
Increase density by shrinking the space between
devices
Keep the voltage high, and use circuit innovations
Need different optimization of the SRAM FETs from
the logic FETs
Or, use eDRAM or other types of memory

66

RWL
WWL

WBL

WBL
Pass-gates for
write only

RBL

Read stack for

read only

Measured Frequency [GHz]

Possible solution: Variation-tolerant 8T cell

32kb Subarray in 65nm
6
5
4
3

~0.7GHz
per 0.1V

2
1
0

0.4 0.6 0.8 1.0 1.2

VDD,Logic = VDD,Array [V]

Cell nodes are not disturbed during read

Stability problems are eliminated

L. Chang et al.,
VLSI05, VLSI07

Read and write mechanisms are decoupled

Writeability problems can be minimized
[Leland Chang]
67

Impact of variability on circuits

1. SRAM
Analysis of margin loss
Alternative cell: 8T

2. Logic Circuits
Impact on delay and power
Statistical timing

68

Impact on yield
Worst-process slow

Worst-process high power

Local variations

Nominal design point must balance yield loss from opposing design
targets (e.g., power and delay). Worst-process points must be chosen
carefully to balance likelihood of global variation reaching this point
against probability of local variations causing design to fail.
69

Increased Static Power

Doping variations, length variations, and noise combine together to
create an approximately Gaussian distribution of equivalent
threshold voltage with sigma, VTeff.
Integrating this Gaussian against the exponential off-current
dependence yields an average shift:
I ave =
=

(VT ) I off (VT )dVT

(V V )2
I exp VT VT
exp T 2 T

0
kT
2 VTeff
2 VTeff

dV T

VTeff

= I 0 exp +
2 ( kT )2

So, the background leakage current increases by the factor

and so does the static power dissipation.
If VTeff exceeds kT, this factor can become quite large.

VTeff

exp +

2 ( kT

)2

70

Delay variability
Analysis of delay variability requires statistical timing
tools
At IBM we use EinsStat

Advantages of EinsStat:

Pessimism reduction
Sensitivity checking
Increased robustness of design
Full-chip coverage
Fully incremental
Yield curve predictions
Performance vs. yield tradeoffs

Identifies critical paths with good process coverage for at-speed

test
Parallelized for fast turnaround
[Chandu Visweswariah]
71

What does EinsStat do?

All timing quantities such as arrival times are propagated as
probability distributions
a

+
+

c
MAX

b
Correlations are important; the covariance matrix for an average chip
is 100M x 100M in size

[Chandu Visweswariah]
72

Pessimism reduction
p2

Exhausting corner
analysis gives us the
worst performance
across these hypercube
corners

3
2
1
p1

Statistical analysis
gives us the worst
performance in
this hypersphere
[Chandu Visweswariah]
73

Impact of variability on optimized performance

Single stage functionality.

P=0.01

Relative Performance

Variation sources:
Signal Coupling noise
Supply noise
Statistical doping variations
LER gate length variations
Consequences modeled:
Increased static power
Critical path delay distribution

1.3
P=1

P=50

1.2
1.1
1
0.9

65nm node, dual

processor core

0.8
0.7
0%

50%

100%

150%

200%

Relative Margin

Increased variability requires:

Higher supply voltages
Less scaled FETs
74

Summary
In the past, CMOS yield loss was often due to processing defects, but
at present and in the future it is dominated by parameter variability.
Parameter variations can be divided into global (chip mean) variations,
local (device-to-device) variations, and across-chip variations.
Global variations and non-thermal across chip variations can probably
be controlled by conventional process control efforts.
Local variations are mostly associated with the discreteness of matter
and energy (atoms and photons).
Discreteness effects tend to get worse with scaling. Extraordinary
efforts may be needed to mitigate this trend.
In SRAM, variability causes margin loss and large numbers of bad
bits.
In Logic, variability causes increased dissipation and timing
uncertainty.

75

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