Institute

School Chitkara School of Engineering & Technology/

Name
Program Name
Course Code
Course Name
Lecture (per week)
Course
Coordinator

School of Electronics and Electrical Engineering

B.E. (ECE)
Microelectronics Circuit Design
4
Course Credits
Mr. Ajaypal Singh Dhillon

Name

1. Scope and Objectives of the Course

Digital and Analog Circuit implementation with CMOS logic.
To understand the Ideal and Non Ideal effects of MOS.
Learning the MOS Fabrication basics.
To understand the concept power dissipation in MOS.

2. Textbooks
TB1: Sung-Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits Analysis
and Design", Tata McGraw Hill, 3rd Edition, 2005.
TB2: Richard C. Jaeger, Travis N. Blalock, "MICROELECTRONIC CIRCUIT DESIGN",
McGraw-Hill, 4th edition, 2011.

3. Reference Books
RB1: Neil H. E. Weste and Kamran Eshraghian ,"Principles of CMOS VLSI design ",
Pearson, 3rd edition, 2005.
RB2: Jacob Millman, Arvin Grabel, " MICROELECTRONICS", Tata McGraw-Hill, 2nd
edition, 1987.

3.Other readings and relevant websites

S.
No.

Link of Journals, Magazines, websites and Research Papers

http://www.mosis.com/vendors/view/on-semiconductor
1

http://www.vlsi.wpi.edu/cds/index.htm
2
3
.

http://www.staticfreesoft.com/index.html

4
.

http://cmosedu.com/cmos1/electric/electric.htm

4. Course Plan
Lect.
No.
(1 Hr)
1-3

5-6
7-8

Topics
UNIT 1:MOS Theory
Introduction, MOS Structure (nMOS-pMOS),
Working of MOS Transistor (nMOS-pMOS),
Different types of representation for nMOS
and pMOS.
Channel Development: Accumulation region,
Depletion region, Inversion region: weak
inversion, Moderate inversion, strong
inversion.
Current Voltage characteristics, Ideal drain
current equation development.
Difference between Enhancement and
Depletion MOSFET. MOS Transistor as Switch,
MOS capacitor characteristics, MOS device
capacitances.

Text
Book

Section No.,
Page No.

TB1

sec 1.1
sec 1.4
sec 1.5
sec 3.3
-100)
sec 3.2

TB1

TB1
TB2
RB1
TB1

(pp.1-5)
(pp.18-20)
(pp.21-23)
(pp.90
(pp.87 -90)

sec 3.4 (pp.100105)

sec 4.2.8 (pp.158159)
sec 1.1 - 1.3 (pp.48)
sec 3.6 (pp. 129134)

UNIT-2: Circuit Designing and Simulation

9
10-11

CMOS Logic inverter: Representation, CMOS TB1

working
DC-characteristics, Logic gates designing TB1
with CMOS Logic
RB1

sec 5.4 (pp.197199)

sec 5.4 (pp.199203)
sec 1.4 (pp8-14)

ST 1
12
13
14-15
16

17
18-19
20-21

Pseudo-nMOS.

TB1

sec 7.4 (pp.300302)

Pass transistor logic
TB1
sec 7.5 (pp. 314316)
Transmission gate logic. Multiplexer TB1
sec 7.5(pp.307,
designing
312-313)
RB1
sec 1.4.6(pp.14-17)
D-flip-flop, SR flip-flop designing, Latch
TB1
sec 8.4 (pp.336design with T-gate.
338)
sec 8.5 (pp. 343349)
UNIT3: MOS Non Ideal Effects and Power Estimation
Channel Length Modulation, Velocity
TB1
sec 3.4(pp.107saturation
TB2
109)
sec 2.3.3 (pp49)
Body effect, Sub threshold conduction, TB2
sec 4.2.9 (pp.159Junction leakage, Tunneling.
160)
Dynamic and Static power estimation
TB2
sec 6.10 (pp.333RB1
336)
sec 4.7 (pp.144147)

22

Rise time and fall time estimation.

23-24
25-26
27
28
29-31

32-33
34-36

TB1

ST2
UNIT4: Layout designing
Layout design rules (Lambda and Micron TB1
rules).
nMos Fabrication and mask generation, TB1
pMOS fabrication and mask generation
RB1
CMOS twin tub technology
RB1
Latchup-effect in CMOS
RB1

sec 6.2 (pp. 220222)

sec 2.4 (pp.66)
sec 2.5 (pp. 67-72)
sec 2.2 (pp.53-56)
sec.3.2 (pp70-91)
sec 3.2 (pp.86-88)
sec 2.6 (pp.58-59)

UNIT5: Analog Integrated Circuit Design Techniques

Small signal model for the MOS Transistor.
TB2
sec 4.6(pp.167Voltage Follower, Common source, Common
168)
drain and Common Gate Amplifiers design
sec 10.9.4 (pp.561)
sec 14.1.3 (pp.860)
sec 14.1.4 (pp.861)
Basics of Differential Amplifier design and
TB2
sec 15.1 .1analysis. Basics of Operational Amplifier
2(PP.969)
designing
Introduction to Current mirror circuit design,
TB2
sec 16.2.1Mirror Ratio, Analog Multiplier.
2(pp.1049-1051)
sec 16.10(pp.1110)

5. Evaluation Scheme:
Component 1
Component 2

Two Subjective /Online Test based on MCQs

End Term Examination
Total

40%
60%
100

Details of Component-1: There will be two sessional tests (STs) for all the theory
papers as per below stated guidelines:
(i) 1st sessional test will be from 0- 30% syllabus of the subject
(ii) 2nd sessional test will be from 31-60% syllabus of the subject.
(iii) The average of both the tests will be taken for finalizing the internal of the
subject.
(iv) Sessional Tests are compulsory.
Details of Component-2: The End Term Examination will be held at the end of
semester. As per academic guidelines minimum 75% attendance is required to
become eligible for appearing in the end term examination. The syllabus for end
term will be
i.

40% contents will be from ST-1 and ST-2

ii.

60% contents will be from 61-100% syllabus.

This Document is approved by:

Designation
Course

Name
Mr. Rajvir Singh

Coordinator
H.O.D
Dean

Ms. Pooja Arora

Mr. Rajesh Hooda

(Academics)
Date

Signature