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Logic Design

10CS33
Assignment Questions
Unit -1
Digital Principles, Digital Logic

1. Explain Duality Theorem?


2. Differentiate between Positive Logic and Negative Logic
3. Using Karnaugh Map,simplify the following boolean expression and give the
implementation of the same using
i)NAND gates only(SOP)
ii) NOR gates only (POS )
a. F(w,x,y,z)=m(0,1,2,4,5,12,14)+dc(8,10)
4. Simplify the following logic equation using Karnaugh map and give the implementation of
the simplified expression
a. f(w,x,y,z)= m(7)+d(10,11,12,13,14,15)
5. What are Universal gates? Implement the following function using Universal gates only
6. Find the prime implicants for the boolean expression using Quine Mc-Clusky method
f(w,x,y,z)= m(1,3,6,7,8,9,10,12,13,14)
7. Give the simplified logic equation using Quine-Mcclusky method for the following
Boolean function
a. f(a,b,c,d)= m(0,1,2, 3,10,11,12,13,14,15)
8. What is the purpose of using an Expander with an AND-OR-INVERT gate? Write a logic
circuit of an expandable AND-OR-INVERT gate
9. Simplify the following logic expression using Karnaugh Map and also by Quine-Mcclusky
method
i. f(a,b,c,d)= m(1,2,8,9,10,12,13,14)
10. Explain different models for writing Verilog modules.Give an example for each.

Unit-2
Combinational Logic Circuits
1. Write a note on Nibble Multiplexers
2. Implement 32:1 multiplexer using 16:1
3. Realize 1:32 Demultiplexer using 1:16 Demultiplexer
4. Write a note on Decoder
5. Write a note on Full Adder
6. Implement BCD to seven segment decoder using PLA
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Logic Design

10CS33

7. Write a note on Priority Encoder


8. Design Decimal to BCD Encoder and Decimal to Octal Encoder.

Unit- 3
Data-Processing Circuits
1. Differentiate between PROM,PAL,PLA
2. Implement the following Boolean functions using PLA
F1(A,B,C)=m(0,1,3,5)
F2(A,B,C)=m(1,3,4,7)
3. Write the verilog code for 4:1 multiplexer and 1:4 demultiplexer using conditional assign
and case statements.
4. Write the characteristic of an ideal clock.
5. Explain Monostable Multivibrator

Unit -4
Clocks, Flip-Flops
1. What is a Flip Flop? Discuss the working principle of SR FlipFlop with its truth table. Also
highlight the role of SR Flip flop in switch debouncer circuit
2. With neat schematic diagram of master slave JK-FF,discuss its operation Mention the
advantages of JK-FF over master-slave SR flip-flop.
3. Explain different types of Flip-flops with truth table
4. What is Race around condition in Flip-Flop.. How can it be eliminated.
5. Conversion of SR flipflop to D flipflop
6. Conversion of D flip flop to JK flipflop
7. Find out characteristic equations of S-R FF and J-K FF.

Unit-5
Registers
1. With a neat circuit diagram, explain the working of a Serial in Serial out shift registers.
2. Write a note on applications of Shift registers.
3. Design a 3 bit PISO(DFlip flop)
4. Design two 4 bit serial adder.
5. Design a 4 bit Johnson counter with sate table
Dept. of CSE, SJBIT

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Logic Design

10CS33

Unit-6
Counters
1. Design a cyclic mod 6 synchronous binary counter using JK Flip-flop. Give the state
diagram, transition table and excitation table .
2. With a block diagram describe a 3-bit Johnson twisted ring counter. Draw the sequence
diagram and indicate the valid and invalid states.
3. Differentiate between ripple and synchronous counter.
4.

Design a synchronous mod 6 up counter using JKflip flop.

5.

Explain Digital clock with block Diagram.

Unit-7
Design of Synchronous and Asynchronous Sequential Circuits
1. Distinguish between Moore and Mealy model with necessary block diagrams
2. Explain Moore model with state synthesis table and also obtain the ciruit diagram for
moore model
3. Design mealy type sequence detector to detect a serial input sequence of 101.
4. Draw state diagram of a sequence detector circuit that detects 1101 from i/p data stream
using both mealy and moore models.(1st bit=1,2nd bit=1,3rd bit=0,4th bit=1)
5. Write short notes on Algorithmic state machine.
6. Design a parity generator using asynchronous sequential logic that gives output=1,when it
receives odd number of pulses and output=0 if the number of pulses received is even.
7. What are the problems with asynchronous sequential circuits.
8. Construct moore and mealy state diagram that will detect input sequence 10110,when input
pattern is detected,z is asserted high. Give state diagrams for each state.

Dept. of CSE, SJBIT

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Logic Design

10CS33
Unit -8
D/A Conversion and A/D Conversion

1. What is accuracy and resolution of the D/A converter? What is the resolution of a 12-bit
D/A converter which uses a binary ladder? If the full scale o/p is +10Volts what is the
resolution in volts.
2. What is Binary ladder. Explain binary ladder with digital input of 1000.
3. Explain 2-bit simultaneous A/D converter.Draw the block diagram of a 2-bit A/D
converter.
4. Draw a 4 bit D/A converter using R-2R resistors and explain its working.
5. Find the following for a 12-bit counter type A/D converter using a 1-MHz clock
Maximum conversion time
Average Conversion Time
Maximum Conversion rate
6. Write the circuit diagram, explain the operation of the CMOS NAND gate.
7. Design a CMOS inverter with relevant circuit diagram.
8. With the aid of a circuit diagram, explain the operation of 2-input TTL NAND gate with
Totem-pole output.
9. Explain the operation of 2-input CMOS NOR gate with the help of a circuit diagram
10. Write a note on CMOS characteristics
11. Give six comparisons of CMOS and TTL families.
12. Discuss the features of high speed TTL , Low power and Schottky TTL families.
13. Explain methods for interfacing CMOS devices to TTL devices.

Dept. of CSE, SJBIT

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