DIEES
Universit di Catania, Facolt di Ingegneria
Viale A. Doria 6, 95125 Catania, Italy
Email: eragone@diees.unict.it, gpalmisano@diees.unict.it
I.
INTRODUCTION
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CIRCUIT DESIGN
Low-Noise Amplifier
The simplified schematic of the LNA is shown in Fig. 1.
B. 24-GHz Synthesizer
The design of a frequency synthesizer working at
operating frequency higher than 5 GHz is an issue of great
concern. The design of both low-noise oscillator and
high-frequency prescaler represents the bottleneck to
demonstrate the feasibility of Si-based chips for
high-frequency applications. This work uses a 24-GHz PLL,
adopting a well-established architecture composed of
phase/frequency detector (PFD), charge pump, external loop
filter, voltage-controlled oscillator (VCO), and N-integer
divider. Using a division ratio N of 2048 a 24.125-GHz carrier
is achieved with a PLL reference frequency fREF of
11.78 MHz. A second order loop filter is used to set PLL
bandwidth at 200 kHz.
The VCO, whose simplified schematic is depicted Fig. 2,
uses a bipolar core with high-Q LC resonator. An issue of
great concern is the design of both capacitors and inductor in
the LC tank. This resonator exploits accumulation MOS
(A-MOS) variable capacitors and a single-turn inductor whose
value at 24 GHz is as low as 230 pH. As reported in [4], both
measurements and modeling of such sub-nH spirals are quite
critical. To overcome these problems and take into account all
connection paths, EM simulators are extensively adopted
during the resonator design.
Finally, the N-integer divider is designed using a chain of
11 divider-by-two stages. Each stage uses flip-flop in
closed-loop master-slave configuration. High-speed flip-flops
are designed using current-mode-logic D-latches. Each divider
drives the subsequent one using an emitter follower stage. The
design of high-speed D-latches requires accurate RLC
extraction and evaluation of connection paths during layout
drawing. To this aim, in addition to conventional post layout
flows, commercial EM simulator was largely exploited to
guarantee working capabilities beyond 30 GHz.
C. UWB Transmitter
The modulated pulses are generated by using a sub-ns
switch, whose simplified schematic is shown in Fig. 3. A
current steering approach is adopted. The 24-GHz signal
drives the RF port, while the pulse signal coming from the
pulse generator (PG) steers the RF signal into the output port
to generate the 24-GHz modulated pulse. The switch is
properly designed to deliver a 0-dBm output power complying
with 1-ns pulse transmission requirements, thus avoiding the
need of an additional amplifier. A resonant load composed of
MIM capacitor, CL, and stacked transformer, TLOAD, is
adopted. The design of the output transformer TLOAD is an
issue of great concern. First a simplified lumped model [5]
was exploited to define the transformer geometrical
parameters and then a commercial 3D EM simulator, Ansoft
HFSS, was used to simulate the layout structure, taking into
account all the connection paths. The monolithic transformer
provides both differential-to-single-ended conversion of the
output signal and ESD protection, as well. Thanks to the
secondary inductor of TLOAD, the current generated by
electrostatic discharge is shorted to the ground without any
ESD protection diode loading the RF stage.
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III.
EXPERIMENTAL RESULTS
496
ACKNOWLEDGMENT
[2]
[3]
[4]
[5]
[6]
Figure 8. Frequency synthesizer output spectrum.
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