Writing Testbenches:

Functional Verification of HDL Models

Second Edition

Janick Bergeron
Synopsys, Inc.

Kluwer Academic Publishers

Boston/DordrechtA.ondon

TABLE OF CONTENTS

About the Cover

XV

Foreword

xvii

Preface

^^

Why This Book Is Important

What This Book Is About
What Prior Knowledge You Should Have
Reading Paths
Choosing a Language
VHDL vs. Verilog

_^

j^^

Hardware Verification Languages

xxiv

And the Winner Is

xxv

For More Information

Acknowledgements

CHAPTER 1

^ix
' ^x
xxi
,^^11
xxiii

What is Verification?
What is a Testbench?
The Importance of Verification
Reconvergence Model

Writing Testbenches: Functional Verification of HDL Models

xxvi
xxvi

1
1
2
5

Table of Contents
The Human Factor

Automation
Poka-Yoke
Redundancy

7
7
7

What Is Being Verified?

Formal Verification
Equivalence Checking
Model Checking
Functional Verification

Functional Verification Approaches

Black-Box Verification
White-Box Verification
Grey-Box Verification

Testing Versus Verification

Scan-Based Testing
Design for Verification

Design and Verification Reuse

CHAPTER 2

8
8
9
10
II

12
12
13
15

16
17
18

19

Reuse Is About Trust

Verification fi}r Reuse
Verification Reuse

19
20
20

The Cost of Verification

Summary

21
23

Verification Tools
Linting Tools
The Limitations of Linting Tools
Linting Verilog Source Code
Linting VHDL Source Code
Linting OpenVera and e Source Code
Code Reviews

Simulators
Stimulus and Response
Event-Driven Simulation
Cycle-Based Simulation
Co-Simulators

Verification Intellectual Property

Hardware Modelers

Waveform Viewers

25
26
27
29
30
32
32

33
34
34
37
39

42
43

. 44

Writing Testbenches: Functional Verification of HDL Models

Code Coverage
Statement Coverage
Path Coverage
Expression Coverage
FSM Coverage
What Does 100% Code Coverage Mean? .[,,""'.'''.
Functional Coverage
Item Coverage
Cross Coverage
Transition Coverage
What Does 100% Functional Coverage Mean?
Verification Languages
Assertions
Simulation Assertions
Formal Assertion Proving
Revision Control
The Software Engineering Experience
Configuration Management
Working with Releases

53

^Q
^
61
^2
^
^5
57
68
69
71
72

Issue Tracking
What Is an Issue?
The Grapevine System
The Post-It System
The Procedural System
Computerized System

74
74
75
76
76
77

Metrics
Code-Related Metrics
Quality-Related Metrics
Interpreting Metrics

'^
79
*^
^^
83

Sununary

CHAPTER 3

"^^

The Verification Plan

^^

The Role of the Verification Plan

Specifying the Verification
Defining First-Time Success

Levels of Verification
Unit-Level Verification
Reusable Components Verification
ASIC and FPGA Verification

^^
^^
^^

vii

Writing Testbenches: Functional Verification of HDL Models

Table of Contents
System-Level Verification
Board-Level Verification

92
93

Verification Strategies
Verifying the Response
From Specification to Features
Component-Level Features
System-Level Features
Error Types to Look For
Prioritize
Design for Verification

94
95
96
99
99
100
101
702

Directed Testbenches Approach

104

Group into Testcases

From Testcases to Testbenches
Verifying Testbenches
Measuring Progress

105
106
107
108

Coverage-Driven Random-Based Approach

109

Measuring Progress
From Features to Functional Coverage
From Features to Testbench
From Features to Generators
Directed Testcases

109
7//
775
775
778

Sununary

CHAPTER 4

High-Level Modeling
Behavioral versus RTL Thinking
Contrasting the Approaches
You Gotta Have Style!
A Question of Discipline
Optimize the Right Thing
Good Comments Improve Maintainability
Structure of Behavioral Code
Encapsulation Hides Implementation Details
Encapsulating Useful Subprograms
Encapsulating Bus-Functional Models
Data Abstraction
Records
Variant Records
Arrays
Usts

vin

120

121
121
i^3
125
125
126
129
l-'O
131
1^^
1^^
145
7^<J
1^1
755
. . . . 757

Writing Testbenches: Functional Verification of HDL Models

Files
163
Mapping High-Level Data Types to Physical Interfaces 165
Object-Oriented Programming
166
Classes
766
Inheritance
773
Polymorphism
777
Limitations of OpenVera andes OOP Implementation . 780

Aspect-Oriented Programming
The Problem with Object-Oriented Programming
Variant Data with Variant Code
Limitations ofe's AOP Implementation

181
.,,181
783
786

The Parallel Simulation Engine

189

Connectivity. Time and Concurrency

Connectivity, Time and Concurrency in HDLs and
HVLs
The Problems with Concurrency
Emulating Parallelism on a Sequential Processor
The Simulation C\cle
The Co-Simulation Cxcle
Parallel vs. Sequeniial
Fork/Join Statement
The Difference Between Driving and Assigning
Race Conditions
Read/Write Race Conditions
Write/\^rite Race Conditions
Initialization Races
Guidelines for Avoiding Race Conditions

1S9
^^
1^1
,.,192
196
797
-C^
208
^^
^^^
'^^
^
- - ^^^

Seme^^res
Verilos Portabilitv Issues

Events from 0^er.rien Scheduled Values

Disabled Scheduled Values
Output Arguments on Disabled Tasks --
Non-Re-Entrant Tasks

^jg
-^^
^
.^l
^

Summary

CHAPTER S

Stimulus a,ui Response

Reference Signals
TmeftesoUaion Issues
.Migning Signals in Delta-Tone

229
^
231
...233

Table of Contents
Clock Multipliers
Asynchronous Reference Signals
Random Generation of Reference Signal Parameters
Applying Reset

Simple Stimulus
Applying Synchronous Data Values
Encapsulating Waveform Generation
Abstracting Waveform Generation

Simple Output
Visual Inspection of Response
Producing Simulation Results
Minimizing Sampling
X^sual Inspection of Waveforms
Self-Checking Testbenches
Input and Output Vectors
Golden Vectors
Self-Checking Operations

Complex Stimulus
Feedback Between Stimulus and Design
Recovering from Deadlocks
Asynchronous Interfaces

Bus-Functional Models
CPU Transactions
From Bus-Functional Procedures to Bus-Functional
Model
OpenVera's Interface Model
Bus-Functional Models in OpenVera
Asynchronous Signals in OpenVera
Synchronous Bus-Functional Models ine
Asynchronous Bus-Functional Models ine
Configurable Bus-Functional Models

Response Monitors
Autonomous Monitors
Slave Generators
Multiple Possible Transactions
Transaction-Level Interface
Variable-Length Transactions
Split Transactions
Retries and Completion Status
Symbol-Level Control
Summary

235
23A
239
24/

246
246
247
248

252
252
252
254
255
256
257
258
260

262
263
264
267

269
269
272
274
276
287
282
287
289

290
295
299
^^
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317

Writing Testbenches: Functional Verification of HDL Models

CHAPTER 6

Architecting Testbenches

sjg

Test Harness

^2^

VHDL Test Harness

Bus-Functional Entity
Abstracting the Client/Server Protocol
Test Harness
Multiple Server instances

325
^27
J29
jj2
334

Design Configuration

335

Abstracting Design Configuration

Configuring the Design
Random Design Configuration

336
338
340

Self-Checking Testbenches

341

Hard Coded Response

Data Tagging
Reference Models
Transfer Function
Scoreboarding
Integration with the Transaction Layer

342
343
345
347
348
350

Directed Stimulus
Random Stimulus

352
354

Atomic Generation
Adding Constramts me
Adding Constraints in OpenVera
Constraining Sequences
Defining' Scenarios in OpenVera
^
Defining Scenarios me

"'^
-'^^
^^^
364

377
374

Summary

375
CHAPTER 7

Simulation Management

Behavioral Models

^7^

Behavioral versus Synthesizable Models

^^^
Example of Behavioral Modeling
^^^
Characteristics of a Behavioral Model ; ^ ^^^
Modeling Reset

...390
Writing Good Behavioral Models
^^^
Behavioral Models Are Faster
395
The Cost of Behavioral Models
. . . . 595
The Benefits of Behavioral Models

xi

^^;;;r:^^^::^:::^,^^^

Table of Contents
Demonstrating Equivalence

Pass or Fail?
Managing Simulations
Configuration Management
Verilog Configuration Management
VHDL Configuration Management
OpenVera Configuration Management
e Configuration Management
SDF Sack-Annotation
Output File Management
Seed Management
Regression
Running Regressions
Regression Management
Summary

APPENDIX A Coding Guidelines

^^9

Directory Structure
VHDL Specific ....[[ [ .'.*.'.
Verilof- Spec,fie
"'

^^

^^^
^^2

General CVxJmg Guidelines

Comments
iMyout
Syntax . . . . . . . . . . \ . \ '
Debugging

Naming Guidelines
Capitali7xition

.^
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"^^^
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.....^^

^^

Identifiers

"^^

^,

AAA

Constants
,,.
"l''<^HVLSperifir"\\
f'tlenamex

'"^'^ Coding Guidelines

Structure
tjiytiut

Z
^^^

^m^LSperifir
^^'-'log Specific

^^^

^"
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455

xij

Writing Tcufbcnchc*: F
unctional Vcrifitation of HDl. Modcli

APPENDIX B Glossary

461

Afterwords

465

Index

467

^^-^r;;;;;^^

verification of HDU ModCs

xiu