Power Aware Characterization of

Input Vectors Sequence for Std.

Cell Based Circuits
Pramod K. Jain

D. Boolchandani

V. Sahula

Department of ECE

Malaviya National Institute of Technology, Jaipur

(Deemed university)

param_jain@rediffmail.com, sahula@recjai.ac.in, dbool@rediffmail.com

VDAT 2002

Power aware Charaterization of IPPS

Index
Motivation
Sources

of power dissipation

Power

estimation from layout (full adder)

Power

minimization technique

Characterizing

the IPPs sequence

Integer linear programming

Greedy heuristic
Results

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Power aware Charaterization of IPPS

Motivation
Cell selection for low power
technology mapping
Low power sequence for stored
data application
Data processing is independent
of sequence of input data

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Power aware Charaterization of IPPS

Low Power VLSI Design

Analysis
accurate estimation

Optimization
process of generating the best design

Estimation techniques forms foundation for

design optimization

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Power aware Charaterization of IPPS

Power Estimation Techniques

Accuracy vs Computing resources (Time and memory)

Abstraction level
computing resources
Algorithms
least
Software and system
Hardware behavior
Resistor transfer
Logic (gate) level
Circuit (transistor) level
Device level
Worst
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Power aware Charaterization of IPPS

Analysis accuracy
Worst

Best
5

Power Measurement
Simulation based approach
Higher accuracy
Not feasible for large circuits
Large memory and
Large simulation time

Probabilistic approach
Power dissipation due to transitions only
Sacrifice accuracy
Complexity
switching activity estimation
Not suitable for small circuits
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Power aware Charaterization of IPPS

Probabilistic Technique
Switching power estimation of full adder
n

1
2
Pav = Vdd CiD(y i )
2
i=1
Where
D(yi): # of the transitions per time interval
Ci : capacitance at node i

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Power aware Charaterization of IPPS

1-Bit Full Adder Example

y3
a0
b0

y9

y1

n18

y8

y2

s0
y10

y7

n16

y6

cy

y4
n19
c0

y5

Layout in 1.5m, Tanner

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Power aware Charaterization of IPPS

Power Components in FA
Switching Power ?
Short ckt. Power
lower for smaller FT, RT

Leakage power
Constt. (Small)

Ckt

Total power
(W)

Dynamic power
(W)

Dynamic vs
Total

1204

1197

99.4%

NAND2

37

35

94.6%

2_1 MUX

211

202

95.7%

XOR

328

325

99.0%

Adder

Tool used for Switching power estimation

Tanner SPICE
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Power aware Charaterization of IPPS

Power Minimization
Technique
Switching power is major contributor
More than 80% of total power (small
circuits)
Minimize the internal switching activity
by selecting appropriate sequence of the
input data
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Agenda
Objective: Find sequence of input-vectors with
minimum power dissipation
Procedure:
Enumerate pair of O/P transitions
Enumerate corresponding 2 I/P vectors

Enumerate sequence of O/P transitions

Enumerate sequence of I/P vectors

Estimate power in switching between 2 I/P

vectors
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Output and Input Transitions

a, b, f {0,1}

fn
0
0
1
1
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fn+1
0
1
0
1

an bn
0 0
0 1
1 0
1 1
fn
0
anbn
00
00
11
11

Power aware Charaterization of IPPS

fn
0
1
1
0

fn+1
0
an+1bn+1
00
11
00
11
12

Problem Definition
k Number of I/Ps
=2k Number of I/P

P2

( 1)!

vectors
Number of pairs of
I/P vectors
Possible number of
sequences of I/P
vectors

00

01

10

11

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3
k 2
8
=2k 4

P2 12 56
( 1)! 6 5040

Problem: Which is minimum power

sequence of I/P vectors out of (2k-1)!
sequences?
Model: Directed graph G of 2k nodes & lP2
edges
Solution: Find minimum weight
Hamiltonian cycle in G. Know the
edge weights (Power in I/P pair).

Power aware Charaterization of IPPS

13

Tracing of Hamiltonian CycleTime complexity

ILP Based Exact algorithm
Sub tours elimination constraints
l 2

k =2

Ck

Edge cover heuristic

Sorting edges in ascending order of weight
Selection of edges till completion of the HC
O(E)

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Char. of IPPs for Low Power

Input Pattern Pair (IPP)
A pair of consecutive input vectors called IPP
Select the suitable sequence of IPPs
minimize the power dissipation

Hamiltonian cycle
closed path in a digraph, which starts and ends on
the same node, passing through all the nodes only
once
Problem Def: Finding a minimum weight Hamiltonian cycle
(HC) in a complete digraph
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IPPs for 3-bit Input Circuit

a0

cy

b0

Full
Adder

c0

Input vectors are l=2n e.g. (000,

001, 010, etc)

7 IPPs corresponding to each

Sum input vector.

Total number of IPPs would be lp2

n=3
=8

P2 = 56

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Power component in full adder

Total Power
using
simulation
Dy. Power
using prob.
Method

Ex. parasitic

In. parasitic

% Difference

587.7w

1197.2 w

42.5% contr.
by parasitic

956.3 w

79.8% to the
total power

r t=rise time=.01ns, f t= fall time=.01ns, p w=pulse width=10ns, Adder delay =3.63ns

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Digraph Representation of All

Possible IPPs
001

A node in a digraph
corresponds to an input
vector

010

000

An edge of the digraph

corresponds to input
vector transition

011

111

The edge weight C ij

the power consumed in
transition.

100

110
101

Possible transitions of input vectors for a 3-input circuit

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Time complexity
ILP
Sub tours elimination constraints
l 2

k =2

Ck

Heuristic
Sorting in ascending order
Selection of edges till completion of the HC
O(E)
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0-1 ILP Based Solution

Find minimum weight Hamiltonian cycle
(HC) in a complete digraph
ILP provides the exact solution
Formulation
Objective function
Constraints equations

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0-1 ILP Based Solution (Contd.)

Introducing a decision variable 0-1 variable Xij such that

1
X ij =
0

if

the edge i to

j is in Hamiltonian cycle

otherwise

The constraint equations to satisfy two conditions

every node must have exactly one in-degree and one
out-degree
sub cycles which are the disjoint loops in the diagraph
must be eliminated.
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ILP Formulation
Objective

function :

n n
min C ij X ij ,
j =1 i =1

for i j

# of equations required
very large O(2l)
146 even for 3-input circuit

Such that
n
X ij = 1 for i = 1,2......., n and j i
j =1

Represents In degree 1.

n
X ij = 1 for j = 1,2......., n and j i
i =1

Represents Out degree 1.

X ij 2 for k {1,2......., n}
ik jk

Sub cycles elimination

constraints

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Proposed Heuristic: Minimum

Power Edge Cover (MPEC)
Minimum-Power Edge-Cover G (V, E)
1. R=E; // R is remaining edge
2. C=; // C is cycle edge
3. While R is not empty
3.1
Remove the shortest edge (v, w) from R
3.2
Check for cycle and in/out degree of a node
3.3
If [(v,w) does not make a cycle with edges in C]
AND [(v,w) would not be second out going or
second incoming edge in C incident on v or w]
3.3.1
Add (v, w) to C
3.4
Continue loop
4. Add the edge connecting the end points of the path in C
5. Return C;

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Power in HCs: XOR Gate

Example
Sequence

Power

Sequence

Power

0, 1, 2, 3
0, 1, 3, 2
0, 2, 1, 3
0, 2, 3, 1
0, 3, 1, 2
0, 3, 2, 1
1, 0, 2, 3
1, 0, 3, 2
1, 2, 0, 3
1, 2, 3, 0
1, 3, 0, 2
1, 3, 2, 0

258 w
286 w
253 w
283 w
321 w
329 w
285 w
328 w
324 w
256 w
255 w
287 w

2, 0, 1, 3
2, 0, 3, 1
2, 1, 3, 0
2, 1, 0, 3
2, 3, 0, 1
2, 3, 1, 0
3, 0, 1, 2
3, 0, 2, 1
3, 1, 0, 2
3, 1, 2, 0
3, 2, 0, 1
3, 2, 1, 0

290 w
326 w
256 w
329 w
257 w
285 w
258 w
257 w
285 w
324 w
288 w
329 w

Average Sequence Power = 289.54

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VDAT 2002
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Hamiltonian cycle

25

3210

3201

3120

3102

3021

3012

2310

2301

2103

2130

2031

2013

1320

1302

1230

1203

1032

1023

0321

0312

0231

0213

0132

0123

Power dissipation (mw)

Power in HCs: XOR Example

3.4

3.3

3.2

3.1

2.9

2.8

2.7

2.6

2.5

Comparing Two Techniques: Low

Power IPPs Sequence
Minimum power HC comparisons using ILP versus Heuristic

Cell

HC/ [Power] using

ILP

HC/ [Power] using

Heuristic

% Difference

XOR

0, 2, 1, 3

[253 w]

3, 0, 2, 1

[257w]

NAND

2, 0, 1, 3

[28 w]

0, 1, 2, 3

[33w]

15.2%

S-R FF

2, 1, 3

2, 1, 3

[161 w]

0%

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[161 w]

Power aware Charaterization of IPPS

1.32%

26

MPEC Heuristic Results: Min. Power

Bound
Cell

Min. Power HC

Avg. Min. Power

3-input NAND

1, 4, 2, 0, 3, 5, 6, 7

52 w

3-input OR

0, 1, 2, 4, 6, 5, 3, 7

78w

3-input NOR

0, 2, 3, 4, 6, 7, 5, 1

70w

2_1 MUX

2, 6, 0, 4, 1, 3, 7, 5

87 w

ADDER

6, 7, 0, 1, 4, 2, 3, 5

2160 w

AND-2 NOR-2

2, 4, 0, 3, 5, 1, 6, 7

337w

OR-2 AND-2

1, 0, 2, 4, 6, 3, 5, 7

94w

AOI

15, 13, 6, 3, 2, 7, 11, 9, 12, 0, 10, 8,

1, 4, 5, 14

85 w

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MPEC Heuristic Results: Max. Power

Bound
Cell

Max. Power Hamiltonian cycle

Avg. Max.
Power

2-input NAND

3, 1, 0, 2

37w

2-input XOR

1, 0, 3, 2

328w

3-input NAND

7, 3, 0, 6, 1, 2, 5, 4

69 w

3-input OR

5, 4, 0, 6, 1, 3, 7, 2

126w

3-input NOR

4, 0, 3, 6, 1, 2, 5, 7

99w

2_1 MUX

1, 6, 3, 4, 7, 2, 7, 5

211 w

continued
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MPEC Heuristic Results: Max. Power

Bound (Contd.)
Cell

Max. Power Hamiltonian cycle

Avg. Max. Power

ADDER

0, 3, 6, 5, 2, 7, 4, 1

2460 w

S_R FF

3, 1, 2

305 w

AND-2 NOR-2

1, 7, 0, 5, 4, 3, 6, 2

2626w

OR-2 AND-2

4, 1, 5, 0, 3, 6, 7, 2

248w

AOI

5, 12, 4, 8, 3, 11, 2, 10, 9, 1, 7, 6, 13,

14, 15, 0

106 w

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Conclusions
Dynamic power
major contributor

Efficient method for power characterization using

IPPs
advantageous in technology mapping for low power

Results using proposed heuristic

optimal or nearly optimal sequence

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30