*Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Malaysia
** Electrical Engineering Department, California Polytechnic State University, San Luis Obispo, CA 93407, USA
C2
I.
C1
L1
Do1
Rload
S1
Co2
Ds1
L3
VAC
Co1
L2
Ds2
S2
INTRODUCTION
Do2
(a)
L1
Cb1
Do1
Do2
L2
Ds1
Co
S1
Vg
L3
Ds2
S2
Cb2
(b)
L1
Cb1
Do1
L2
Vg
R
Co
S1
Ds2
(c)
L1
Do2
R
Vg
Ds1
Co
L3
S2
Cb2
(d)
Fig. 1. Circuit topology for (a) bridgeless SEPIC PFC in [8], and (b) the
proposed bridgeless SEPIC operated during (c) positive and (d) negative
half line cycle
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S1,S2
CIRCUIT OPERATION
ON
OFF
0A
iL1(t)
t
0A
iCb1(t)
0A
(a)
iL2(t)
t
0A
vL1 (t)
t
(b)
iCo(t)
t
0A
vL2 (t)
t
(c)
Fig. 2. Equivalent circuit during (a) MODE 1(d1TS), (b) MODE 2(d2TS) and
(c) MODE 3(d3TS).
d1TS
d2TS
d3TS
Fig. 3. Waveforms within each switching period for several components.
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value,
0.35
L1
(1)
(d1TS )
v
v
iDo1 pk =
i L1 pk +
i L 2 pk =
d1TS g +
Cb1
L1 L2
Since
(3)
d2 =
vg
(vCb1 + vO v g )
d1
(4)
M =
vO
RTS
= d1
vg
2La
CCM/DCM
Boundary
0.25
0.2
0.15
CCM
DCM
0.1
0.05
Pout=50W
Pout=20W
Pout=100W
0
100
150
200
Pout=200W
250
300
350
Input Voltage, Vm
(2)
iDo1 pk =
d1TS g
L
a
0.3
Duty Cycle, D1
iL1 peak =
vg
1
d1 >
2La .
RTS
(6)
(5)
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115-230Vrms at 50Hz
150uH
70uH
1uF
50V DC
50kHz
100W
1410uF
its values are similar to the designed ones. Figure 6 shows the
experimental results for the proposed circuit.
From Figure 6(a), the input current follows the voltage
waveform and is in phase with the 115 Vrms input voltage
with power factor for this condition recorded at 0.98. The
same results can be observed for 230 Vrms input voltage in
Figure 6(b) with 0.97 power factor. It is proved that without
iL1(115Vrms)
vg(115Vrms)
4.0A
iL1(115Vrms
0A
-4.0A
200V
(a)
vg(115Vrms)
iL(230Vrms)
0V
-200V
40ms
50ms
60ms
70ms
80ms
(a)
4.0A
iL1(230Vrms)
vg(230Vrms)
0A
-4.0A
400V
(b)
vg(230Vrms)
0V
-400V
40ms
50ms
60ms
70ms
80ms
vout=50V DC
(b)
60V
50V
vout=50V DC
40V
200V
vg(115Vrms)
(c)
0V
iL1
-200V
40ms
50ms
60ms
70ms
80ms
(c)
2.0A
iL1
0A
vGS-S1
-2.0A
40V
vGS-S1
20V
0V
67.487ms
67.500ms
67.520ms
67.540ms
67.560ms
(d)
67.580ms
(d)
Fig. 5. Simulation results for (a) input voltage and input current with
|Vg|=115Vrms, (b) input voltage and input current with |Vg|=230Vrms, (c)
output voltage and, (d) input current and gate drive signal within each
switching period.
Fig. 6. Experimental results for (a) input voltage and input current with
|Vg|=115Vrms, (b) input voltage and input current with |Vg|=230Vrms, (c)
output voltage and, (d) input current and gate drive signal within each
switching period.
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93.0
92.5
Efficiency (%)
92.0
91.5
91.0
90.5
115Vrms
90.0
230Vrms
89.5
89.0
20
40
50
60
80
100
80
100
Power (W)
PF
(a)
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
IV.
115Vrms
230Vrms
20
40
50
60
CONCLUSIONS
Power (W)
(b)
Fig. 7. (a) The efficiency and (b) power factor for the proposed converter at
115Vrms and 230Vrms input voltages.
290