EC 252

ASSIGNMENT 4

Prepared by : Subhash Kumar Baghelkar (09116046)

B. T.ech IInd Year ECE

Development of microprocessors

INTEL 8086 microprocessor architecture : -

INTEL 8086 internal architecture

Here
BIU Bus interface unit
EU Execution unit
CS - Code Segment register
DS - Data Segment register
ES - Extra Segment register
SS - Stack Segment register
The BIU handles all transactions of data and addresses on the buses for EU.
The BIU performs all bus operations such as instruction fetching, reading and writing

operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch
and execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.

Memory
Program, data and stack memories occupy the same memory space. The total addressable
memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the
processor can effectively address only 64 KB of memory. To access memory outside of 64
KB the CPU uses special segment registers to specify where the code, stack and data 64 KB
segments are positioned within 1 MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
32-bit addresses are stored in " segment: offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment : offset pair is calculated as:
address = (<segment> * 16) + <offset>
Program memory - program can be located anywhere in memory. Jump and call instructions
can be used for short jumps within currently selected 64 KB code segment, as well as for far
jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to
jump within approximately +127 - -127 bytes from current instruction.

Data memory - the 8086 processor can access data in any one out of 4 available segments,
which limits the size of accessible memory to 256 KB (if all four segments point to different
64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually
done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions
by default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two memory
accesses to read 16-bit word located at odd byte boundaries. Reading word data from even
byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data Memory" above).
Reserved locations:

0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit
pointer in format segment : offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at
the FFFF0h address.

Interrupts
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help
of the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into
stack, disables further interrupts, fetches from the bus one byte representing interrupt type,
and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt
type>. Interrupt processing routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.

INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt
processing routine.

Processor exceptions: divide error (type 0), unused opcode (type 6) and escape
opcode (type 7).

Software interrupt processing is the same as for the hardware interrupts.

I/O ports
65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.

Registers
Most of the registers contain data/instruction offsets within 64 KB memory segment. There
are four different 64 KB segments for instructions, stack, data and extra data. To specify
where in 1 MB of processor memory these 4 segments are located the 8086 microprocessor
uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions.
It is possible to change default segments used by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and logic
operations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the
word, and CH contains the high-order byte. Count register can be used as a counter in string
manipulation and shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains highorder word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.

Instruction Set
Instruction set of Intel 8086 processor consists of the following instructions:

Data moving instructions.

Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.
Logic - AND, OR, exclusive OR, shift/rotate and test.
String manipulation - load, store, move, compare and scan for byte/word.
Control transfer - conditional, unconditional, call subroutine and return from
subroutine.
Input/Output instructions.
Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is
located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or
BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI
or DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an
index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a
pointer to location where data resides.

8086 Pin diagram & description

Intel 80186 microprocessor architecture

Memory
Program, data and stack memories occupy the same memory space. The total addressable
memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the
processor can effectively address only 64 KB of memory. To access memory outside of 64
KB the CPU uses special segment registers to specify where the code, stack and data 64 KB
segments are positioned within 1 MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as:
address: low-order byte
address+1: high-order byte
32-bit addresses are stored in "segment:offset" format as:
address: low-order byte of segment
address+1: high-order byte of segment
address+2: low-order byte of offset
address+3: high-order byte of offset
Physical memory address pointed by segment:offset pair is calculated as:
address = (<segment> * 16) + <offset>
Program memory - program can be located anywhere in memory. Jump and call instructions
can be used for short jumps within currently selected 64 KB code segment, as well as for far
jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to
jump within approximately +127 - -127 bytes from current instruction.
Data memory - the processor can access data in any one out of 4 available segments, which
limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB
blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by
prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by
default may use the ES or SS segments instead of DS segment).
Word data can be located at odd or even byte boundaries. The processor uses two memory
accesses to read 16-bit word located at odd byte boundaries. Reading word data from even
byte boundaries requires only one memory access.
Stack memory can be placed anywhere in memory. The stack can be located at odd memory
addresses, but it is not recommended for performance reasons (see "Data Memory" above).

Reserved locations:

0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit
pointer in format segment:offset.
FFFF0h - FFFFFh - after RESET the processor always starts program execution at
the FFFF0h address.

Interrupts
The processor has the following interrupts:
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help
of the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into
stack, disables further interrupts, fetches from the bus one byte representing interrupt type,
and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt
type>. Interrupt processing routine should return with the IRET instruction.
Integrated 80186 peripherals generate the following hardware interrupts (higher priority
interrupts are listed first):

Timer 0 - type 8
Timer 1 - type 18
Timer 2 - type 19
DMA 0 - type 10
DMA 1 - type 11
INT0 - type 12
INT1 - type 13
INT2 - type 14
INT3 - type 15.

Interrupt types 9, 16 (on 80186), 17, and 20 - 31 are reserved.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR
interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is
stored in location 0008h. This interrupt has higher priority then the maskable interrupt.
Software interrupts are non-maskable interrupts. They can be caused by:

INT instruction - breakpoint interrupt. This is a type 3 interrupt.

INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow. This is a type 4 interrupt.
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When
the CPU processes this interrupt it clears TF flag before calling the interrupt
processing routine.

Processor exceptions: divide error (type 0), array bounds exception (type 5), unused
opcode (type 6), escape opcode (type 7), and numeric co-processor exception (type
16, 80C186 only).

Software interrupt processing is the same as for the hardware interrupts. Software interrupts
have the same priority as the NMI interrupt.

I/O ports
65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.
Reserved ports:

00F8h - 00FFh
FF00h - FFFFh: 256-byte control block. This is a default block location after RESET.
If necessary, the block can be remapped to different place in I/O or memory space.
For description of the control block please see "Control registers" in the "Registers"
section below.

Registers
Most of the registers contain data/instruction offsets within 64 KB memory segment. There
are four different 64 KB segments for instructions, stack, data and extra data. To specify
where in 1 MB of processor memory these 4 segments are located the processor uses four
segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS register can be changed
directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions.

It is possible to change default segments used by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.
All general registers of the 80186 microprocessor can be used for arithmetic and logic
operations. The general registers are:
Accumulator register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.
Base register consists of 2 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.
Count register consists of 2 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low-order byte of the
word, and CH contains the high-order byte. Count register can be used as a counter in string
manipulation and shift/rotate instructions.
Data register consists of 2 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low-order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains highorder word of the initial or resulting number.
The following registers are both general and index registers:
Stack Pointer (SP) is a 16-bit register pointing to program stack.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register
indirect addressing, as well as a destination data address in string manipulation instructions.
Other registers:
Instruction Pointer (IP) is a 16-bit register.
Flags is a 16-bit register containing 9 1-bit flags:

Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
Direction Flag (DF) - if set then string manipulation instructions will auto-decrement
index registers. If cleared then the index registers will be auto-incremented.
Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.
Single-step Flag (TF) - if set then single-step interrupt will occur after the next
instruction.
Sign Flag (SF) - set if the most significant bit of the result is set.
Zero Flag (ZF) - set if the result is zero.
Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
AL register.
Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.

Control registers are used to control 80186 integrated peripherals. These 16-bit registers are
part of 256-byte control block that can be mapped into system RAM or I/O space. The control
block includes the following registers:

Interrupt control - 20h - 3Eh

Time 0 control - 50h (counter), 52h (max count A), 54h (max count B), and 56h
(control word)
Time 1 control - 58h (counter), 5Ah (max count A), 5Ch (max count B), and 5Eh
(control word)
Time 2 control - 60h (counter), 62h (max count A), and 66h (control word)
Chip-select control - A0h (upper memory), A2h (lower memory), A4h (peripheral),
A6h and A8h (mid-range memory)
DMA descriptors channel 0 - C0h and C2h (source pointer), C4h and C6h
(destination pointer), C8h (transfer count) and CAh (control word).
DMA descriptors channel 1 - D0h and D2h (source pointer), D4h and D6h
(destination pointer), D8h (transfer count) and DAh (control word).
Refresh Control Unit registers (80C186 in Enhanced mode only) - E0h - E4h
Power-Saving control (80C186 only) - F0h
Relocation register - FEh

After reset the control block is mapped at address FF00h in I/O space.

Instruction Set
80186 instruction set consists of the following instructions:

Data moving instructions.

Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.
Logic - AND, OR, exclusive OR, shift/rotate and test.
String manipulation - load, store, move, compare and scan for byte/word.

Control transfer - conditional, unconditional, call subroutine and return from

subroutine.
Input/Output instructions.
Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes
Implied - the data value/data address is implicitly associated with the instruction.
Register - references the data in a register or in a register pair.
Immediate - the data is provided in the instruction.
Direct - the instruction operand specifies the memory address where data is located.
Register indirect - instruction specifies a register containing an address, where data is
located. This addressing mode works with SI, DI, BX and BP registers.
Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or
BP), the resulting value is a pointer to location where data resides.
Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI
or DI), the resulting value is a pointer to location where data resides.
Based Indexed - the contents of a base register (BX or BP) is added to the contents of an
index register (SI or DI), the resulting value is a pointer to location where data resides.
Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the
contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a
pointer to location where data resides.

Intel 80286 microprocessor architecture

An 8MHz Intel 80286 Microprocessor

Architecture of Intel 80286

Key Features

16-bit date bus

24-bit non-multiplexed bus
Packaged in a 68-pin ceramic pack

80286 has 2 24 = 16 M Byte of physical memory accessibility

Basic Architecture of 80286

Memory Bank
Memory of 80286 is setup as an odd bank and an even bank, just as it is for the 8086.
The even bank is enabled when A 0 is low and the odd bank is enabled when
is
low. To access an aligned word, both A 0
will be low.

Memory banks in 80286

Memory Addressing in 80286
1.

Real Addressing Mode - It is just like as in 8086. Address is 20 bit with 16 bit
segment and 16 bit offset. When 80286 is hardware reset, it automatically
enters real address mode.
2. Protected Virtual Addressing Mode (PVAM) - In this we have 1 GByte of
virtual memory and 16 Mbyte of physical memory. The address is 24 bit. To
enter PVAM mode, Processor Status Word (PSW) is loaded by the instruction
LPSW.

Load Processor Status Word

PE - Protection Enable
MP - Monitor Processor Extension

EM - Emulate Processor Extension

TS - Task Switch
Hardware reset is the only way to come out of protected mode.
80286 Memory Management Scheme Memory is organized into logical segments.
Segment size can be anywhere between 1 Byte to 16 KByte. All 24 address pins are
active and 16 MByte of physical memory is available.
Descriptor
It is 8-byte quantity. Each segment has a descriptor. There are two main types of
descriptor

Segment Descriptor
System control Descriptor

Format of a Descriptor

Descriptor Format
80286 Interrupt Handling
Real addressing mode has 256 interrupts with types 0-255. Each interrupt takes 4 bytes, so we
have to reserve 1KByte of memory for interrupt.
In PVAM mode also we have 256 interrupts but it is not assigned a fixed memory. The
interrupt descriptor table can be anywhere in the physical memory. Base address of interrupt
descriptor table is stored in interrupt descriptor table register (IDTR). The particular
descriptor is accessed as follows (Interrupt Type * 8) + IDTR

Descriptor

Intel 80386 microprocessor architecture

Memory Model
The 80386 has two available memory models to choose from. A "Flat" model and a
Segmented Model. The "Flat" memory model is basically a single segment. A single segment
can address up to 4Gb of memory ((2^32) - 1). The segmented model can consist of 16,383
segments.

Processor Registers
There are sixteen registers that are of use to general purpose programmers. (There are several
other registers for system level programming that are not discussed in this guide.)

General Registers
There are 8 general purpose, 32-bit registers in the 80386. They are EAX, EBX, ECX, EDX,
EBP, ESP, ESI, and EDI. Each register can hold a doubleword containing any of the data
types listed above.
A backwards compatible feature is built into the 80386. The lower word of each register can
be addressed as a separate unit. This is useful for handling 16-bit data items and for
compatibility with older 8086 and 80286 programs. The registers are named AX, BX, CX,
DX, BP, SP, SI and DI. Note, the upper word of each register cannot be addressed separately.

Segment Registers
There are six segment registers, CS, DS, SS, ES, FS, and GS. They are used to identify the
current six segments in use by a program. The CS registers contains the address of the
currently running code segment. The DS register contains the address of the currently
accessible data segment. The SS register contains the address of the current stack segment.
The ES, FS, and GS registers contains additional segments as required by the program.

Stack Implementation
The 80386 allows for multiple stacks, with each stack being a separate segment. The stack
pointer (ESP) register points to the top of the stack. The stack is a push-down stack, and is
referenced implicitly by PUSH and POP instructions, subroutine calls and returns and
interrupt operations. When an item is pushed on the stack, ESP is first decremented, then the
data is written to the new ESP location. The opposite occurs when data is popped off the
stack. The data is first copied out of the stack, then the ESP is incremented. The stack grows
down in memory toward lesser addresses.
The stack frame base pointer (EBP) register is the best register to use for accessing data
within the stack. It typically identifies the base address of the current stack frame in use by
the current procedure. When this register is used in an offset calculation, the data is

automatically fetched from the stack segment. This means the stack segment does not have to
be included in the instruction, making for a more compact instruction.

Flags Register
The flags register is a 32-bit register named EFLAGS. The low-order 16 bits of EFLAGS is
named FLAGS for compatibility with older 8086 and 80286 code. There are three basic
groups of flags, status flags, control flags and the system flags. The flags are as follows:
16
------------------------------------X
--X-

15
-----------------------------XX
-X--------

------------------X
--X-X-X---------------

---------X
-X-X---------------------------

0
---X
-X-----------------------------------

CF
PF
AF
ZF
SF
TF
IF
DF
OF
PL
NT
RF
v8

Carry Flag
Parity Flag
Auxiliary Carry
Zero Flag
Sign Flag
Trap Flag
Interrupt Flag
Direction Flag
Overflow Flag
I/O Privilege Level
Nested Task Flag
Resume Flag
Virtual 8086 MODE

The remaining bits are reserved for future Intel use. A flag is considered cleared when it is
zero, set when it is 1.
The status flags used by application programmers are CF, PF, AF, ZF, SF, and OF. These
flags hold the results of various instructions that are then used by later instructions. What
follows is a brief description of each flag.

Carry Flag: Set in math instructions to indicate that the high-order bit was either
carried or borrowed. It is cleared if neither of these conditions occur.
Parity Flag: Indicates whether the lower 8-bits of a result contains an even number of
bits set to 1 (flag is set) or an odd set of bits are set to 1 (flag is cleared)
Adjust Flag: Set in decimal math instructions to indicate whether the low order 4-bits
of AL where carried, or borrowed. It is cleared if not.
Zero Flag:Set to indicate a math instruction resulted in a zero result. It is cleared
otherwise. It is also used by string and loop instructions to indicate completion of the
instruction.
Sign Flag:Set equal to high-order bit of results of math instruction. If set the result is
negative, positive if cleared.
Overflow Flag:Indicates if the number placed in the destination operand overflowed,
either too large, or small. If no overflow occurred, the bit is cleared.

The only control flag at this time is the Direction Flag. It is used by string instructions to
determine whether to process strings from the end of the string (auto-decrement), or from the
beginning of the string (auto-increment).
The other flags are system flags. Refer to the 80386 Programmers guide for further
information on these flags.
Instruction Pointer
The instruction pointer register (EIP) contains the offset into the current code segment. It is a
32-bit value. The lower 16-bit field is addressable as a single unit for backwards
compatibility, and is named IP. The programmer should not fiddle with this register. It is
controlled by instructions that transfer control of the program such as jump instructions,
interrupts, and exceptions.

Intel 80486 microprocessor architecture

The 32-bit 80486 is the next evolutionary step up from the 80386.
One of the most obvious feature included in a 80486 is a built in math coprocessor.
This coprocessor is essentially the same as the 80387 processor used with a 80386,
but being integrated on the chip allows it to execute math instructions about three
times as fast as a 80386 combination.
80486 is an 8Kbyte code and data cache.
To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid
array package instead of the 132 pin PGA used for the 80386.

80486 Memory System

The memory system for the 486 is identical to 386 microprocessor. The 486 contains
4G bytes of memory beginning at location 00000000H and ending at FFFFFFFFH.
The major change to the memory system is internal to 486 in the form of 8K byte
cache memory, which speeds the execution of instructions and the acquisition of
data.
Another addition is the parity checker/ generator built into the 80486 microprocessor.
Parity Checker / Generator : Parity is often used to determine if data are correctly
read from a memory location. INTEL has incorporated an internal parity generator /
decoder.
Parity is generated by the 80486 during each write cycle. Parity is generated as even
parity and a parity bit is provided for each byte of memory. The parity check bits
appear on pins DP0-DP3, which are also parity inputs as well as parity outputs.
These are typically stored in memory during each write cycle and read from memory
during each read cycle.

On a read, the microprocessor

essor checks parity and generates a parity check error, if it
occurs on the PCHK# pin. A parity error causes no change in processing unless the
user applies the PCHK signal to an interrupt input.
Interrupts are often used to signal a parity error in DS-based
DS
computer systems. This
is same as 80386, except the parity bit storage.
If parity is not used, Intel recommends that the DP0 DP3 pins be pulled up to +5v.
CACHE MEMORY: The cache memory system stores data used by a program and
also the instructions of the program. The cache is organised as a 4 way set associative
cache with each location containing 16 bytes or 4 doublewords of data.
Control register CR0 is used to control the cache with two new control bits not
present in the 80386 microprocessor.

Control Register Zero ( CR0)For The 80486 Microprocessor

The CD ( cache disable ) , NW ( non-cache

non
write through ) bits are new to the 80486
and are used to control the 8K byte cache.
If the CD bit is a logic 1, all cache operations are inhibited. This setting is only used
for debugging software and normally remains cleared. The NW bit is used to inhibit
cache write-through
through operation. As with CD, cache write through is inhibited only for
testing. For normal operations
erations CD = 0 and NW = 0.
Because the cache is new to 80486 microprocessor and the cache is filled using burst
cycle not present on the 386.

80486 Memory Management

The 80486 contains the same memory-management

memory
system as the 80386. This
includes a paging unit to allow any 4K byte block of physical memory to be assigned
to any 4K byte block of linear memory. The only difference between 80386 and
80486 memory-management
management system is paging.
The 80486 paging system can disabled caching for section of translation memory
pages, while the 80386 could not.
If these are compared with 80386 entries, the addition of two new control bits is
observed ( PWT and PCD ).
The page write through and page cache disable bits control caching.

The PWT controls how the cache functions for a write operation of the external cache
memory. It does not control writing to the internal cache. The logic level of this bit is
found on the PWT pin of the 80486 microprocessor. Externally, it can be used to
dictate the write through policy of the external caching.
The PCD bit controls the on-chip cache. If the PCD = 0, the on-chip cache is enabled
for the current page of memory.
Note that 80386 page table entries place a logic 0 in the PCD bit position, enabling
caching. If PCD = 1, the on-chip cache is disable. Caching is disable regard less of
condition of KEN#, CD, and NW.

Cache Test Registers

The 80486 cache test registers are TR3, TR4, TR5.

Cache data register (TR3) is used to access either the cache fill buffer for a write test
operation or the cache read buffer for a cache read test operation.
In order to fill or read a cache line ( 128 bits wide ), TR3 must be written or read four
times.
The contents of the set select field in TR5 determine which internal cache line is
written or read through TR3. The 7 bit test field selects one of the 128 different 16
byte wide cache lines. The entry select bits of TR5 select an entry in the set or the 32
bit location in the read buffer.
The control bits in TR5 enable the fill buffer or read buffer operation ( 00 )
Perform a cache write ( 01 ), Perform a cache read ( 10 )
Flush the cache ( 11 ).
The cache status register (TR4) hold the cache tag, LRU bits and a valid bit. This
register is loaded with the tag and valid bit before a cache a cache write operation and
contains the tag, valid bit, LRU bits, and 4 valid bits on a cache test read.
Cache is tested each time that the microprocessor is reset if the AHOLD pin is high
for 2 clocks prior to the RESET pin going low. This causes the 486 to completely test
itself with a built in self test or BIST.
The BIST uses TR3, TR4, TR5 to completely test the internal cache. Its outcome is
reported in register EAX. If EAX is a zero, the microprocessor, the coprocessor and
cache have passed the self test.
The value of EAX can be tested after reset to determine if an error is detected. In
most of the cases we do not directly access the test register unless we wish to perform
our own tests on the cache or TLB.