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1. Write the features of 8085.

Single + 5V Supply

100% Software Compatible withm 8080A

1.3 US Instruction Cycle

On Chip Clock Generator (with External Crystal or RC Network)

On Chip System Controller; Advanced Cycle Status Information Available for Large System Control

4 Vectored Interrupts (One is Non Maskable)

Serial In/Serial Out Port

Decimal, Binary, and Double Precision Arithmetic

Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU). Its instruction set is 100% software compatible with the 8080A
microprocessor, and it is designed to improve the present 8080's performance by higher system speed. Its high level of system integration allows a minimum
system of 3 IC's: 8085A (CPU), 8156 (RAM), and 8355/ 8755A (ROM/PROM).
The 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided for the 8080, thereby offering a high level of
system integration.
The 8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit data bus. The on chip address latches of
8155/8156/8355/8755A memory products allows a direct interface with the 8085A.

2. Explain the architecture of 8085.

INTEL 8085 CPU BLOCK DIAGRAM MICROPROCESSORS

Figure: Intel 8085 CPU Block Diagram

The 8085A is a complete 8 bit parallel central processor. It is designed with N channel depletion loads and requires a single t5 volt supply Its basic clock speed
is 3 MHz thus improving on the present 8080's performance with higher system speed. Also it is designed to fit into a minimum system of three IC's: The CPU,
a RAM/ IO, and a ROM or PROM/IO chip.

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The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus. During the first cycle
the address is sent out. The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE). During the rest of the machine cycle the Data Bus
is used for memory or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold, Ready, and all
Interrupts are synchronized. The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface.
In addition to these features, the 8085A has three maskable, restart interrupts and one nonmaskable trap

interrupt.

General Purpose Register

It looks like Scratch pad register. Some register inside microprocessor to scratch for temporary storage of data. Size of register in generally
equal to word length.
8085 ===> 8 bit
8086 ===> 16 bit
386,486 ===> 32 bit
All three above are A, B, C, D, E, H, L
A, B, C can be used as single 8 bit register and also can be used as pairs.
Flag Register
5 Flip-flops
- Signify different condition in ALU takes place.
(1) Carry Flag - F/F is set when there is carry in result.
(2) Zero Flag - It set to 1 when result = 0 useful to compare the two number.
(3) Sign Flag - Identify either the number is +ve or -ve.
(4) Parity Flag - Used to add up parity bit in the system.
- Data is change on the way
- Make a noise of electricity.
(5) AC Flag - Is used by ALU to BCD addition , attach to ALU.
Temporary Registers.
Used for temporary storage of data by a CPU. It is not reliable to users.
Program Counter ----> Address lines ----> Memory ----> Data
---->CPU ---> Operation Code Buffer ------> Decoder-----> Timing.
Explanation
Microprocessors used to read and write from memory .There,
operation code register was stored. CPU will issue address on
address lines using program counter. Memory will issue operation code which will be stored in operation code buffer. The output of
operation code is decoder using 8 decoder to understand the memory
of code/instruction. Output of decoder given to timing to generate internal and external control signals for execution and instruction
The 8085A includes the following features on chip in addition to all of the 8080A functions.

Internal clock generator

Clock output

Fully synchronized Ready

Schmitt action on RESET IN

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RESET OUT pin

RD, WR, and IO/M Bus Control Signals

Encoded Status information

Multiplexed Address and Data

Direct Restarts and nonmaskable Interrupt

Serial Input/Output lines.

The internal clock generator requires an external crystal or RC network. It will oscillate at twice the basic CPU operating frequency. A 50% duty cycle, two
phase, nonoverlapping clock is generated from this oscillator internally and one phase of the clock (2) is available as an external clock. The 8085A directly
provides the external RDY synchronization previously provided by the 8224. The RESET IN input is provided with a Schmitt action input so that power on
reset only requires a resistor and capacitor. RESET OUT is provided for System RESET.
The 8085A provides RD, WR and IO/M signals for Bus control. An INTA which was previously provided by the 8228 in 8080 system is also included in
8085A.
Status Information
Status information is directly available from the 8085A. ALE serves as a status strobe. The status is partially encoded, and provides the user with advanced
timing of the type of bus transfer being done. IO/M cycle status signal is provided directly also. Decoded So ,S carries the following status information:
HALT
WRITE
READ
FETCH
S1 can be interpreted as R/W in all bus transfers.
In the 8085A the 8 LSB of address are multiplexed with the data instead of status. The ALE line is used as a strobe to enter the lower half of the address into
the memory or peripheral address latch. This also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080 INT Each of three RESTART inputs,
5.5, 6.5. 7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable.
The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RST independent of the state of the
interrupt enable or masks.

. Explain the pin configuration of 8085.

|
|

_________ _________

_|

--> X1 |_|1

_|

--> X2 |_|2

_|

\__/

|_

_|

<-- SOD |_|4

_|

--> SID |_|5

40|_| Vcc (+5V)

|_

|
39|_| HOLD <--

|_

| <-- RESET OUT |_|3

|

|
|

38|_| HLDA -->

|_

|
|

37|_| CLK (OUT) --> |

|_ ________
36|_| RESET IN <--

|
|

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|

_|

--> TRAP |_|6

_|

|
|
|
|
|

35|_| READY <-|_

_|

<--> AD0 |_|12

_|

<--> AD1 |_|13

_|

<--> AD2 |_|14

_|

<--> AD3 |_|15

_|

<--> AD4 |_|16

_|

<--> AD5 |_|17

_|

<--> AD6 |_|18

_|

<--> AD7 |_|19

_|

(Gnd) Vss |_|20

32|_| RD -->
|_ __
8085A

____ _|
<-- INTA |_|11

|_ __

--> RST 5.5 |_|9

33|_| S1 -->

_|

--> INTR |_|10

|_

--> RST 6.5 |_|8

34|_| IO/M -->

_|

_|

--> RST 7.5 |_|7

|_

|
|

31|_| WR -->

|_

|
30|_| ALE -->

|_

|
29|_| S0 -->

|_

|
28|_| A15 -->

|_

|
27|_| A14 -->

|_

|
26|_| A13 -->

|_

|
25|_| A12 -->

|_

|
24|_| A11 -->

|_

|
23|_| A10 -->

|_

|
22|_| A9 -->

|_

|
|

21|_| A8 -->

|______________________|

|
|

|
The following describes the function of each pin :
A6 A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.
ADo 7 (Input/Output 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then
becomes the data bus during the second and third clock cycles.3 stated during Hold and Halt modes.

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ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chiplatch of peripherals. The
falling edge of ALE isset to guarantee setup and hold times for the address information . ALE can also be used to strobe the status information. ALE is never 3
stated.
SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 So
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.
RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer. 3stated during Hold and Halt.
WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during
Hold and Halt modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of
buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is
removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low
after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction.
If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction
can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt
is accepted.
INTA(Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to
activate the 8259 Interrupt chip or some other interrupt port.
RST5.5
RST 6.5 - (Inputs)
RST7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5

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RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest
priority of any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register)
are affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided
by 2 to give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
Vcc
+5 volt supply.
Vss
Ground Reference.
4. Explain 8085 machine cycle.
The 8085 has seven machine cycles. These are
1.Opcode fetch
2.Memory Read
3.Memory Write
4.I/O Read
5.I/O Write
6.Interrupt Acknowlege
7.Bus Idle.
5. Explain the data transfer instructions available in 8085.
Instruction Naming Conventions:
The mnemonics assigned to the instructions are designed to indicate the function of the instruction. The instructions fall into the following functional
categories:

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Data Transfer Croup:

The data transfer instructions move data between registers or between memory and registers.
MOV

Move

MVI

Move Immediate

LDA

Load Accumulator Directly from Memory

STA

Store Accumulator Directly in Memory

LHLD

Load H & L Registers Directly from

SHLD

Store H & L Registers Directly in Memory

Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits);
LXI

Load Register Pair with Immediate data

LDAX

Load Accumulator from Address in

Register Pair

STAX

Store Accumulator in Address in Register

Pair

XCHG

Exchange H & L with D & E

XTHL

Exchange Top of Stack with H & L

6. Explain the arithmetic instructions available in 8085.

Arithmetic Group:
The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.
ADD

Add to Accumulator

ADI

Add Immediate Data to Accumulator

ADC

Add to Accumulator Using Carry Flag

ACI

Add Immediate data to Accumulator Using Carry

SUB

Subtract from Accumulator

SUI

Subtract Immediate Data from

Accumulator

SBB

Subtract from Accumulator Using Borrow

(Carry) Flag

SBI

Subtract Immediate from Accumulator Using Borrow (Carry) Flag

INR

Increment Specified Byte by One

DCR

Decrement Specified Byte by One

INX

Increment Register Pair by One

DCX

Decrement Register Pair by One

DAD

Double Register Add; Add Content of

Register
Pair to H & L Register Pair

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7. Explain logical instructions available in 8085.

Logical Group:
This group performs logical (Boolean) operations on data in registers and memory and on condition flags.
The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or OFF.
ANA

Logical AND with Accumulator

ANI

Logical AND with Accumulator Using Immediate Data

ORA

Logical OR with Accumulator

OR

Logical OR with Accumulator Using Immediate Data

XRA

Exclusive Logical OR with Accumulator

XRI

Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;
CMP

Compare

CPI

Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position to the left or right:
RLC

Rotate Accumulator Left

RRC

Rotate Accumulator Right

RAL

Rotate Left Through Carry

RAR

Rotate Right Through Carry

Complement and carry flag instructions:

CMA

Complement Accumulator

CMC

Complement Carry Flag

STC

Set Carry Flag

8. Explain branch instructions available in 8085.

Branch Group:
The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as
follows:
JMP

Jump

CALL

Call

RET

Return

Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions
that may be specified are as follows:
NZ

Not Zero (Z =0)

Zero (Z = 1)

NC

No Carry (C =0)

Carry (C = 1)

PO

Parity Odd (P= 0)

PE

Parity Even (P= 1)

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P

Plus (S = 0)

Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps

Calls

Returns

CC

RC

(Carry)

INC

CNC

RNC

(No Carry)

JZ

CZ

RZ

(Zero)

JNZ

CNZ

RNZ

(Not Zero)

JP

CP

RP

(Plus)

JM

CM

RM

(Minus)

JPE

CPE

RPE

(Parity Even)

JP0

CPO

RPO

(Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program counter:
PCHL

Move H & L to Program Counter

RST

Special Restart Instruction Used with Interrupts

Stack I/O, and Machine Control Instructions:

The following instructions affect the Stack and/or Stack Pointer:
PUSH

Push Two bytes of Data onto the Stack

POP

Pop Two Bytes of Data off the Stack

XTHL

Exchange Top of Stack with H & L

SPHL

Move content of H & L to Stack Pointer

The I/0 instructions are as follows:

IN

Initiate Input Operation

OUT

Initiate Output Operation

The Machine Control instructions are as follows:

EI

Enable Interrupt System

DI

Disable Interrupt System

HLT

Halt

NOP

No Operation

9. Explain various addressing modes of 8085 of addressing the hardware registers

and/or memory.
Implied Addressing:
The addressing mode of certain instructions is implied by the instructions function. For example, the STC (set carry flag) instruction deals only with the carry
flag, the DAA (decimal adjust accumulator) instruction deals with the accumulator.
Register Addressing:
Quite a large set of instructions call for register addressing. With these instructions, you must specify one of the registers A through E, H or L as well as the
operation code. With these instructions, the accumulator is implied as a second operand. For example, the instruction CMP E may be interpreted as 'compare
the contents of the E register with the contents of the accumulator.

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Most of the instructions that use register addressing deal with 8-bit values. However, a few of these instructions deal with 16-bit register pairs. For example,
the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers.

Immediate Addressing:
Instructions that use immediate addressing have data assembled as a part of the instruction itself. For example, the instruction CPI 'C' may be interpreted as
compare the contents of the accumulator with the letter C. When assembled, this instruction has the hexadecimal value FE43. Hexadecimal 43 is the internal
representation for the letter C. When this instruction is executed, the processor fetches the first instruction byte and determines that it must fetch one more byte.
The processor fetches the next byte into one of its internal registers and then performs the compare operation.
Notice that the names of the immediate instructions indicate that they use immediate data. Thus, the name of an add instruction is ADD; the name of an add
immediate instruction is ADI.
All but two of the immediate instructions uses the accumulator as an implied operand, as in the CPI instruction shown previously.
The MVI (move immediate) instruction can move its immediate data to any of the working registers including the accumulator or to memory. Thus, the
instruction MVI D, OFFH moves the hexadecimal value FF to the D register.
The LXI instruction (load register pair immediate) is even more unusual in that its immediate data is a 16-bit value.
This instruction is commonly used to load addresses into a register pair. As mentioned previously, your program must initialize the stack pointer; LXI is the
instruction most commonly used for this purpose. For example, the instruction LXI SP,3OFFH loads the stack pointer with the hexadecimal value 30FF.
Direct Addressing:
Jump instructions include a 16-bit address as part of the instruction. For example, the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by
replacing the current contents of the program counter with the new value 1000H.
Instructions that include a direct address require three bytes of storage: one for the instruction code, and two for the 16-bit address
Register Indirect Addressing:
Register indirect instructions reference memory via a register pair. Thus, the instruction MOV M,C moves the contents of the C register into the memory
address stored in the H and L register pair. The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register
pair.
Combined Addressing Modes:
Some instructions use a combination of addressing modes. A CALL instruction, for example, combines direct addressing and register indirect
addressing.
The direct address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL
instruction pushes the current contents of the program counter into the memory location specified by the stack pointer.

10. Explain stack operations in 8085.

The STACK
The stack is one of the most important things you must know when programming. Think of the stack as a deck of cards. When you put a card on the deck, it
will be the top card. Then you put another card, then another. When you remove the cards, you remove them backwards, the last card first and so on. The stack
works the same way, you put (push) words (addresses or register pairs) on the stack and then remove (pop) them backwards. That's called LIFO, Last In First
Out.
The 8085 uses a 16 bit register to know where the stack top is located, and that register is called the SP (Stack Pointer). There are instructions that allow you to
modify its contents but you should NOT change the contents of that register if you don't know what you're doing!
PUSH & POP
As you may have guessed, push and pop pushes bytes on the stack and then takes them off. When you push something, the stack counter will decrease with 2
(the stack "grows" down, from higher addresses to lower) and then the register pair is loaded onto the stack. When you pop, the register pair is first lifted of the
stack, and then SP increases by 2.
N.B: Push and Pop only operate on words (2 bytes ie: 16 bits).
You can push (and pop) all register pairs: BC, DE, HL and PSW (Register A and Flags). When you pop PSW, remember that all flags may be changed. You
can't push an immediate value. If you want, you'll have to load a register pair with the value and then push it. Perhaps it's worth noting that when you push
something, the contents of the registers will still be the same; they won't be erased or something. Also, if you push DE, you can pop it back as HL (you don't
have to pop it back to the same register where you got it from).
The stack is also updated when you CALL and return from subroutines. The PC (program counter which points at the next instruction to be executed) is pushed
to the stack and the calling address is loaded into PC. When returning, the PC is loaded with the word popped from the top of the stack (TOS).

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So, when is this useful? It's almost always used when you call subroutines. For example, you have an often used value stored in HL. You have to call a
subroutine that you know will destroy HL (with destroy I mean that HL will be changed to another value, which you perhaps don't know). Instead of first
saving HL in a memory location and then loading it back after the subroutine, you can push HL before calling and directly after the calling pop it back. Of
course, it's often better to use the pushes and pops inside the subroutine.
All registers you know will be changed are often pushed in the beginning of a subroutine and then popped at the end, in reverse order! Don't forget - last in first
out. If you want to only push one 8 bit register, you still have to push it's "friend". Therefore, be aware that if you want to store away D with pushing and
popping, remember that E will also be changed back to what it was before. In those cases, if you don't want that to happen, you should try first to change
register (try to store the information in E in another register if you can) or else you have to store it in a temporary variable.
Before executing a program, you should keep track of your pushes and pops, since they are responsible for 99% of all computer crashes! For example, if you
push HL and then forget to pop it back, the next RET instruction will cause a jump to HL, which can be anywhere in the ROM/RAM and the computer will
crash. Note however, its also a way to jump to the location stored in HL, but then you should really use the JMP instruction, to do the same thing.
Push and pop doesn't change any flags, so you can use them between a compare and jump instructions, depending on a condition, which is often very useful.

11. Explain 8085 interrupts.

Interrupts
In a typical computer system, the software can be divided into 3 possible groups. One is the Operating Loop, another is the Interrupt Service Routines, and the
last is the BIOS/OS functions and subroutines.
The Operating Loop is the main part of the system. It will usually end up being a sequence of calls to BIOS/OS subroutines, arranged in an order that
accomplishes what we set out to do, with a little manipulation and data transfer in between.
At the same time, at least it looks like it's happening at the same time, interrupts are being serviced as they happen. In the 8085, there are thirteen (13) possible
events that can trigger an interrupt. Five of them are from external hardware interrupt inputs (TRAP, RST 7.5, 6.5, 5.5, and INTR), that can be from whatever
hardware we've added to the 8085 that we deem to need servicing as soon as they happen. The remainder are software instructions that cause an interrupt when
they are executed (RST 0 7).
. One is to scan or poll them and the other is to use interrupts. Scanning is just what is sounds like. Each possible event is scanned in a sequence, one at a time.
This is ok for things that don't require immediate action. Interrupts, on the other hand, cause the current process to be suspended temporarily and the event that
caused the interrupt is serviced, or handled, immediately.
The routine that is executed as a result of an interrupt is called the interrupt service routine (ISR), or recently, the interrupt handler routine.
In the 8085, as with any CPU that has interrupt capability, there is a method by which the interrupt gets serviced in a timely manner.
When the interrupt occurs, and the current instruction that is being processed is finished, the address of the next instruction to be executed is pushed onto the
Stack. Then a jump is made to a dedicated location where the ISR is located.. Some interrupts have their own vector, or unique location where it's service
routine starts. These are hard coded into the 8085 and can't be changed (see below).
TRAP

- has highest priority and cannot be masked or disabled. A rising-edge pulse will cause a jump to location 0024H.

RST 7.5- 2nd priority and can be masked or disabled. Rising-edge pulse will cause a jump to location 7.5 * 8 = 003CH.
This interrupt is latched internally and must be reset before it can be used again.
RST 6.5 3rd priority and can be masked or disabled. A high logic level will cause a jump to location 6.5 * 8 = 0034H.
RST 5.5 4th priority and can be masked or disabled. A high logic level will cause a jump to location 5.5 * 8 = 002CH.
INTR

5th priority and can be masked or disabled. A high logic level will cause a jump to specific location as follows:

When the interrupt request (INTR) is made, the CPU first completes its current execution. Provided no other interrupts are pending, the CPU will take the
INTA pin low thereby acknowledging the interrupt.
It is up to the hardware device that first triggered the interrupt, to now place an 8-bit number on the data bus, as the CPU will then read whatever number it
finds on that data bus and do the following: multiply it by 8 and jump to the resulting address location. Since the 8-bit data bus can hold any number from 00
FFH (0 255) then this interrupt can actually jump you to any area of memory between 0*8 and 255*8 ie: 0000 and 07FFH ( a 2K space). N.B: This interrupt
does not save the PC on the stack, like all other hardware and software interrupts!
You will notice that there isn't many locations between vector addresses. What is normally done is that at the start of each vector address, a jump instruction (3
bytes) is placed, that jumps to the actual start of the service routine which may be in RAM..
This way the service routines can be anywhere in program memory. The vector address jumps to the service routine. There is more than enough room between
each vector address to put a jump instruction. Looking at the table above, there are at least 8 locations for each of the vectors except RST 5.5, 6.5, and 7.5.
When actually writing the software, at address 0000h will be a jump instruction that jumps around the other vector locations.
Besides being able to disable/enable all of the interrupts at once (DI / EI) ie: except TRAP, there is a way to enable or disable them individually using the SIM
instruction and also, check their status using RIM.

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There are other things about interrupts that we will cover as they come up, but this lesson was to get you used to the idea of interrupts and what they're used for
in a typical system. Its similar to the scene where one is standing at a busy intersection waiting for the traffic light to change, when a person came up and
tapped us on the shoulder and asked what time it was. It didn't stop us from going across the street, it just temporarily interrupted us long enough to tell them
what time it was. This is the essence of interrupts. They interrupt normal program execution long enough to handle some event that has occurred in the system.
Polling, or scanning, is the other method used to handle events in the system. It is much slower than interrupts because the servicing of any single event has to
wait its turn in line while other events are checked to see if they have occurred. There can be any number of polled events but a limited number of interrupt
driven events. The choice of which method to use is determined by the speed at which the event must be handled.
The software interrupts are the instructions RST n, where n = 0 7. The value n is multiplied by 8 and the result forms an address that the program jumps to as
it vector address ie: RST 4 would jump to location 4*8 = 32 (20H).

12. Comparison between memory mapped i/o &i/o mapped i/o.

S.No

Memory mapped I/O I/Omapped I/O

1
In this device address is 16 bit. A0-A15 lines are used to generate device address.
lines are used to generate device address.
2

In this device address is 8 bit. Thus A0 A7 or A8-A15

-------- ----------

MEMR,MEMW control signals are used to control read &write I/O operations.
------ -----IOR, IOW control signals are used to control read &write I/O operations.
3

Data transfer is between any register and I/O device.

Data transfer is between Accumulator and I/O device.

Maximum number of I/O devices are 65536. Maximum number of I/O devices are 256.

5.

Decoding 16 bit address may require more hardware.

Decoding 16 bit address may require less hardware.

14. Add two 4 digit BCD number in HL and DE register pairs and store result in memory l0cation. 2300H and 2301H
Problem:
(HL) =

3629

(DE)=

4738

Step 1:

29+38=61 auxiliary carry flag =1

add 06
61+06=67

Step 2 :

36+47+0(carry of LSB) =7D

Lower nibble of addition is greater than 9
So add 6.
7D +06= 83

Result = 8367
Source Program:
MOV A,L ; Get lower 2 digits of no.1
ADD E

; Add two lower digits

DAA

; Adjust result to valid BCD

STA 2300H ; Store partial result

MOV A,H
ADC D

; Get most significant 2 digits of no.2

; Add two most significant digits

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DAA

; Adjust result to valid BCD

STA 2300H ; Store partial result

HLT

; Terminate program execution.

15. Explain different type of Data transfer instructions with suitable examples.
Data Transfer Group:
The data transfer group instructions load the given data into register, copy data from register to register, and copy data from register to memory
location and vice versa. This group consists of following set of instructions. These instructions do not affect any flag in the flag register.
1.

MVT r, data (8 bit)

2.

MVI M, data (8-bit)

3.

MOV rd, rs

4.

MOV M, rs

5.

MOV RD, m

6.

LXI rp, data (16 BIT)

7.

STA addr

8.

LDA addr

9.

SHLD addr

10.

LHLD addr

11.

STAX rp

12.

LDAX rp

13.

XCHG

1. MVI r, data (8) : Move 8 bit immediate data to register r.

Operation

: r 8-bit data (byte)

Description
: This instruction directly loads a specified register with an 8-bit data given within the instruction. The register r is an 8-bit general
purpose register such as A,B,C,D,E,H and L
No. of bytes

: 2 bytes
First byte: Opcode of MVI r
Second byte : g-bit data

No. of T- states
Addressing mode

: Require 7 t- states for execution.

: Immediate addressing

Flags
Example
MVI B, 60H
2. MVI M, data (8)
Operation

: flags are not affected

:
: This instruction will load 60H directly into the B register.
: Move 8 bit immediate data to memory whose address is in Hl register pair.
: M byte or (HL) byte

Description
: This instruction directly loads an 8-bit data given with the instruction into a memory location. The memory location is specified by
the contents of HL register pair.
No. of bytes

: 2 bytes

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First byte : Opcode of MVI M.
Second byte: 8 bit data
No. of T- states

: Require10T- states for execution

Addressing mode

: immediate and indirect addressing

Flags

: Flags are not affected.

Example

: H =20H and L =50H

MVI M, 40H : This instruction will load 40H into

: memory whose address is 2050H

3. Mov rd, rs

: Move data from source regiser (rs) to destination register (rd)

Operation

: rd rs

Description : This instruction copies data from the source register into destination register .the rs and rd are general-purpose registers such as A,B,C,D,E,H
and L. The contents of the source register remain unchanged after execution of the instruction.
No. of bytes

: 1 byte
Opcode of MOV rd,rs

No. of T-states :Requires 4 T- states for execution.

Addressing mode : Register addressing
Flags : Flags are not affected.
Example

: A= 20H

MOV B,A

: Thus instruction will copy the contents of register A(20H) into register B.

4. Mov M,rs

: Move data from source register (rs) to memory whose address is HL register pair.

Operation

: (HL) rs.

Description

: This instruction repies data from the

source register into memory location

pointed by the HL register pair. The
rs is an 8-bit general purpose
register such as A,B,C,D,E,H and L.
No of bytes: 1 byte
Opcode of MOV M.rs
No of T.states : Requires 7 T-states for execution
Addressing mode : Indirect addressing
Flags : flags are not affected
Examples : If HL = 2050H, B=30H
Mov M,B

: This institution will copy the contents

: of B register (30H) into the memory location
: Whose address is verified by HL (2050H)

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5. MOV rd, M

: Move data from memory location

specified by HL register pair to the destination register (rd)

: rd (HL)

Operation

Description
: This instruction copies data from memory location whose address is specified by Hl register pair into destination register . the contents of
the memory location remain unchanged. The rd is an 8-bit general-purpose register such as A,B,C,D,E,H and L.
No. of bytes : 1 byte
Opcode of MOV d,M
No of T- states: Requires 7 T-state for execution
Addressing mode : Indirect addressing.
Flags : Flags are not affect
Example ; HL =2050H, contents at 200H memory location =40H
MOV C,M

: This instruction will copy the contents

Of memory location pointed by HL.
: register pair(40H) into the C register.

6. LXI rp , data (16) : Load 16-bit immediate data to specified register pair
:rp data (16)

Operation

Description
: This instruction loads immediate16 bit data specified within the instruction into register pair or stack pointer. The rp is 16-bit register pair
such as BC, DE, HL or 16-bit stack pointer.
No. of bytes

: 3 bytes
First byte : Opcode of LXI rp
Second byte: Low order byte of 16-bit data
Third byte: High order byte of 16-bit data.

No. of T- states : Requires 10 T- states for execution

Addressing mode: Immediate addressing.
Flags

: Flags are not affected.

Example

i. LXI B , 1020 H ; this instruction will load10H into B

: register and 20H into C register.
ii. LXI sp 27 FFH
STA addr

: this instruction will load 27FFH into stack pointer

: Store the contents of A register at address given within the instruction

:(addra) A

Description
: This instruction stores the contents of A register into the memory location whose address is directly specified within the instruction. The
contents of A register remain unchanged.
No of bytes : 3 bytes
First byte: Opcode of STA.
Second byte: Low order byte of the address
Third byte: High order byte of the address.

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No. of T-states : Requires13 T-states for execution
Addressing mode : Direct addressing.
Flags

; Flags are not affected

Example ; (2000H0=30H
LDA 2000H : This instruction will copy the
; contents of memory location
: 2000H i.edata 30H into the
: A regiser
9. SHLD addr : Store HL register pair in memory
: (addr) L and (addr+1) H

Operation

Description : This instruction storesthe contents of L register in the memory location given within the instruction and contents of H register at address next
to it. This instruction is used to store the contents of H and L register directly into the memory. The contents of the H and L register remain unchanged.
No of bytes : 3 bytes
First bytes : Opcode of SHLD
Second byte : Low order byte of the address
Third byte : High order byte of the address
No. of T- states

: Requires 16 T- states for execution

Addressing mode : Direct addressing

Flags

: flags are not affected.

Example

: H =30H .L =60H

SHLD 2500H : This instruction will copy

: the contents of L register at
; address 2500 H and the contents
; Of H register at address 2501 H
10.LHLD addr
Operation

: Load HL register pair from memory

: L (addr), H (addr+1)

Description : This instruction copiesthe contents of the memory location given with the instruction into the L register and the contents of the next memory
location into H register.
No.of bytes

; 3 bytes

First byte : opcode of HLD

Second byte: Low order byte of the address
Third byte: High order byte of the address
No. Of T-states: Requires 16 T- states for execution
Addressing mode : Direct addressing
Flag ; flags are not affected.
Example : (2500H0 =30H , (2501H) =60H
LHLD 2500H : this instruction will copy the
: contents of memory location 2500H

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: i.e. data 30H into the L register and
; the contents at memory location
; 2501 h i.e. data60H into the H register
11. STAX rp ; Store the contents of A register in memory location whose address is specified by BC or DE register pair
Operation : (rp) A
Description : This instruction copies the contents of accumulator into the memory location. Whose address is specified by the specified register pair. The rp is
BC or DE register pair. This register pair is used as a memory pointer. The contents of the accumulator remain unchanged.
No. of bytes ; 1 byte
Opcode of STAX rp
No.of T-states ; Requires7 T- states for execution
Addressing mode :Register indirect addressing
Flags : Flags are not affected
Example ; BC : 1020H , A = 50H
STAX B

: This instruction will copy the

; contents of A register (50H) to the
: memory location specified
: by BC register pair (1020H)

12. LDAX rp : Load A register with the contents of memory location whose address is specified by Bc or DE register pair.