International Conference on Recent Advances in Mechanical Engineering and Interdisciplinary Developments [ICRAMID - 2014]

Design and Implementation of a Novel

Bridgeless Interleaved SEPIC Converter for
LED Applications
Sreemallika.R

R.Seyezhai

PG scholar,
Department of EEE,
SSN College of Engineering,
Chennai, India
rsreemallika@gmail.com

Associate Professor,
Department of EEE,
SSN College of Engineering,
Chennai, India
seyezhair@ssn.edu.in

Abstract In the recent years, LED light sources are finding

more applications than traditional light sources due to their
outstanding characteristics. But the main concern is to have a
high quality power supply for driving LED. The Single Ended
Primary Inductance Converter (SEPIC) converter is more
popular for LED applications as it can be used as a single-stage
power conversion because we can achieve its output voltage lower
or higher than the input voltage and also a high power factor can
be achieved. This paper proposes a novel SEPIC power factor
correction converter for LED applications. Simulation has been
carried out using MATLAB/simulink. The results show that the
topology can achieve a high power factor close to unity. To
further improve the power factor, Average current control
technique is implemented. The system performance is evaluated
in terms of supply power factor, Distortion factor and supply
current THD. The results are compared with the conventional
SEPIC topology
KeywordsSEPIC, LED, Interleaved, Bridgeless, THD, Power
Factor, PFC, Average Current control

I. INTRODUCTION
LED Lighting technology is fast emerging in the recent
years. Around 19% of the electrical energy is consumed by
residential, commercial or industrial lighting worldwide.
Generally incandescent bulbs, halogen bulbs, fluorescent
lamps, compact fluorescent lamps (CFL), and high intensity
discharge (HID) lamps are used for lighting applications. With
the development of new materials and manufacture
procedures, LEDs are now attracting more and more attention
as they are eco-friendly, energy efficient, mercury-free,
difficult to break, long lifetime (10 times more than that of
CFL), high efficacy, less energy consumption, fast turn on/off
time and compact. [1]
It is a challenge for the engineers to develop high quality
LED power supplies in order to achieve a good performance
lighting system. So it has been a constant concern to maintain
the power factor as high as possible in order to have a high
power quality LED supply systems. The European standard
IEC 61000-3-2 mandates to stipulate the power factor for all
lighting products above 25 W [2]. For this purpose, switchmode DC-DC converters incorporate Power Factor Correction
(PFC) circuits to emulate a resistive behaviour of the
converter. This ensures a high power factor at the supply side
[3].Active switches are used in combination with reactive
elements to control the supply current so that the current
waveform follows exactly the supply voltage waveform and a
controllable output voltage is obtained. This is called active

power factor correction. The most popular active PFC

topology for LED applications is SEPIC Converter.
In this paper, a novel SEPIC converter called
Bridgeless Interleaved SEPIC converter is proposed and its
operation is discussed in section II. Section III presents the
average current control technique implemented for the
proposed converter to improve the power quality of supply
current. The simulation results and the comparison of
performance parameters of the proposed converter with the
conventional SEPIC converters are discussed in section IV.
II. BRIDGELESS INTERLEAVED SEPIC PFC CONVERTER
The proposed converter called Bridgeless Interleaved
SEPIC PFC topology combines the merits of both the
bridgeless topology and the interleaved structure. This
converter introduces two more diodes and two more
MOSFETs instead of two slow diodes used in the input diode
bridge rectifier. The input diode bridge rectifier is avoided in
the bridgeless configuration and hence the problem of heat
management is addressed. As fewer number of semiconductor
devices conduct in each cycle, the conduction losses are
greatly minimised. In the interleaved structure, SEPIC
converters operate in parallel with 180 out of phase. Here,
the input current is equal to the sum of the two input inductor
currents. So, the input ripple current is reduced as the
inductors ripple currents are out of phase and hence they tend
to cancel each other. The ripple frequency of the output
capacitor is reduced as well. [4]

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Fig.1.Bridgeless Interleaved SEPIC converter

International Conference on Recent Advances in Mechanical Engineering and Interdisciplinary Developments [ICRAMID - 2014]

The circuit diagram of Bridgeless Interleaved SEPIC converter

is shown in Fig.1. The circuit operation is divided into two
modes. During the positive half cycle, Q1/Q3 is turned on and
current flows through L1-Q1 and Q3-L3, returning to the line
and thus energy gets stored in L1 and L3. When Q1/Q3 are
turned off, L1 and L3 releases its stored energy and thus the
current flows through C1/C3, through the load and returns
through the body diode of Q3 back to the input mains. The
inductors L5/L7 connected to switches Q1/Q3 take energy from
the SEPIC capacitor C1 and C3. The output capacitor supplies
the load.
During the negative half cycle, Q4/Q2 is turned on and
current flows through L4 -Q4 and Q2-L2, returning to the line;
During this period, energy is stored in L4 and L2. When Q4/Q2
are turned off, L4 and L2 releases its stored energy and thus
current flows through C2/C4 , through the load and returns
through the body diode of Q2 back to the input mains. The
inductors L4 and L2 connected to switches Q4/Q2 take energy
from the SEPIC capacitor C2 and C4. The output capacitor
supplies the load. [4]

Selection of SEPIC Capacitor:

D Io
5
Vc fsw
where Vc is Capacitor Voltage Ripple and Io is the load
current.
C

B. Simulation Parameters
The simulation parameters for the proposed SEPIC PFC
converter are tabulated in Table 1.
TABLE I. SIMULATION PARAMETERS OF SEPIC RECTIFER

Parameter
Input Voltage
Switching Frequency
Duty Cycle
L1 , L2 , L3 , L4
L5 , L6 , L7 , L8
C1 , C2 , C3 ,C4
Output Capacitor
Output voltage

A. Design Considerations
The design of the proposed converter involves the selection of
duty cycle, inductor and SEPIC capacitors. The following
equations are used to design the proposed converter. [5]

Specification
24V,50Hz
25kHz
59%
2.8mH
4.03mH
6.7F
3200F
48V

III. AVERAGE CURRENT CONTROL TECHNIQUE FOR IMPROVING THE

QUALITY OF SUPPLY CURRENT

Selection of Duty cycle, D:

Vo
D
=
=M
Vin 1 D

(1)

where M is conversion ratio, Vo is Output voltage (V)

and Vin is Input Voltage (V) .

Selection of Inductor:
RL
L1c
2fsw M + M 2
L2c

M+1

(2)

(3)

For CCM mode, L1 > L1c ; L2 > L2c

where fsw is Switching Frequency (kHz).

Selection of Output Capacitor:

Co

Po
Vo 2Vo 2fs

(4)

where fs is supply frequency (Hz), Po is output power

(W) and Vo is change in output voltage.

The power factor is found to be the highest in case of

the bridgeless Interleaved SEPIC topology in the open loop
configuration. To improve the THD much more, closed loop
implementation i.e. forward and feedback loops are introduced
to shape the supply current. There are different current control
topologies discussed in the literature. But the widely adopted
technique is Average Current Mode Control (ACMC). Fig.2
shows the block diagram of the implementation of average
current control for the proposed converter.
The unique feature of ACMC is that it uses a high
gain, wide bandwidth Current Error Amplifier which forces the
average of the inductor current, to follow the current reference
with very small error. [6] It is a two loop control method. The
inner loop controls the shape of the inductor current. The outer
loop controls the output voltage; the output voltage level is
scaled and compared with the given reference. The error
voltage obtained is used to generate the current reference. The
current reference is so obtained such that it is the average of
the inductor current waveform. The reference current, Iref, is
obtained by multiplying a rectified input voltage by the voltage
controller output. The inductor current is compared with the
reference current and when the inductor current exceeds Iref,
power switch is turned off. The main feature of this control
technique is that it has good noise immunity and high degree
of accuracy [7]-[8].

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International Conference on Recent Advances in Mechanical Engineering and Interdisciplinary Developments [ICRAMID - 2014]

60

50

Output Voltage(V)

40

30

20

10

-10

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Time(sec)

Fig.4. Output Voltage of Bridgeless Interleaved SEPIC converter

The Simulation results for the implementation of Average

current control for Bridgeless Interleaved SEPIC converter are
shown in Fig.5 and Fig.6.
Supply Voltage(V) , Supply Current(A)

40

Fig.2. Average Current control of Bridgeless Interleaved SEPIC Converter

IV. SIMULATION RESULTS

30

20

10

-10

-20

-30

-40
0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Time(sec)

Supply Voltage (Volts) , Supply Current(A)

The simulation studies were carried out using

MATLAB/simulink. The results of the proposed converter in
open loop configuration are shown in Fig 3 and Fig 4.
40
30
20
10
0
-10
-20
-30
-40
0.02

0.03

0.04

0.05

0.06
Time(sec)

0.07

0.08

0.09

Fig.5 (a) Supply voltage and current (b) FFT Analysis of supply current
of Average current controlled Bridgeless Interleaved SEPIC Rectifier

0.1

60

Output Voltage(V)

50

40

30

20

10

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Time(sec)

Fig.6. Output voltage of Average current controlled Bridgeless

Interleaved SEPIC converter
Fig.3 (a) Supply voltage and current (b) FFT Analysis of supply current of
Bridgeless Interleaved SEPIC converter

It is obvious from Fig. 3 that the input current waveform is

very less distorted and the supply current harmonics are highly
reduced. The FFT analysis of the supply current shows that
the THD is about 6.26%. Fig.4 depicts the output voltage
waveform of 48V.

Fig.6 shows that the THD is 4.20% and hence it has a low
harmonic profile. So the power factor is better than its open
loop configuration.
V. PERFORMANCE PARAMETERS OF PFC TOPOLOGIES
The performance of a converter is evaluated in terms of
THD and power factor.

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International Conference on Recent Advances in Mechanical Engineering and Interdisciplinary Developments [ICRAMID - 2014]

a) Total Harmonic Distortion: (THD)

The Total Harmonic Distortion indicates how much the signal
is distorted w.r.t the fundamental component.
1
Kd =
(6)
1 + THD2
where K d is the distortion factor .

low THD. To improve the power quality much more, closed

loop control strategy i.e average current control is
implemented. To further improve the quality of supply
current, Peak current control, Hysteresis current control and
Non-linear current control can also be implemented.

b) Displacement Factor(K ):
The displacement factor K is the cosine of the displacement
angle () between the fundamental input current and the input
voltage.
K = cos
(7)
c) Power Factor(PF):
Here, Power Factor refers to the quality of supply current. In
case of non-sinusoidal signals, power factor is the product of
the distortion factor, K d and the displacement factor, K .
PF = K d K

(8)

Table II shows the comparison of the Bridgeless Interleaved

SEPIC Converter with the Conventional SEPIC Converters. It
can be inferred that the proposed SEPIC Converter has an
improved power factor and low harmonic profile compared to
the conventional SEPIC and bridgeless SEPIC converter.
TABLE II COMPARISON OF PERFORMANCE PARAMETERS OF SEPIC
CONVERTERS

Performance Parameters

Active PFC
Topology

THD
(%)

SEPIC
Bridgeless SEPIC
Bridgeless
Interleaved SEPIC

Power
Factor

16.79
9.35

0.9862
0.9956

0.9855
0.9781

0.9719
0.9738

6.26

0.9980

0.9903

0.9883

Table III compares the power factor obtained for open loop
and closed loop implementation for the proposed PFC
converter. It is observed that implementation of ACMC
improves the power factor to 0.9936.
TABLE III COMPARISON OF PERFORMANCE PARAMETERS OF BRIDGELESS
INTERLEAVED SEPIC CONVERTERS

Bridgeless
Interleaved
SEPIC Rectifier
Topology
Open Loop
Average Current
control

Performance Parameters
THD
(%)

Power
Factor

6.26

0.9980

0.9903

0.9883

4.20

0.9991

0.9945

0.9936

IV. CONCLUSION
This paper proposes a novel Bridgeless Interleaved
SEPIC converter for LED applications that provides an
improved power factor and a better harmonic profile. A
comparative analysis with the conventional SEPIC topology
has been done and it is significant from the simulation results
that the proposed converter exhibits better power factor and a

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REFERENCES
[1] Ye , Zhongming , Fred Greenfeld, and Zhixiang Liang. "Single-stage
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International Conference on Recent Advances in Mechanical Engineering and Interdisciplinary Developments [ICRAMID - 2014]

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